\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTOTRI : Automatic Transmitter Tristate
bits : 0 - 0 (1 bit)
access : read-write
DATABITS : Data-Bit Mode
bits : 1 - 1 (1 bit)
access : read-write
PARITY : Parity-Bit Mode
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x00000000 : NONE
Parity bits are not used
0x00000002 : EVEN
Even parity are used. Parity bits are automatically generated and checked by hardware.
0x00000003 : ODD
Odd parity is used. Parity bits are automatically generated and checked by hardware.
End of enumeration elements list.
STOPBITS : Stop-Bit Mode
bits : 4 - 4 (1 bit)
access : read-write
INV : Invert Input and Output
bits : 5 - 5 (1 bit)
access : read-write
ERRSDMA : Clear RX DMA on Error
bits : 6 - 6 (1 bit)
access : read-write
LOOPBK : Loopback Enable
bits : 7 - 7 (1 bit)
access : read-write
SFUBRX : Start-Frame UnBlock RX
bits : 8 - 8 (1 bit)
access : read-write
MPM : Multi-Processor Mode
bits : 9 - 9 (1 bit)
access : read-write
MPAB : Multi-Processor Address-Bit
bits : 10 - 10 (1 bit)
access : read-write
BIT8DV : Bit 8 Default Value
bits : 11 - 11 (1 bit)
access : read-write
RXDMAWU : RX DMA Wakeup
bits : 12 - 12 (1 bit)
access : read-write
TXDMAWU : TX DMA Wakeup
bits : 13 - 13 (1 bit)
access : read-write
TXDELAY : TX Delay Transmission
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0x00000000 : NONE
Frames are transmitted immediately
0x00000001 : SINGLE
Transmission of new frames are delayed by a single bit period
0x00000002 : DOUBLE
Transmission of new frames are delayed by two bit periods
0x00000003 : TRIPLE
Transmission of new frames are delayed by three bit periods
End of enumeration elements list.
Start Frame Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTFRAME : Start Frame
bits : 0 - 8 (9 bit)
access : read-write
Signal Frame Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGFRAME : Signal Frame
bits : 0 - 8 (9 bit)
access : read-write
Receive Buffer Data Extended Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 8 (9 bit)
access : read-only
PERR : Receive Data Parity Error
bits : 14 - 14 (1 bit)
access : read-only
FERR : Receive Data Framing Error
bits : 15 - 15 (1 bit)
access : read-only
Receive Buffer Data Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 7 (8 bit)
access : read-only
Receive Buffer Data Extended Peek Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATAP : RX Data Peek
bits : 0 - 8 (9 bit)
access : read-only
PERRP : Receive Data Parity Error Peek
bits : 14 - 14 (1 bit)
access : read-only
FERRP : Receive Data Framing Error Peek
bits : 15 - 15 (1 bit)
access : read-only
Transmit Buffer Data Extended Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 8 (9 bit)
access : read-write
TXBREAK : Transmit Data as Break
bits : 13 - 13 (1 bit)
access : read-write
TXDISAT : Disable TX After Transmission
bits : 14 - 14 (1 bit)
access : read-write
RXENAT : Enable RX After Transmission
bits : 15 - 15 (1 bit)
access : read-write
Transmit Buffer Data Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 7 (8 bit)
access : read-write
Interrupt Flag Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXC : TX Complete Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only
TXBL : TX Buffer Level Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only
RXDATAV : RX Data Valid Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only
RXOF : RX Overflow Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only
RXUF : RX Underflow Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-only
TXOF : TX Overflow Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-only
PERR : Parity Error Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-only
FERR : Framing Error Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only
MPAF : Multi-Processor Address Frame Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-only
STARTF : Start Frame Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-only
SIGF : Signal Frame Interrupt Flag
bits : 10 - 10 (1 bit)
access : read-only
Interrupt Flag Set Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXC : Set TXC Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only
RXOF : Set RXOF Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only
RXUF : Set RXUF Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only
TXOF : Set TXOF Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only
PERR : Set PERR Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only
FERR : Set FERR Interrupt Flag
bits : 7 - 7 (1 bit)
access : write-only
MPAF : Set MPAF Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only
STARTF : Set STARTF Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only
SIGF : Set SIGF Interrupt Flag
bits : 10 - 10 (1 bit)
access : write-only
Interrupt Flag Clear Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXC : Clear TXC Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only
RXOF : Clear RXOF Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only
RXUF : Clear RXUF Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only
TXOF : Clear TXOF Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only
PERR : Clear PERR Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only
FERR : Clear FERR Interrupt Flag
bits : 7 - 7 (1 bit)
access : write-only
MPAF : Clear MPAF Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only
STARTF : Clear STARTF Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only
SIGF : Clear SIGF Interrupt Flag
bits : 10 - 10 (1 bit)
access : write-only
Interrupt Enable Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXC : TXC Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
TXBL : TXBL Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
RXDATAV : RXDATAV Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
RXOF : RXOF Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
RXUF : RXUF Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
TXOF : TXOF Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
PERR : PERR Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
FERR : FERR Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
MPAF : MPAF Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
STARTF : STARTF Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
SIGF : SIGF Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Pulse Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PULSEW : Pulse Width
bits : 0 - 3 (4 bit)
access : read-write
PULSEEN : Pulse Generator/Extender Enable
bits : 4 - 4 (1 bit)
access : read-write
PULSEFILT : Pulse Filter
bits : 5 - 5 (1 bit)
access : read-write
Command Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXEN : Receiver Enable
bits : 0 - 0 (1 bit)
access : write-only
RXDIS : Receiver Disable
bits : 1 - 1 (1 bit)
access : write-only
TXEN : Transmitter Enable
bits : 2 - 2 (1 bit)
access : write-only
TXDIS : Transmitter Disable
bits : 3 - 3 (1 bit)
access : write-only
RXBLOCKEN : Receiver Block Enable
bits : 4 - 4 (1 bit)
access : write-only
RXBLOCKDIS : Receiver Block Disable
bits : 5 - 5 (1 bit)
access : write-only
CLEARTX : Clear TX
bits : 6 - 6 (1 bit)
access : write-only
CLEARRX : Clear RX
bits : 7 - 7 (1 bit)
access : write-only
Freeze Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGFREEZE : Register Update Freeze
bits : 0 - 0 (1 bit)
access : read-write
Synchronization Busy Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTRL : CTRL Register Busy
bits : 0 - 0 (1 bit)
access : read-only
CMD : CMD Register Busy
bits : 1 - 1 (1 bit)
access : read-only
CLKDIV : CLKDIV Register Busy
bits : 2 - 2 (1 bit)
access : read-only
STARTFRAME : STARTFRAME Register Busy
bits : 3 - 3 (1 bit)
access : read-only
SIGFRAME : SIGFRAME Register Busy
bits : 4 - 4 (1 bit)
access : read-only
TXDATAX : TXDATAX Register Busy
bits : 5 - 5 (1 bit)
access : read-only
TXDATA : TXDATA Register Busy
bits : 6 - 6 (1 bit)
access : read-only
PULSECTRL : PULSECTRL Register Busy
bits : 7 - 7 (1 bit)
access : read-only
I/O Routing Pin Enable Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXPEN : RX Pin Enable
bits : 0 - 0 (1 bit)
access : read-write
TXPEN : TX Pin Enable
bits : 1 - 1 (1 bit)
access : read-write
I/O Routing Location Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXLOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
End of enumeration elements list.
TXLOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
End of enumeration elements list.
LEUART Input Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXPRSSEL : RX PRS Channel Select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x00000000 : PRSCH0
PRS Channel 0 selected
0x00000001 : PRSCH1
PRS Channel 1 selected
0x00000002 : PRSCH2
PRS Channel 2 selected
0x00000003 : PRSCH3
PRS Channel 3 selected
0x00000004 : PRSCH4
PRS Channel 4 selected
0x00000005 : PRSCH5
PRS Channel 5 selected
0x00000006 : PRSCH6
PRS Channel 6 selected
0x00000007 : PRSCH7
PRS Channel 7 selected
0x00000008 : PRSCH8
PRS Channel 8 selected
0x00000009 : PRSCH9
PRS Channel 9 selected
0x0000000A : PRSCH10
PRS Channel 10 selected
0x0000000B : PRSCH11
PRS Channel 11 selected
0x0000000C : PRSCH12
PRS Channel 12 selected
0x0000000D : PRSCH13
PRS Channel 13 selected
0x0000000E : PRSCH14
PRS Channel 14 selected
0x0000000F : PRSCH15
PRS Channel 15 selected
End of enumeration elements list.
RXPRS : PRS RX Enable
bits : 5 - 5 (1 bit)
access : read-write
Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXENS : Receiver Enable Status
bits : 0 - 0 (1 bit)
access : read-only
TXENS : Transmitter Enable Status
bits : 1 - 1 (1 bit)
access : read-only
RXBLOCK : Block Incoming Data
bits : 2 - 2 (1 bit)
access : read-only
TXC : TX Complete
bits : 3 - 3 (1 bit)
access : read-only
TXBL : TX Buffer Level
bits : 4 - 4 (1 bit)
access : read-only
RXDATAV : RX Data Valid
bits : 5 - 5 (1 bit)
access : read-only
TXIDLE : TX Idle
bits : 6 - 6 (1 bit)
access : read-only
Clock Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Fractional Clock Divider
bits : 3 - 16 (14 bit)
access : read-write
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