\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
MCU Device ID Code Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEV_ID : Device Identifier
bits : 0 - 11 (12 bit)
REV_ID : Revision Identifier
bits : 16 - 31 (16 bit)
DBG configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_STOP : Debug Stop mode Debug options in Stop mode. Upon Stop mode exit, the software must re-establish the desired clock configuration.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
All clocks disabled, including FCLK and HCLK. Upon Stop mode exit, the CPU is clocked by the HSI internal RC oscillator.
0x1 : B_0x1
FCLK and HCLK running, derived from the internal RC oscillator remaining active. If Systick is enabled, it may generate periodic interrupt and wake up events.
End of enumeration elements list.
DBG_STANDBY : Debug Standby and Shutdown modes Debug options in Standby or Shutdown mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Digital part powered. From software point of view, exiting Standby and Shutdown modes is identical as fetching reset vector (except for status bits indicating that the MCU exits Standby)
0x1 : B_0x1
Digital part powered and FCLK and HCLK running, derived from the internal RC oscillator remaining active. The MCU generates a system reset so that exiting Standby and Shutdown has the same effect as starting from reset.
End of enumeration elements list.
DBG APB freeze register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_TIM2_STOP : Clocking of TIM2 counter when the core is halted This bit enables/disables the clock to the counter of TIM2 when the core is halted:
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Enable
0x1 : B_0x1
Disable
End of enumeration elements list.
DBG_TIM3_STOP : Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted:
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Enable
0x1 : B_0x1
Disable
End of enumeration elements list.
DBG_TIM6_STOP : Clocking of TIM6 counter when the core is halted This bit enables/disables the clock to the counter of TIM6 when the core is halted:
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Enable
0x1 : B_0x1
Disable
End of enumeration elements list.
DBG_TIM7_STOP : Clocking of TIM7 counter when the core is halted. This bit enables/disables the clock to the counter of ITIM7 when the core is halted:
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Enable
0x1 : B_0x1
Disable
End of enumeration elements list.
DBG_RTC_STOP : Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted:
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Enable
0x1 : B_0x1
Disable
End of enumeration elements list.
DBG_WWDG_STOP : Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted:
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Enable
0x1 : B_0x1
Disable
End of enumeration elements list.
DBG_IWDG_STOP : Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted:
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Enable
0x1 : B_0x1
Disable
End of enumeration elements list.
DBG_I2C1_SMBUS_TIMEOUT : SMBUS timeout when core is halted
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Same behavior as in normal mode
0x1 : B_0x1
The SMBUS timeout is frozen
End of enumeration elements list.
DBG_LPTIM2_STOP : Clocking of LPTIMER2 counter when the core is halted This bit enables/disables the clock to the counter of LPTIMER2 when the core is halted:
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Enable
0x1 : B_0x1
Disable
End of enumeration elements list.
DBG_LPTIM1_STOP : Clocking of LPTIMER1 counter when the core is halted This bit enables/disables the clock to the counter of LPTIMER1 when the core is halted:
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Enable
0x1 : B_0x1
Disable
End of enumeration elements list.
DBG APB freeze register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_TIM1_STOP : Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted:
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Enable
0x1 : B_0x1
Disable
End of enumeration elements list.
DBG_TIM14_STOP : Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted:
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Enable
0x1 : B_0x1
Disable
End of enumeration elements list.
DBG_TIM15_STOP : Clocking of TIM15 counter when the core is halted This bit enables/disables the clock to the counter of TIM15 when the core is halted: Only available on STM32G071xx and STM32G081xx, reserved on STM32G031xx and STM32G041xx.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Enable
0x1 : B_0x1
Disable
End of enumeration elements list.
DBG_TIM16_STOP : Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted:
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Enable
0x1 : B_0x1
Disable
End of enumeration elements list.
DBG_TIM17_STOP : Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted:
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Enable
0x1 : B_0x1
Disable
End of enumeration elements list.
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