AES_CR (CR)

AES_KEYR0 (KEYR0)

AES_KEYR1 (KEYR1)

AES_KEYR2 (KEYR2)

AES_KEYR3 (KEYR3)

AES_IVR0 (IVR0)

AES_IVR1 (IVR1)

AES_IVR2 (IVR2)

AES_IVR3 (IVR3)

AES_KEYR4 (KEYR4)

AES_KEYR5 (KEYR5)

AES_KEYR6 (KEYR6)

AES_KEYR7 (KEYR7)

AES_SR (SR)

AES_SUSP0R (SUSP0R)

AES_SUSP1R (SUSP1R)

AES_SUSP2R (SUSP2R)

AES_SUSP3R (SUSP3R)

AES_SUSP4R (SUSP4R)

AES_SUSP5R (SUSP5R)

AES_SUSP6R (SUSP6R)

AES_SUSP7R (SUSP7R)

AES_DINR (DINR)

AES_DOUTR (DOUTR)

EN : AES enable This bit enables/disables the AES peripheral: At any moment, clearing then setting the bit re-initializes the AES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATATYPE : Data type selection This bitfield defines the format of data written in the AES_DINR register or read from the AES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE : AES operating mode This bitfield selects the AES operating mode: Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. Any attempt to selecting Mode 4 while either ECB or CBC chaining mode is not selected, defaults to effective selection of Mode 3. It is not possible to select a Mode 3 following a Mode 4.
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHMOD1 : Chaining mode selection, bit [2] Refer to the bits [5:6] of the register for the description of the CHMOD[2:0] bitfield CHMOD[1:0]: Chaining mode selection, bits [1:0] This bitfield, together with the bit CHMOD[2] forming CHMOD[2:0], selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CCFC : Computation complete flag clear Upon written to 1, this bit clears the computation complete flag (CCF) in the AES_SR register: Reading the flag always returns zero.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERRC : Error flag clear Upon written to 1, this bit clears the RDERR and WRERR error flags in the AES_SR register: Reading the flag always returns zero.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CCFIE : CCF interrupt enable This bit enables or disables (masks) the AES interrupt generation when CCF (computation complete flag) is set:
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERRIE : Error interrupt enable This bit enables or disables (masks) the AES interrupt generation when RDERR and/or WRERR is set:
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMAINEN : DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by AES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). Usage of DMA with Mode 4 (single decryption) is not recommended.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMAOUTEN : DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by AES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). Usage of DMA with Mode 4 (single decryption) is not recommended.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GCMPH : GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield).
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHMOD2 : Chaining mode selection, bit [2] Refer to the bits [5:6] of the register for the description of the CHMOD[2:0] bitfield CHMOD[1:0]: Chaining mode selection, bits [1:0] This bitfield, together with the bit CHMOD[2] forming CHMOD[2:0], selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

KEYSIZE : Key size selection This bitfield defines the length of the key used in the AES cryptographic core, in bits: Attempts to write the bit are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NPBLB : Number of padding bytes in last block The bitfield sets the number of padding bytes in last block of payload: ...
bits : 20 - 23 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

KEY : Cryptographic key, bits [31:0] This bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode: - In Mode 1 (encryption), Mode 2 (key derivation) and Mode 4 (key derivation then single decryption): the value to write into the bitfield is the encryption key. - In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before being used for decryption. After writing the encryption key into the bitfield, its reading before enabling AES returns the same value. Its reading after enabling AES and after the CCF flag is set returns the decryption key derived from the encryption key. Note: In mode 4 (key derivation then single decryption) the bitfield always contains the encryption key. The AES_KEYRx registers may be written only when KEYSIZE value is correct and when the AES peripheral is disabled (EN bit of the AES_CR register cleared). Note that, if, the key is directly loaded to AES_KEYRx registers (hence writes to key register is ignored and KEIF is set). Refer to for more details.
bits : 0 - 31 (32 bit)
access : read-write

KEY : Cryptographic key, bits [63:32] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
bits : 0 - 31 (32 bit)
access : read-write

KEY : Cryptographic key, bits [95:64] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
bits : 0 - 31 (32 bit)
access : read-write

KEY : Cryptographic key, bits [127:96] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
bits : 0 - 31 (32 bit)
access : read-write

IVI : Initialization vector input, bits [31:0] Refer to for description of the IVI[127:0] bitfield. The initialization vector is only used in chaining modes other than ECB. The AES_IVRx registers may be written only when the AES peripheral is disabled
bits : 0 - 31 (32 bit)
access : read-write

IVI : Initialization vector input, bits [63:32] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.
bits : 0 - 31 (32 bit)
access : read-write

IVI : Initialization vector input, bits [95:64] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.
bits : 0 - 31 (32 bit)
access : read-write

IVI : Initialization vector input, bits [127:96] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.
bits : 0 - 31 (32 bit)
access : read-write

KEY : Cryptographic key, bits [159:128] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
bits : 0 - 31 (32 bit)
access : read-write

KEY : Cryptographic key, bits [191:160] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
bits : 0 - 31 (32 bit)
access : read-write

KEY : Cryptographic key, bits [223:192] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
bits : 0 - 31 (32 bit)
access : read-write

KEY : Cryptographic key, bits [255:224] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
bits : 0 - 31 (32 bit)
access : read-write

CCF : Computation completed flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCFC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the AES_CR register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RDERR : Read error flag This flag indicates the detection of an unexpected read operation from the AES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register. The flag setting has no impact on the AES operation. Unexpected read returns zero.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

WRERR : Write error This flag indicates the detection of an unexpected write operation to the AES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register. The flag setting has no impact on the AES operation. Unexpected write is ignored.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUSY : Busy This flag indicates whether AES is idle or busy during GCM payload encryption phase: When the flag indicates “idle”, the current GCM encryption processing may be suspended to process a higher-priority message. In other chaining modes, or in GCM phases other than payload encryption, the flag must be ignored for the suspend process.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SUSP : AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers.
bits : 0 - 31 (32 bit)
access : read-write

SUSP : AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers.
bits : 0 - 31 (32 bit)
access : read-write

SUSP : AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers.
bits : 0 - 31 (32 bit)
access : read-write

SUSP : AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers.
bits : 0 - 31 (32 bit)
access : read-write

SUSP : AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers.
bits : 0 - 31 (32 bit)
access : read-write

SUSP : AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers.
bits : 0 - 31 (32 bit)
access : read-write

SUSP : AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers.
bits : 0 - 31 (32 bit)
access : read-write

SUSP : AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers.
bits : 0 - 31 (32 bit)
access : read-write

DIN : Input data word A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the AES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 128-bit input buffer. The data signification of the input data block depends on the AES operating mode: - Mode 1 (encryption): plaintext - Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for input) - Mode 3 (decryption) and Mode 4 (key derivation then single decryption): ciphertext The data swap operation is described in page 499.
bits : 0 - 31 (32 bit)
access : read-write

DOUT : Output data word This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the AES peripheral. Before reaching the output buffer, the data produced by the AES core are handled by the data swap block according to the DATATYPE[1:0] bitfield. Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0]. The data signification of the output data block depends on the AES operating mode: - Mode 1 (encryption): ciphertext - Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for output) - Mode 3 (decryption) and Mode 4 (key derivation then single decryption): plaintext The data swap operation is described in page 499.
bits : 0 - 31 (32 bit)
access : read-only