\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initialize
bits : 0 - 0 (1 bit)
access : read-write
IE : Module Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
SIE : Status Change Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
EIE : Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
DAR : Disable Automatic Retransmission
bits : 5 - 5 (1 bit)
access : read-write
CCE : Configuration Change Enable
bits : 6 - 6 (1 bit)
access : read-write
TEST : Test Mode Enable Write
bits : 7 - 7 (1 bit)
access : read-write
Interrupt Identification Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTID : Interrupt Identifier
bits : 0 - 5 (6 bit)
access : read-only
INTSTAT : Status Interupt
bits : 15 - 15 (1 bit)
access : read-only
Test Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASIC : Basic Mode
bits : 2 - 2 (1 bit)
access : read-write
SILENT : Silent Mode
bits : 3 - 3 (1 bit)
access : read-write
LBACK : Loopback Mode
bits : 4 - 4 (1 bit)
access : read-write
TX : Control of CAN_TX Pin
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x00000000 : CORE
Reset value, CAN_TX is controlled by the CAN Core.
0x00000001 : SAMPT
Sample Point can be monitored at CAN_TX pin.
0x00000002 : LOW
CAN_TX pin drives a dominant bit (0) value.
0x00000003 : HIGH
CAN_TX pin drives a recessive bit (1) value.
End of enumeration elements list.
RX : Monitors the Actual Value of CAN_RX Pin
bits : 7 - 7 (1 bit)
access : read-only
BRP Extension Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRPE : Baud Rate Prescaler Extension
bits : 0 - 3 (4 bit)
access : read-write
Transmission Request Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXRQSTOUT : Transmission Request Bits (Of All Message Objects)
bits : 0 - 31 (32 bit)
access : read-only
Enumeration:
0x00000000 : FALSE
This Message Object is not waiting for transmission.
0x00000001 : TRUE
The transmission of this Message Object is requested and is not yet done.
End of enumeration elements list.
New Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALID : DATAVALID Bits (of All Message Objects)
bits : 0 - 31 (32 bit)
access : read-only
Message Valid Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALID : Message Valid Bits (of All Message Objects)
bits : 0 - 31 (32 bit)
access : read-only
Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGHALT : Debug Halt
bits : 15 - 15 (1 bit)
access : read-write
Message Object Interrupt Flag Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MESSAGE : Message Object Interrupt Flag
bits : 0 - 31 (32 bit)
access : read-only
Message Object Interrupt Flag Set Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MESSAGE : Set MESSAGE Interrupt Flag
bits : 0 - 31 (32 bit)
access : write-only
Message Object Interrupt Flag Clear Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MESSAGE : Clear MESSAGE Interrupt Flag
bits : 0 - 31 (32 bit)
access : write-only
Message Object Interrupt Enable Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MESSAGE : MESSAGE Interrupt Enable
bits : 0 - 31 (32 bit)
access : read-write
Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEC : Last Error Code
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No error occurred during last CAN bus event.
0x00000001 : STUFF
More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
0x00000002 : FORM
A fixed format part of a received frame has the wrong format.
0x00000003 : ACK
The message this CAN Core transmitted was not acknowledged by another node.
0x00000004 : BIT1
During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant.
0x00000005 : BIT0
During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored Bus value was recessive. During Bus Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).
0x00000006 : CRC
The CRC check sum was incorrect in the message received the CRC received for an incoming message does not match with the calculated CRC for the received data.
0x00000007 : UNUSED
When the LEC shows the value '7', no CAN bus event was detected since the CPU wrote this value to the LEC.
End of enumeration elements list.
TXOK : Transmitted a Message Successfully
bits : 3 - 3 (1 bit)
access : read-write
RXOK : Received a Message Successfully
bits : 4 - 4 (1 bit)
access : read-write
EPASS : Error Passive
bits : 5 - 5 (1 bit)
access : read-only
EWARN : Warning Status
bits : 6 - 6 (1 bit)
access : read-only
BOFF : Bus Off Status
bits : 7 - 7 (1 bit)
access : read-only
Status Interrupt Flag Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATUS : Status Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only
Message Object Interrupt Flag Set Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
STATUS : Set STATUS Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only
Message Object Interrupt Flag Clear Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
STATUS : Clear STATUS Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only
Status Interrupt Enable Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATUS : STATUS Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
I/O Routing Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPEN : TX Pin Enable
bits : 0 - 0 (1 bit)
access : read-write
RXLOC : RX Pin Location
bits : 2 - 7 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
End of enumeration elements list.
TXLOC : TX Pin Location
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
End of enumeration elements list.
Interface Command Mask Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAB : CC Channel Mode
bits : 0 - 0 (1 bit)
access : read-write
DATAA : Access Data Bytes 0-3
bits : 1 - 1 (1 bit)
access : read-write
TXRQSTNEWDAT : Transmission Request Bit/ New Data Bit
bits : 2 - 2 (1 bit)
access : read-write
CLRINTPND : Clear Interrupt Pending Bit
bits : 3 - 3 (1 bit)
access : read-write
CONTROL : Access Control Bits
bits : 4 - 4 (1 bit)
access : read-write
ARBACC : Access Arbitration Bits
bits : 5 - 5 (1 bit)
access : read-write
MASKACC : Access Mask Bits
bits : 6 - 6 (1 bit)
access : read-write
WRRD : Write/Read RAM
bits : 7 - 7 (1 bit)
access : read-write
Interface Mask Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Identifier Mask
bits : 0 - 28 (29 bit)
access : read-write
MDIR : Mask Message Direction
bits : 30 - 30 (1 bit)
access : read-write
MXTD : Mask Extended Identifier
bits : 31 - 31 (1 bit)
access : read-write
Interface Arbitration Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Message Identifier
bits : 0 - 28 (29 bit)
access : read-write
DIR : Message Direction
bits : 29 - 29 (1 bit)
access : read-write
XTD : Extended Identifier
bits : 30 - 30 (1 bit)
access : read-write
MSGVAL : Message Valid
bits : 31 - 31 (1 bit)
access : read-write
Interface Message Control Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLC : Data Length Code
bits : 0 - 3 (4 bit)
access : read-write
EOB : End of Buffer
bits : 7 - 7 (1 bit)
access : read-write
TXRQST : Transmit Request
bits : 8 - 8 (1 bit)
access : read-write
RMTEN : Remote Enable
bits : 9 - 9 (1 bit)
access : read-write
RXIE : Receive Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
TXIE : Transmit Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
UMASK : Use Acceptance Mask
bits : 12 - 12 (1 bit)
access : read-write
INTPND : Interrupt Pending
bits : 13 - 13 (1 bit)
access : read-write
MESSAGEOF : Message Lost (only Valid for Message Objects With Direction = Receive)
bits : 14 - 14 (1 bit)
access : read-write
DATAVALID : New Data
bits : 15 - 15 (1 bit)
access : read-write
Interface Data a Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : First Byte of CAN Data Frame
bits : 0 - 7 (8 bit)
access : read-write
DATA1 : Second Byte of CAN Data Frame
bits : 8 - 15 (8 bit)
access : read-write
DATA2 : Third Byte of CAN Data Frame
bits : 16 - 23 (8 bit)
access : read-write
DATA3 : Fourth Byte of CAN Data Frame
bits : 24 - 31 (8 bit)
access : read-write
Interface Data B Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA4 : Fifth Byte of CAN Data Frame
bits : 0 - 7 (8 bit)
access : read-write
DATA5 : Sixth Byte of CAN Data Frame
bits : 8 - 15 (8 bit)
access : read-write
DATA6 : Seventh Byte of CAN Data Frame
bits : 16 - 23 (8 bit)
access : read-write
DATA7 : Eight Byte of CAN Data Frame
bits : 24 - 31 (8 bit)
access : read-write
Interface Command Request Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSGNUM : Message Number
bits : 0 - 5 (6 bit)
access : read-write
BUSY : Busy Flag
bits : 15 - 15 (1 bit)
access : read-only
Error Count Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEC : Transmit Error Counter
bits : 0 - 7 (8 bit)
access : read-only
REC : Receive Error Counter
bits : 8 - 14 (7 bit)
access : read-only
RECERRP : Receive Error Passive
bits : 15 - 15 (1 bit)
access : read-only
Interface Command Mask Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAB : CC Channel Mode
bits : 0 - 0 (1 bit)
access : read-write
DATAA : Access Data Bytes 0-3
bits : 1 - 1 (1 bit)
access : read-write
TXRQSTNEWDAT : Transmission Request Bit/ New Data Bit
bits : 2 - 2 (1 bit)
access : read-write
CLRINTPND : Clear Interrupt Pending Bit
bits : 3 - 3 (1 bit)
access : read-write
CONTROL : Access Control Bits
bits : 4 - 4 (1 bit)
access : read-write
ARBACC : Access Arbitration Bits
bits : 5 - 5 (1 bit)
access : read-write
MASKACC : Access Mask Bits
bits : 6 - 6 (1 bit)
access : read-write
WRRD : Write/Read RAM
bits : 7 - 7 (1 bit)
access : read-write
Interface Mask Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Identifier Mask
bits : 0 - 28 (29 bit)
access : read-write
MDIR : Mask Message Direction
bits : 30 - 30 (1 bit)
access : read-write
MXTD : Mask Extended Identifier
bits : 31 - 31 (1 bit)
access : read-write
Interface Arbitration Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Message Identifier
bits : 0 - 28 (29 bit)
access : read-write
DIR : Message Direction
bits : 29 - 29 (1 bit)
access : read-write
XTD : Extended Identifier
bits : 30 - 30 (1 bit)
access : read-write
MSGVAL : Message Valid
bits : 31 - 31 (1 bit)
access : read-write
Interface Message Control Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLC : Data Length Code
bits : 0 - 3 (4 bit)
access : read-write
EOB : End of Buffer
bits : 7 - 7 (1 bit)
access : read-write
TXRQST : Transmit Request
bits : 8 - 8 (1 bit)
access : read-write
RMTEN : Remote Enable
bits : 9 - 9 (1 bit)
access : read-write
RXIE : Receive Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
TXIE : Transmit Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
UMASK : Use Acceptance Mask
bits : 12 - 12 (1 bit)
access : read-write
INTPND : Interrupt Pending
bits : 13 - 13 (1 bit)
access : read-write
MESSAGEOF : Message Lost (only Valid for Message Objects With Direction = Receive)
bits : 14 - 14 (1 bit)
access : read-write
DATAVALID : New Data
bits : 15 - 15 (1 bit)
access : read-write
Interface Data a Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : First Byte of CAN Data Frame
bits : 0 - 7 (8 bit)
access : read-write
DATA1 : Second Byte of CAN Data Frame
bits : 8 - 15 (8 bit)
access : read-write
DATA2 : Third Byte of CAN Data Frame
bits : 16 - 23 (8 bit)
access : read-write
DATA3 : Fourth Byte of CAN Data Frame
bits : 24 - 31 (8 bit)
access : read-write
Interface Data B Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA4 : Fifth Byte of CAN Data Frame
bits : 0 - 7 (8 bit)
access : read-write
DATA5 : Sixth Byte of CAN Data Frame
bits : 8 - 15 (8 bit)
access : read-write
DATA6 : Seventh Byte of CAN Data Frame
bits : 16 - 23 (8 bit)
access : read-write
DATA7 : Eight Byte of CAN Data Frame
bits : 24 - 31 (8 bit)
access : read-write
Interface Command Request Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSGNUM : Message Number
bits : 0 - 5 (6 bit)
access : read-write
BUSY : Busy Flag
bits : 15 - 15 (1 bit)
access : read-only
Bit Timing Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRP : Baud Rate Prescaler
bits : 0 - 5 (6 bit)
access : read-write
SJW : Synchronization Jump Width
bits : 6 - 7 (2 bit)
access : read-write
TSEG1 : Time Segment Before the Sample Point
bits : 8 - 11 (4 bit)
access : read-write
TSEG2 : Time Segment After the Sample Point
bits : 12 - 14 (3 bit)
access : read-write
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