\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
IP Version ID
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP VERSION
bits : 0 - 31 (32 bit)
access : read-only
PDM Status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACT : PDM is active
bits : 0 - 0 (1 bit)
access : read-only
FULL : FIFO FULL Status
bits : 4 - 4 (1 bit)
access : read-only
EMPTY : FIFO EMPTY Status
bits : 5 - 5 (1 bit)
access : read-only
FIFOCNT : FIFO CNT
bits : 8 - 10 (3 bit)
access : read-only
PDM Core Configuration Register0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORDER : Filter order
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x00000000 : SECOND
Second order filter.
0x00000001 : THIRD
Third order filter.
0x00000002 : FOURTH
Fourth order filter.
0x00000003 : FIFTH
Fifth order filter.
End of enumeration elements list.
NUMCH : Number of Channels
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Only one Channel.
0x00000001 : TWO
Two Channels.
0x00000002 : THREE
Three Channels.
0x00000003 : FOUR
Four Channels.
End of enumeration elements list.
DATAFORMAT : Filter output format
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x00000000 : RIGHT16
Right aligned 16-bit, left bits are sign extended.
0x00000001 : DOUBLE16
Pack two 16-bit samples into one 32-bit word.
0x00000002 : RIGHT24
Right aligned 24bit, left bits are sign extended.
0x00000003 : FULL32BIT
32 bit data.
0x00000004 : LEFT16
Left aligned 16-bit, right bits are zeros.
0x00000005 : LEFT24
Left aligned 24-bit, right bits are zeros.
0x00000006 : RAW32BIT
RAW 32 bit data from Integrator.
End of enumeration elements list.
FIFODVL : Data Valid level in FIFO
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Atleast one word.
0x00000001 : TWO
Two words.
0x00000002 : THREE
Three words.
0x00000003 : FOUR
Four words.
End of enumeration elements list.
STEREOMODECH01 : Stereo mode CH01
bits : 16 - 16 (1 bit)
access : read-write
STEREOMODECH23 : Stereo mode CH23
bits : 17 - 17 (1 bit)
access : read-write
CH0CLKPOL : CH0 CLK Polarity
bits : 24 - 24 (1 bit)
access : read-write
CH1CLKPOL : CH1 CLK Polarity
bits : 25 - 25 (1 bit)
access : read-write
CH2CLKPOL : CH2 CLK Polarity
bits : 26 - 26 (1 bit)
access : read-write
CH3CLKPOL : CH3 CLK Polarity
bits : 27 - 27 (1 bit)
access : read-write
PDM Core Configuration Register1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : Prescalar Setting for PDM sample
bits : 0 - 9 (10 bit)
access : read-write
PDM Received Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : PDM received data
bits : 0 - 31 (32 bit)
access : read-only
PDM Module enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Module enable
bits : 0 - 0 (1 bit)
access : read-write
Interrupt Flag Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DV : Data Valid Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only
DVL : Data Valid Level Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only
OF : FIFO Overflow Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only
UF : FIFO Undeflow Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only
Interrupt Flag Set Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DV : Set DV Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only
DVL : Set DVL Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only
OF : Set OF Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only
UF : Set UF Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only
Interrupt Flag Clear Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DV : Clear DV Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only
DVL : Clear DVL Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only
OF : Clear OF Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only
UF : Clear UF Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only
Interrupt Enable Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DV : DV Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
DVL : DVL Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
OF : OF Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
UF : UF Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
I/O LOCATION Enable Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAT0PEN : DAT0 I/O Enable
bits : 0 - 0 (1 bit)
access : read-write
DAT1PEN : DAT1 I/O Enable
bits : 1 - 1 (1 bit)
access : read-write
DAT2PEN : DAT2 I/O Enable
bits : 2 - 2 (1 bit)
access : read-write
DAT3PEN : DAT3 I/O Enable
bits : 3 - 3 (1 bit)
access : read-write
CLKPEN : CLK I/O Enable
bits : 8 - 8 (1 bit)
access : read-write
I/O LOCATION Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAT0LOC : I/O Location for DAT0 pins
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
End of enumeration elements list.
DAT1LOC : I/O Location for DAT1 pins
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
End of enumeration elements list.
DAT2LOC : I/O Location for DAT2 pins
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
End of enumeration elements list.
DAT3LOC : I/O Location for DAT3 pins
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
End of enumeration elements list.
I/O LOCATION Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKLOC : I/O Location for CLK pin
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
End of enumeration elements list.
Synchronization Busy Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STARTBUSY : START sync busy
bits : 0 - 0 (1 bit)
access : read-only
STOPBUSY : STOP sync busy
bits : 1 - 1 (1 bit)
access : read-only
CLEARBUSY : CLEAR sync busy
bits : 2 - 2 (1 bit)
access : read-only
FIFOFLBUSY : FIFO Flush Sync busy
bits : 3 - 3 (1 bit)
access : read-only
PRESCBUSY : PRESC Sync busy
bits : 8 - 8 (1 bit)
access : read-only
CTRLREGBUSY : CTRLREGBUSY busy
bits : 10 - 10 (1 bit)
access : read-only
PDM Core Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAIN : Selects Gain factor of DCF
bits : 0 - 4 (5 bit)
access : read-write
DSR : Down sampling rate of Decimation filter
bits : 8 - 19 (12 bit)
access : read-write
OUTCLKEN : PDM Clock enable
bits : 31 - 31 (1 bit)
access : read-write
PDM Core Command Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
START : Start DCF
bits : 0 - 0 (1 bit)
access : write-only
STOP : Stop DCF
bits : 4 - 4 (1 bit)
access : write-only
CLEAR : Clear DCF
bits : 8 - 8 (1 bit)
access : write-only
FIFOFL : FIFO Flush
bits : 16 - 16 (1 bit)
access : write-only
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