\n

GTZC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TZSC_CR

TZSC_SECCFGR1

TZSC_SECCFGR2

TZSC_PRIVCFGR1

TZSC_PRIVCFGR2

TZSC_MPCWM1_NSWMR1

TZSC_MPCWM1_NSWMR2

TZSC_MPCWM2_NSWMR1

TZSC_MPCWM2_NSWMR2

TZSC_MPCWM3_NSWMR1


TZSC_CR

TZSC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_CR TZSC_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCK

LCK : LCK
bits : 0 - 0 (1 bit)


TZSC_SECCFGR1

TZSC secure configuration register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_SECCFGR1 TZSC_SECCFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2SEC TIM3SEC TIM4SEC TIM5SEC TIM6SEC TIM7SEC WWDGSEC IWDGSEC SPI2SEC SPI3SEC USART2SEC USART3SEC UART4SEC UART5SEC I2C1SEC I2C2SEC I2C3SEC CRSSEC DACSEC OPAMPSEC LPTIM1SEC LPUART1SEC I2C4SEC LPTIM2SEC LPTIM3SEC FDCAN1SEC USBFSSEC UCPD1SEC VREFBUFSEC COMPSEC TIM1SEC SPI1SEC

TIM2SEC : TIM2SEC
bits : 0 - 0 (1 bit)

TIM3SEC : TIM3SEC
bits : 1 - 1 (1 bit)

TIM4SEC : TIM4SEC
bits : 2 - 2 (1 bit)

TIM5SEC : TIM5SEC
bits : 3 - 3 (1 bit)

TIM6SEC : TIM6SEC
bits : 4 - 4 (1 bit)

TIM7SEC : TIM7SEC
bits : 5 - 5 (1 bit)

WWDGSEC : WWDGSEC
bits : 6 - 6 (1 bit)

IWDGSEC : IWDGSEC
bits : 7 - 7 (1 bit)

SPI2SEC : SPI2SEC
bits : 8 - 8 (1 bit)

SPI3SEC : SPI3SEC
bits : 9 - 9 (1 bit)

USART2SEC : USART2SEC
bits : 10 - 10 (1 bit)

USART3SEC : USART3SEC
bits : 11 - 11 (1 bit)

UART4SEC : UART4SEC
bits : 12 - 12 (1 bit)

UART5SEC : UART5SEC
bits : 13 - 13 (1 bit)

I2C1SEC : I2C1SEC
bits : 14 - 14 (1 bit)

I2C2SEC : I2C2SEC
bits : 15 - 15 (1 bit)

I2C3SEC : I2C3SEC
bits : 16 - 16 (1 bit)

CRSSEC : CRSSEC
bits : 17 - 17 (1 bit)

DACSEC : DACSEC
bits : 18 - 18 (1 bit)

OPAMPSEC : OPAMPSEC
bits : 19 - 19 (1 bit)

LPTIM1SEC : LPTIM1SEC
bits : 20 - 20 (1 bit)

LPUART1SEC : LPUART1SEC
bits : 21 - 21 (1 bit)

I2C4SEC : I2C4SEC
bits : 22 - 22 (1 bit)

LPTIM2SEC : LPTIM2SEC
bits : 23 - 23 (1 bit)

LPTIM3SEC : LPTIM3SEC
bits : 24 - 24 (1 bit)

FDCAN1SEC : FDCAN1SEC
bits : 25 - 25 (1 bit)

USBFSSEC : USBFSSEC
bits : 26 - 26 (1 bit)

UCPD1SEC : UCPD1SEC
bits : 27 - 27 (1 bit)

VREFBUFSEC : VREFBUFSEC
bits : 28 - 28 (1 bit)

COMPSEC : COMPSEC
bits : 29 - 29 (1 bit)

TIM1SEC : TIM1SEC
bits : 30 - 30 (1 bit)

SPI1SEC : SPI1SEC
bits : 31 - 31 (1 bit)


TZSC_SECCFGR2

TZSC secure configuration register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_SECCFGR2 TZSC_SECCFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM8SEC USART1SEC TIM15SEC TIM16SEC TIM17SEC SAI1SEC SAI2SEC DFSDM1SEC CRCSEC TSCSEC ICACHESEC ADCSEC AESSEC HASHSEC RNGSEC PKASEC SDMMC1SEC FSMC_REGSEC OCTOSPI1_REGSEC

TIM8SEC : TIM8SEC
bits : 0 - 0 (1 bit)

USART1SEC : USART1SEC
bits : 1 - 1 (1 bit)

TIM15SEC : TIM15SEC
bits : 2 - 2 (1 bit)

TIM16SEC : TIM16SEC
bits : 3 - 3 (1 bit)

TIM17SEC : TIM17SEC
bits : 4 - 4 (1 bit)

SAI1SEC : SAI1SEC
bits : 5 - 5 (1 bit)

SAI2SEC : SAI2SEC
bits : 6 - 6 (1 bit)

DFSDM1SEC : DFSDM1SEC
bits : 7 - 7 (1 bit)

CRCSEC : CRCSEC
bits : 8 - 8 (1 bit)

TSCSEC : TSCSEC
bits : 9 - 9 (1 bit)

ICACHESEC : ICACHESEC
bits : 10 - 10 (1 bit)

ADCSEC : ADCSEC
bits : 11 - 11 (1 bit)

AESSEC : AESSEC
bits : 12 - 12 (1 bit)

HASHSEC : HASHSEC
bits : 13 - 13 (1 bit)

RNGSEC : RNGSEC
bits : 14 - 14 (1 bit)

PKASEC : PKASEC
bits : 15 - 15 (1 bit)

SDMMC1SEC : SDMMC1SEC
bits : 16 - 16 (1 bit)

FSMC_REGSEC : FSMC_REGSEC
bits : 17 - 17 (1 bit)

OCTOSPI1_REGSEC : OCTOSPI1_REGSEC
bits : 18 - 18 (1 bit)


TZSC_PRIVCFGR1

TZSC privilege configuration register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_PRIVCFGR1 TZSC_PRIVCFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2PRIV TIM3PRIV TIM4PRIV TIM5PRIV TIM6PRIV TIM7PRIV WWDGPRIV IWDGPRIV SPI2PRIV SPI3PRIV USART2PRIV USART3PRIV UART4PRIV UART5PRIV I2C1PRIV I2C2PRIV I2C3PRIV CRSPRIV DACPRIV OPAMPPRIV LPTIM1PRIV LPUART1PRIV I2C4PRIV LPTIM2PRIV LPTIM3PRIV FDCAN1PRIV USBFSPRIV UCPD1PRIV VREFBUFPRIV COMPPRIV TIM1PRIV SPI1PRIV

TIM2PRIV : TIM2PRIV
bits : 0 - 0 (1 bit)

TIM3PRIV : TIM3PRIV
bits : 1 - 1 (1 bit)

TIM4PRIV : TIM4PRIV
bits : 2 - 2 (1 bit)

TIM5PRIV : TIM5PRIV
bits : 3 - 3 (1 bit)

TIM6PRIV : TIM6PRIV
bits : 4 - 4 (1 bit)

TIM7PRIV : TIM7PRIV
bits : 5 - 5 (1 bit)

WWDGPRIV : WWDGPRIV
bits : 6 - 6 (1 bit)

IWDGPRIV : IWDGPRIV
bits : 7 - 7 (1 bit)

SPI2PRIV : SPI2PRIV
bits : 8 - 8 (1 bit)

SPI3PRIV : SPI3PRIV
bits : 9 - 9 (1 bit)

USART2PRIV : USART2PRIV
bits : 10 - 10 (1 bit)

USART3PRIV : USART3PRIV
bits : 11 - 11 (1 bit)

UART4PRIV : UART4PRIV
bits : 12 - 12 (1 bit)

UART5PRIV : UART5PRIV
bits : 13 - 13 (1 bit)

I2C1PRIV : I2C1PRIV
bits : 14 - 14 (1 bit)

I2C2PRIV : I2C2PRIV
bits : 15 - 15 (1 bit)

I2C3PRIV : I2C3PRIV
bits : 16 - 16 (1 bit)

CRSPRIV : CRSPRIV
bits : 17 - 17 (1 bit)

DACPRIV : DACPRIV
bits : 18 - 18 (1 bit)

OPAMPPRIV : OPAMPPRIV
bits : 19 - 19 (1 bit)

LPTIM1PRIV : LPTIM1PRIV
bits : 20 - 20 (1 bit)

LPUART1PRIV : LPUART1PRIV
bits : 21 - 21 (1 bit)

I2C4PRIV : I2C4PRIV
bits : 22 - 22 (1 bit)

LPTIM2PRIV : LPTIM2PRIV
bits : 23 - 23 (1 bit)

LPTIM3PRIV : LPTIM3PRIV
bits : 24 - 24 (1 bit)

FDCAN1PRIV : FDCAN1PRIV
bits : 25 - 25 (1 bit)

USBFSPRIV : USBFSPRIV
bits : 26 - 26 (1 bit)

UCPD1PRIV : UCPD1PRIV
bits : 27 - 27 (1 bit)

VREFBUFPRIV : VREFBUFPRIV
bits : 28 - 28 (1 bit)

COMPPRIV : COMPPRIV
bits : 29 - 29 (1 bit)

TIM1PRIV : TIM1PRIV
bits : 30 - 30 (1 bit)

SPI1PRIV : SPI1PRIV
bits : 31 - 31 (1 bit)


TZSC_PRIVCFGR2

TZSC privilege configuration register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_PRIVCFGR2 TZSC_PRIVCFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM8PRIV USART1PRIV TIM15PRIV TIM16PRIV TIM17PRIV SAI1PRIV SAI2PRIV DFSDM1PRIV CRCPRIV TSCPRIV ICACHEPRIV ADCPRIV AESPRIV HASHPRIV RNGPRIV PKAPRIV SDMMC1PRIV FSMC_REGPRIV OCTOSPI1_REGPRIV

TIM8PRIV : TIM8PRIV
bits : 0 - 0 (1 bit)

USART1PRIV : USART1PRIV
bits : 1 - 1 (1 bit)

TIM15PRIV : TIM15PRIV
bits : 2 - 2 (1 bit)

TIM16PRIV : TIM16PRIV
bits : 3 - 3 (1 bit)

TIM17PRIV : TIM17PRIV
bits : 4 - 4 (1 bit)

SAI1PRIV : SAI1PRIV
bits : 5 - 5 (1 bit)

SAI2PRIV : SAI2PRIV
bits : 6 - 6 (1 bit)

DFSDM1PRIV : DFSDM1PRIV
bits : 7 - 7 (1 bit)

CRCPRIV : CRCPRIV
bits : 8 - 8 (1 bit)

TSCPRIV : TSCPRIV
bits : 9 - 9 (1 bit)

ICACHEPRIV : ICACHEPRIV
bits : 10 - 10 (1 bit)

ADCPRIV : ADCPRIV
bits : 11 - 11 (1 bit)

AESPRIV : AESPRIV
bits : 12 - 12 (1 bit)

HASHPRIV : HASHPRIV
bits : 13 - 13 (1 bit)

RNGPRIV : RNGPRIV
bits : 14 - 14 (1 bit)

PKAPRIV : PKAPRIV
bits : 15 - 15 (1 bit)

SDMMC1PRIV : SDMMC1PRIV
bits : 16 - 16 (1 bit)

FSMC_REGPRIV : FSMC_REGPRIV
bits : 17 - 17 (1 bit)

OCTOSPI1_REGPRIV : OCTOSPI1_REGRIV
bits : 18 - 18 (1 bit)


TZSC_MPCWM1_NSWMR1

TZSC external memory non-secure watermark register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM1_NSWMR1 TZSC_MPCWM1_NSWMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSWM1STRT NSWM1LGTH

NSWM1STRT : NSWM1STRT
bits : 0 - 10 (11 bit)

NSWM1LGTH : NSWM1LGTH
bits : 16 - 27 (12 bit)


TZSC_MPCWM1_NSWMR2

TZSC external memory non-secure watermark register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM1_NSWMR2 TZSC_MPCWM1_NSWMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSWM2STRT NSWM2LGTH

NSWM2STRT : NSWM2STRT
bits : 0 - 10 (11 bit)

NSWM2LGTH : NSWM2LGTH
bits : 16 - 27 (12 bit)


TZSC_MPCWM2_NSWMR1

TZSC external memory non-secure watermark register 1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM2_NSWMR1 TZSC_MPCWM2_NSWMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSWM1STRT NSWM1LGTH

NSWM1STRT : NSWM1STRT
bits : 0 - 10 (11 bit)

NSWM1LGTH : NSWM1LGTH
bits : 16 - 27 (12 bit)


TZSC_MPCWM2_NSWMR2

TZSC external memory non-secure watermark register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM2_NSWMR2 TZSC_MPCWM2_NSWMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSWM2STRT NSWM2LGTH

NSWM2STRT : NSWM2STRT
bits : 0 - 10 (11 bit)

NSWM2LGTH : NSWM2LGTH
bits : 16 - 27 (12 bit)


TZSC_MPCWM3_NSWMR1

TZSC external memory non-secure watermark register 2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM3_NSWMR1 TZSC_MPCWM3_NSWMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSWM2STRT NSWM2LGTH

NSWM2STRT : NSWM2STRT
bits : 0 - 10 (11 bit)

NSWM2LGTH : NSWM2LGTH
bits : 16 - 27 (12 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.