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SYSCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SECCFGR

CSLOCKR

CFGR2

SCSR

SKR

SWPR

SWPR2

RSSCMDR

CFGR1

FPUIMR

CNSLCKR


SECCFGR

SYSCFG secure configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECCFGR SECCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGSEC CLASSBSEC SRAM2SEC FPUSEC

SYSCFGSEC : SYSCFG clock control security
bits : 0 - 0 (1 bit)

CLASSBSEC : ClassB security
bits : 1 - 1 (1 bit)

SRAM2SEC : SRAM2 security
bits : 2 - 2 (1 bit)

FPUSEC : FPUSEC
bits : 3 - 3 (1 bit)


CSLOCKR

SYSCFG CPU secure lock register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSLOCKR CSLOCKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKSVTAIRCR LOCKSMPU LOCKSAU

LOCKSVTAIRCR : LOCKSVTAIRCR
bits : 0 - 0 (1 bit)

LOCKSMPU : LOCKSMPU
bits : 1 - 1 (1 bit)

LOCKSAU : LOCKSAU
bits : 2 - 2 (1 bit)


CFGR2

CFGR2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR2 CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLL SPL PVDL ECCL SPF

CLL : LOCKUP (hardfault) output enable bit
bits : 0 - 0 (1 bit)
access : write-only

SPL : SRAM2 parity lock bit
bits : 1 - 1 (1 bit)
access : write-only

PVDL : PVD lock enable bit
bits : 2 - 2 (1 bit)
access : write-only

ECCL : ECC Lock
bits : 3 - 3 (1 bit)
access : write-only

SPF : SRAM2 parity error flag
bits : 8 - 8 (1 bit)
access : read-write


SCSR

SCSR
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCSR SCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRAM2ER SRAM2BSY

SRAM2ER : SRAM2 Erase
bits : 0 - 0 (1 bit)
access : read-write

SRAM2BSY : SRAM2 busy by erase operation
bits : 1 - 1 (1 bit)
access : read-only


SKR

SKR
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SKR SKR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : SRAM2 write protection key for software erase
bits : 0 - 7 (8 bit)


SWPR

SWPR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWPR SWPR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0WP P1WP P2WP P3WP P4WP P5WP P6WP P7WP P8WP P9WP P10WP P11WP P12WP P13WP P14WP P15WP P16WP P17WP P18WP P19WP P20WP P21WP P22WP P23WP P24WP P25WP P26WP P27WP P28WP P29WP P30WP P31WP

P0WP : P0WP
bits : 0 - 0 (1 bit)

P1WP : P1WP
bits : 1 - 1 (1 bit)

P2WP : P2WP
bits : 2 - 2 (1 bit)

P3WP : P3WP
bits : 3 - 3 (1 bit)

P4WP : P4WP
bits : 4 - 4 (1 bit)

P5WP : P5WP
bits : 5 - 5 (1 bit)

P6WP : P6WP
bits : 6 - 6 (1 bit)

P7WP : P7WP
bits : 7 - 7 (1 bit)

P8WP : P8WP
bits : 8 - 8 (1 bit)

P9WP : P9WP
bits : 9 - 9 (1 bit)

P10WP : P10WP
bits : 10 - 10 (1 bit)

P11WP : P11WP
bits : 11 - 11 (1 bit)

P12WP : P12WP
bits : 12 - 12 (1 bit)

P13WP : P13WP
bits : 13 - 13 (1 bit)

P14WP : P14WP
bits : 14 - 14 (1 bit)

P15WP : P15WP
bits : 15 - 15 (1 bit)

P16WP : P16WP
bits : 16 - 16 (1 bit)

P17WP : P17WP
bits : 17 - 17 (1 bit)

P18WP : P18WP
bits : 18 - 18 (1 bit)

P19WP : P19WP
bits : 19 - 19 (1 bit)

P20WP : P20WP
bits : 20 - 20 (1 bit)

P21WP : P21WP
bits : 21 - 21 (1 bit)

P22WP : P22WP
bits : 22 - 22 (1 bit)

P23WP : P23WP
bits : 23 - 23 (1 bit)

P24WP : P24WP
bits : 24 - 24 (1 bit)

P25WP : P25WP
bits : 25 - 25 (1 bit)

P26WP : P26WP
bits : 26 - 26 (1 bit)

P27WP : P27WP
bits : 27 - 27 (1 bit)

P28WP : P28WP
bits : 28 - 28 (1 bit)

P29WP : P29WP
bits : 29 - 29 (1 bit)

P30WP : P30WP
bits : 30 - 30 (1 bit)

P31WP : SRAM2 page 31 write protection
bits : 31 - 31 (1 bit)


SWPR2

SWPR2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWPR2 SWPR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P32WP P33WP P34WP P35WP P36WP P37WP P38WP P39WP P40WP P41WP P42WP P43WP P44WP P45WP P46WP P47WP P48WP P49WP P50WP P51WP P52WP P53WP P54WP P55WP P56WP P57WP P58WP P59WP P60WP P61WP P62WP P63WP

P32WP : P32WP
bits : 0 - 0 (1 bit)

P33WP : P33WP
bits : 1 - 1 (1 bit)

P34WP : P34WP
bits : 2 - 2 (1 bit)

P35WP : P35WP
bits : 3 - 3 (1 bit)

P36WP : P36WP
bits : 4 - 4 (1 bit)

P37WP : P37WP
bits : 5 - 5 (1 bit)

P38WP : P38WP
bits : 6 - 6 (1 bit)

P39WP : P39WP
bits : 7 - 7 (1 bit)

P40WP : P40WP
bits : 8 - 8 (1 bit)

P41WP : P41WP
bits : 9 - 9 (1 bit)

P42WP : P42WP
bits : 10 - 10 (1 bit)

P43WP : P43WP
bits : 11 - 11 (1 bit)

P44WP : P44WP
bits : 12 - 12 (1 bit)

P45WP : P45WP
bits : 13 - 13 (1 bit)

P46WP : P46WP
bits : 14 - 14 (1 bit)

P47WP : P47WP
bits : 15 - 15 (1 bit)

P48WP : P48WP
bits : 16 - 16 (1 bit)

P49WP : P49WP
bits : 17 - 17 (1 bit)

P50WP : P50WP
bits : 18 - 18 (1 bit)

P51WP : P51WP
bits : 19 - 19 (1 bit)

P52WP : P52WP
bits : 20 - 20 (1 bit)

P53WP : P53WP
bits : 21 - 21 (1 bit)

P54WP : P54WP
bits : 22 - 22 (1 bit)

P55WP : P55WP
bits : 23 - 23 (1 bit)

P56WP : P56WP
bits : 24 - 24 (1 bit)

P57WP : P57WP
bits : 25 - 25 (1 bit)

P58WP : P58WP
bits : 26 - 26 (1 bit)

P59WP : P59WP
bits : 27 - 27 (1 bit)

P60WP : P60WP
bits : 28 - 28 (1 bit)

P61WP : P61WP
bits : 29 - 29 (1 bit)

P62WP : P62WP
bits : 30 - 30 (1 bit)

P63WP : P63WP
bits : 31 - 31 (1 bit)


RSSCMDR

RSSCMDR
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSSCMDR RSSCMDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSSCMD

RSSCMD : RSS commands
bits : 0 - 7 (8 bit)


CFGR1

configuration register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR1 CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOOSTEN ANASWVDD I2C_PB6_FMP I2C_PB7_FMP I2C_PB8_FMP I2C_PB9_FMP I2C1_FMP I2C2_FMP I2C3_FMP I2C4_FMP

BOOSTEN : I/O analog switch voltage booster enable
bits : 8 - 8 (1 bit)

ANASWVDD : GPIO analog switch control voltage selection
bits : 9 - 9 (1 bit)

I2C_PB6_FMP : Fast-mode Plus (Fm+) driving capability activation on PB6
bits : 16 - 16 (1 bit)

I2C_PB7_FMP : Fast-mode Plus (Fm+) driving capability activation on PB7
bits : 17 - 17 (1 bit)

I2C_PB8_FMP : Fast-mode Plus (Fm+) driving capability activation on PB8
bits : 18 - 18 (1 bit)

I2C_PB9_FMP : Fast-mode Plus (Fm+) driving capability activation on PB9
bits : 19 - 19 (1 bit)

I2C1_FMP : I2C1 Fast-mode Plus driving capability activation
bits : 20 - 20 (1 bit)

I2C2_FMP : I2C2 Fast-mode Plus driving capability activation
bits : 21 - 21 (1 bit)

I2C3_FMP : I2C3 Fast-mode Plus driving capability activation
bits : 22 - 22 (1 bit)

I2C4_FMP : I2C4_FMP
bits : 23 - 23 (1 bit)


FPUIMR

FPU interrupt mask register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPUIMR FPUIMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPU_IE

FPU_IE : Floating point unit interrupts enable bits
bits : 0 - 5 (6 bit)


CNSLCKR

SYSCFG CPU non-secure lock register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNSLCKR CNSLCKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKNSVTOR LOCKNSMPU

LOCKNSVTOR : VTOR_NS register lock
bits : 0 - 0 (1 bit)

LOCKNSMPU : Non-secure MPU registers lock
bits : 1 - 1 (1 bit)



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