\n

OctoSPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

DCR3

CCR

TCR

IR

ABR

LPTR

DCR4

WPCCR

WPTCR

WPIR

WPABR

WCCR

WTCR

WIR

WABR

SR

HLCR

FCR

DLR

AR

DR

DCR1

PSMKR

PSMAR

PIR

DCR2


CR

control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN ABORT DMAEN TCEN DQM FSEL FTHRES TEIE TCIE FTIE SMIE TOIE APMS PMM FMODE

EN : Enable
bits : 0 - 0 (1 bit)

ABORT : Abort request
bits : 1 - 1 (1 bit)

DMAEN : DMA enable
bits : 2 - 2 (1 bit)

TCEN : Timeout counter enable
bits : 3 - 3 (1 bit)

DQM : Dual-quad mode
bits : 6 - 6 (1 bit)

FSEL : FLASH memory selection
bits : 7 - 7 (1 bit)

FTHRES : IFO threshold level
bits : 8 - 12 (5 bit)

TEIE : Transfer error interrupt enable
bits : 16 - 16 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 17 - 17 (1 bit)

FTIE : FIFO threshold interrupt enable
bits : 18 - 18 (1 bit)

SMIE : Status match interrupt enable
bits : 19 - 19 (1 bit)

TOIE : TimeOut interrupt enable
bits : 20 - 20 (1 bit)

APMS : Automatic poll mode stop
bits : 22 - 22 (1 bit)

PMM : Polling match mode
bits : 23 - 23 (1 bit)

FMODE : Functional mode
bits : 28 - 29 (2 bit)


DCR3

device configuration register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCR3 DCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSBOUND

CSBOUND : CS boundary
bits : 16 - 20 (5 bit)


CCR

communication configuration register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCYC DHQC SSHIFT

DCYC : Number of dummy cycles
bits : 0 - 4 (5 bit)

DHQC : Delay hold quarter cycle
bits : 28 - 28 (1 bit)

SSHIFT : Sample shift
bits : 30 - 30 (1 bit)


TCR

timing configuration register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTRUCTION

INSTRUCTION : INSTRUCTION
bits : 0 - 31 (32 bit)


IR

instruction register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IR IR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALTERNATE

ALTERNATE : Alternate bytes
bits : 0 - 31 (32 bit)


ABR

alternate bytes register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ABR ABR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEOUT

TIMEOUT : Timeout period
bits : 0 - 15 (16 bit)


LPTR

low-power timeout register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPTR LPTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMODE IDTR ISIZE ADMODE ADDTR ADSIZE ABMODE ABDTR ABSIZE DMODE DDTR DQSE

IMODE : Instruction mode
bits : 0 - 2 (3 bit)

IDTR : Instruction double transfer rate
bits : 3 - 3 (1 bit)

ISIZE : Instruction size
bits : 4 - 5 (2 bit)

ADMODE : Address mode
bits : 8 - 10 (3 bit)

ADDTR : Address double transfer rate
bits : 11 - 11 (1 bit)

ADSIZE : Address size
bits : 12 - 13 (2 bit)

ABMODE : Alternate byte mode
bits : 16 - 18 (3 bit)

ABDTR : Alternate bytes double transfer rate
bits : 19 - 19 (1 bit)

ABSIZE : Alternate bytes size
bits : 20 - 21 (2 bit)

DMODE : Data mode
bits : 24 - 26 (3 bit)

DDTR : alternate bytes double transfer rate
bits : 27 - 27 (1 bit)

DQSE : DQS enable
bits : 29 - 29 (1 bit)


DCR4

DCR4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCR4 DCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEF TCF FTF SMF TOF BUSY FLEVEL

TEF : Transfer error flag
bits : 0 - 0 (1 bit)

TCF : Transfer complete flag
bits : 1 - 1 (1 bit)

FTF : FIFO threshold flag
bits : 2 - 2 (1 bit)

SMF : Status match flag
bits : 3 - 3 (1 bit)

TOF : Timeout flag
bits : 4 - 4 (1 bit)

BUSY : BUSY
bits : 5 - 5 (1 bit)

FLEVEL : FIFO level
bits : 8 - 13 (6 bit)


WPCCR

write communication configuration register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPCCR WPCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCYC DHQC SSHIFT

DCYC : Number of dummy cycles
bits : 0 - 4 (5 bit)

DHQC : Delay hold quarter cycle
bits : 28 - 28 (1 bit)

SSHIFT : Sample shift
bits : 30 - 30 (1 bit)


WPTCR

write timing configuration register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPTCR WPTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTRUCTION

INSTRUCTION : INSTRUCTION
bits : 0 - 31 (32 bit)


WPIR

write instruction register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPIR WPIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALTERNATE

ALTERNATE : Alternate bytes
bits : 0 - 31 (32 bit)


WPABR

write alternate bytes register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPABR WPABR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LM WZL TACC TRWR

LM : Latency mode
bits : 0 - 0 (1 bit)

WZL : Write zero latency
bits : 1 - 1 (1 bit)

TACC : Access time
bits : 8 - 15 (8 bit)

TRWR : Read write recovery time
bits : 16 - 23 (8 bit)


WCCR

WCCR
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WCCR WCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFRESH

REFRESH : REFRESH
bits : 0 - 15 (16 bit)


WTCR

WTCR
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR WTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMODE IDTR ISIZE ADMODE ADDTR ADSIZE ABMODE ABDTR ABSIZE DMODE DDTR DQSE

IMODE : IMODE
bits : 0 - 2 (3 bit)

IDTR : IDTR
bits : 3 - 3 (1 bit)

ISIZE : ISIZE
bits : 4 - 5 (2 bit)

ADMODE : ADMODE
bits : 8 - 10 (3 bit)

ADDTR : ADDTR
bits : 11 - 11 (1 bit)

ADSIZE : ADSIZE
bits : 12 - 13 (2 bit)

ABMODE : ABMODE
bits : 16 - 18 (3 bit)

ABDTR : ABDTR
bits : 19 - 19 (1 bit)

ABSIZE : ABSIZE
bits : 20 - 21 (2 bit)

DMODE : DMODE
bits : 24 - 26 (3 bit)

DDTR : DDTR
bits : 27 - 27 (1 bit)

DQSE : DQSE
bits : 29 - 29 (1 bit)


WIR

WIR
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WIR WIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCYC

DCYC : DCYC
bits : 0 - 4 (5 bit)


WABR

WABR
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WABR WABR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTRUCTION

INSTRUCTION : INSTRUCTION
bits : 0 - 31 (32 bit)


SR

status register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SR SR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTEF CTCF CSMF CTOF

CTEF : Clear transfer error flag
bits : 0 - 0 (1 bit)

CTCF : Clear transfer complete flag
bits : 1 - 1 (1 bit)

CSMF : Clear status match flag
bits : 3 - 3 (1 bit)

CTOF : Clear timeout flag
bits : 4 - 4 (1 bit)


HLCR

HyperBusTM latency configuration register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HLCR HLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALTERNATE

ALTERNATE : Alternate bytes
bits : 0 - 31 (32 bit)


FCR

flag clear register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCR FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DL

DL : Data length
bits : 0 - 31 (32 bit)


DLR

data length register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLR DLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : ADDRESS
bits : 0 - 31 (32 bit)


AR

address register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AR AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 31 (32 bit)


DR

data register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Status mask
bits : 0 - 31 (32 bit)


DCR1

device configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCR1 DCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKMODE FRCK CSHT DEVSIZE MTYP

CKMODE : Mode 0 / mode 3
bits : 0 - 0 (1 bit)

FRCK : Free running clock
bits : 1 - 1 (1 bit)

CSHT : Chip-select high time
bits : 8 - 10 (3 bit)

DEVSIZE : Device size
bits : 16 - 20 (5 bit)

MTYP : Memory type
bits : 24 - 25 (2 bit)


PSMKR

polling status mask register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSMKR PSMKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH

MATCH : Status match
bits : 0 - 31 (32 bit)


PSMAR

polling status match register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSMAR PSMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTERVAL

INTERVAL : Polling interval
bits : 0 - 15 (16 bit)


PIR

polling interval register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIR PIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMODE IDTR ISIZE ADMODE ADDTR ADSIZE ABMODE ABDTR ABSIZE DMODE DDTR DQSE SIOO

IMODE : Instruction mode
bits : 0 - 2 (3 bit)

IDTR : Instruction double transfer rate
bits : 3 - 3 (1 bit)

ISIZE : Instruction size
bits : 4 - 5 (2 bit)

ADMODE : Address mode
bits : 8 - 10 (3 bit)

ADDTR : Address double transfer rate
bits : 11 - 11 (1 bit)

ADSIZE : Address size
bits : 12 - 13 (2 bit)

ABMODE : Alternate byte mode
bits : 16 - 18 (3 bit)

ABDTR : Alternate bytes double transfer rate
bits : 19 - 19 (1 bit)

ABSIZE : Alternate bytes size
bits : 20 - 21 (2 bit)

DMODE : Data mode
bits : 24 - 26 (3 bit)

DDTR : Alternate bytes double transfer rate
bits : 27 - 27 (1 bit)

DQSE : DQS enable
bits : 29 - 29 (1 bit)

SIOO : Send instruction only once mode
bits : 31 - 31 (1 bit)


DCR2

device configuration register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCR2 DCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESCALER WRAPSIZE

PRESCALER : Clock prescaler
bits : 0 - 7 (8 bit)

WRAPSIZE : Wrap size
bits : 16 - 18 (3 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.