\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
EXTI rising trigger selection register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RT0 : Rising trigger event configuration bit of configurable event input x
bits : 0 - 0 (1 bit)
RT1 : Rising trigger event configuration bit of configurable event input x
bits : 1 - 1 (1 bit)
RT2 : Rising trigger event configuration bit of configurable event input x
bits : 2 - 2 (1 bit)
RT3 : Rising trigger event configuration bit of configurable event input x
bits : 3 - 3 (1 bit)
RT4 : Rising trigger event configuration bit of configurable event input x
bits : 4 - 4 (1 bit)
RT5 : Rising trigger event configuration bit of configurable event input x
bits : 5 - 5 (1 bit)
RT6 : Rising trigger event configuration bit of configurable event input x
bits : 6 - 6 (1 bit)
RT7 : Rising trigger event configuration bit of configurable event input x
bits : 7 - 7 (1 bit)
RT8 : Rising trigger event configuration bit of configurable event input x
bits : 8 - 8 (1 bit)
RT9 : Rising trigger event configuration bit of configurable event input x
bits : 9 - 9 (1 bit)
RT10 : Rising trigger event configuration bit of configurable event input x
bits : 10 - 10 (1 bit)
RT11 : Rising trigger event configuration bit of configurable event input x
bits : 11 - 11 (1 bit)
RT12 : Rising trigger event configuration bit of configurable event input x
bits : 12 - 12 (1 bit)
RT13 : Rising trigger event configuration bit of configurable event input x
bits : 13 - 13 (1 bit)
RT14 : Rising trigger event configuration bit of configurable event input x
bits : 14 - 14 (1 bit)
RT15 : Rising trigger event configuration bit of configurable event input x
bits : 15 - 15 (1 bit)
RT16 : Rising trigger event configuration bit of configurable event input x
bits : 16 - 16 (1 bit)
RT21 : Rising trigger event configuration bit of configurable event input x
bits : 21 - 21 (1 bit)
RT22 : Rising trigger event configuration bit of configurable event input x
bits : 22 - 22 (1 bit)
EXTI falling edge pending register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIF0 : configurable event inputs x falling edge pending bit.
bits : 0 - 0 (1 bit)
FPIF1 : configurable event inputs x falling edge pending bit.
bits : 1 - 1 (1 bit)
FPIF2 : configurable event inputs x falling edge pending bit.
bits : 2 - 2 (1 bit)
FPIF3 : configurable event inputs x falling edge pending bit.
bits : 3 - 3 (1 bit)
FPIF4 : configurable event inputs x falling edge pending bit.
bits : 4 - 4 (1 bit)
FPIF5 : configurable event inputs x falling edge pending bit.
bits : 5 - 5 (1 bit)
FPIF6 : configurable event inputs x falling edge pending bit.
bits : 6 - 6 (1 bit)
FPIF7 : configurable event inputs x falling edge pending bit.
bits : 7 - 7 (1 bit)
FPIF8 : configurable event inputs x falling edge pending bit.
bits : 8 - 8 (1 bit)
FPIF9 : configurable event inputs x falling edge pending bit.
bits : 9 - 9 (1 bit)
FPIF10 : configurable event inputs x falling edge pending bit.
bits : 10 - 10 (1 bit)
FPIF11 : configurable event inputs x falling edge pending bit.
bits : 11 - 11 (1 bit)
FPIF12 : configurable event inputs x falling edge pending bit.
bits : 12 - 12 (1 bit)
FPIF13 : configurable event inputs x falling edge pending bit.
bits : 13 - 13 (1 bit)
FPIF14 : configurable event inputs x falling edge pending bit.
bits : 14 - 14 (1 bit)
FPIF15 : configurable event inputs x falling edge pending bit.
bits : 15 - 15 (1 bit)
FPIF16 : configurable event inputs x falling edge pending bit.
bits : 16 - 16 (1 bit)
FPIF21 : configurable event inputs x falling edge pending bit.
bits : 21 - 21 (1 bit)
FPIF22 : configurable event inputs x falling edge pending bit.
bits : 22 - 22 (1 bit)
EXTI security configuration register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC0 : Security enable on event input x
bits : 0 - 0 (1 bit)
SEC1 : Security enable on event input x
bits : 1 - 1 (1 bit)
SEC2 : Security enable on event input x
bits : 2 - 2 (1 bit)
SEC3 : Security enable on event input x
bits : 3 - 3 (1 bit)
SEC4 : Security enable on event input x
bits : 4 - 4 (1 bit)
SEC5 : Security enable on event input x
bits : 5 - 5 (1 bit)
SEC6 : Security enable on event input x
bits : 6 - 6 (1 bit)
SEC7 : Security enable on event input x
bits : 7 - 7 (1 bit)
SEC8 : Security enable on event input x
bits : 8 - 8 (1 bit)
SEC9 : Security enable on event input x
bits : 9 - 9 (1 bit)
SEC10 : Security enable on event input x
bits : 10 - 10 (1 bit)
SEC11 : Security enable on event input x
bits : 11 - 11 (1 bit)
SEC12 : Security enable on event input x
bits : 12 - 12 (1 bit)
SEC13 : Security enable on event input x
bits : 13 - 13 (1 bit)
SEC14 : Security enable on event input x
bits : 14 - 14 (1 bit)
SEC15 : Security enable on event input x
bits : 15 - 15 (1 bit)
SEC16 : Security enable on event input x
bits : 16 - 16 (1 bit)
SEC17 : Security enable on event input x
bits : 17 - 17 (1 bit)
SEC18 : Security enable on event input x
bits : 18 - 18 (1 bit)
SEC19 : Security enable on event input x
bits : 19 - 19 (1 bit)
SEC20 : Security enable on event input x
bits : 20 - 20 (1 bit)
SEC21 : Security enable on event input x
bits : 21 - 21 (1 bit)
SEC22 : Security enable on event input x
bits : 22 - 22 (1 bit)
SEC23 : Security enable on event input x
bits : 23 - 23 (1 bit)
SEC24 : Security enable on event input x
bits : 24 - 24 (1 bit)
SEC25 : Security enable on event input x
bits : 25 - 25 (1 bit)
SEC26 : Security enable on event input x
bits : 26 - 26 (1 bit)
SEC27 : Security enable on event input x
bits : 27 - 27 (1 bit)
SEC28 : Security enable on event input x
bits : 28 - 28 (1 bit)
SEC29 : Security enable on event input x
bits : 29 - 29 (1 bit)
SEC30 : Security enable on event input x
bits : 30 - 30 (1 bit)
SEC31 : Security enable on event input x
bits : 31 - 31 (1 bit)
EXTI privilege configuration register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIV0 : Security enable on event input x
bits : 0 - 0 (1 bit)
PRIV1 : Security enable on event input x
bits : 1 - 1 (1 bit)
PRIV2 : Security enable on event input x
bits : 2 - 2 (1 bit)
PRIV3 : Security enable on event input x
bits : 3 - 3 (1 bit)
PRIV4 : Security enable on event input x
bits : 4 - 4 (1 bit)
PRIV5 : Security enable on event input x
bits : 5 - 5 (1 bit)
PRIV6 : Security enable on event input x
bits : 6 - 6 (1 bit)
PRIV7 : Security enable on event input x
bits : 7 - 7 (1 bit)
PRIV8 : Security enable on event input x
bits : 8 - 8 (1 bit)
PRIV9 : Security enable on event input x
bits : 9 - 9 (1 bit)
PRIV10 : Security enable on event input x
bits : 10 - 10 (1 bit)
PRIV11 : Security enable on event input x
bits : 11 - 11 (1 bit)
PRIV12 : Security enable on event input x
bits : 12 - 12 (1 bit)
PRIV13 : Security enable on event input x
bits : 13 - 13 (1 bit)
PRIV14 : Security enable on event input x
bits : 14 - 14 (1 bit)
PRIV15 : Security enable on event input x
bits : 15 - 15 (1 bit)
PRIV16 : Security enable on event input x
bits : 16 - 16 (1 bit)
PRIV17 : Security enable on event input x
bits : 17 - 17 (1 bit)
PRIV18 : Security enable on event input x
bits : 18 - 18 (1 bit)
PRIV19 : Security enable on event input x
bits : 19 - 19 (1 bit)
PRIV20 : Security enable on event input x
bits : 20 - 20 (1 bit)
PRIV21 : Security enable on event input x
bits : 21 - 21 (1 bit)
PRIV22 : Security enable on event input x
bits : 22 - 22 (1 bit)
PRIV23 : Security enable on event input x
bits : 23 - 23 (1 bit)
PRIV24 : Security enable on event input x
bits : 24 - 24 (1 bit)
PRIV25 : Security enable on event input x
bits : 25 - 25 (1 bit)
PRIV26 : Security enable on event input x
bits : 26 - 26 (1 bit)
PRIV27 : Security enable on event input x
bits : 27 - 27 (1 bit)
PRIV28 : Security enable on event input x
bits : 28 - 28 (1 bit)
PRIV29 : Security enable on event input x
bits : 29 - 29 (1 bit)
PRIV30 : Security enable on event input x
bits : 30 - 30 (1 bit)
PRIV31 : Security enable on event input x
bits : 31 - 31 (1 bit)
EXTI rising trigger selection register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RT35 : Rising trigger event configuration bit of configurable event input x
bits : 3 - 3 (1 bit)
RT36 : Rising trigger event configuration bit of configurable event input x
bits : 4 - 4 (1 bit)
RT37 : Rising trigger event configuration bit of configurable event input x
bits : 5 - 5 (1 bit)
RT38 : Rising trigger event configuration bit of configurable event input x
bits : 6 - 6 (1 bit)
EXTI falling trigger selection register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FT35 : FT35
bits : 3 - 3 (1 bit)
FT36 : FT36
bits : 4 - 4 (1 bit)
FT37 : FT37
bits : 5 - 5 (1 bit)
FT38 : FT38
bits : 6 - 6 (1 bit)
EXTI software interrupt event register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWI35 : SWI35
bits : 3 - 3 (1 bit)
SWI36 : SWI36
bits : 4 - 4 (1 bit)
SWI37 : SWI37
bits : 5 - 5 (1 bit)
SWI38 : SWI38
bits : 6 - 6 (1 bit)
EXTI rising edge pending register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RPIF35 : RPIF35
bits : 3 - 3 (1 bit)
RPIF36 : RPIF36
bits : 4 - 4 (1 bit)
RPIF37 : RPIF37
bits : 5 - 5 (1 bit)
RPIF38 : RPIF38
bits : 6 - 6 (1 bit)
EXTI falling edge pending register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIF35 : FPIF35
bits : 3 - 3 (1 bit)
FPIF36 : FPIF36
bits : 4 - 4 (1 bit)
FPIF37 : FPIF37
bits : 5 - 5 (1 bit)
FPIF38 : FPIF38
bits : 6 - 6 (1 bit)
EXTI security enable register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIV32 : PRIV32
bits : 0 - 0 (1 bit)
PRIV33 : PRIV33
bits : 1 - 1 (1 bit)
PRIV34 : PRIV34
bits : 2 - 2 (1 bit)
PRIV35 : PRIV35
bits : 3 - 3 (1 bit)
PRIV36 : PRIV36
bits : 4 - 4 (1 bit)
PRIV37 : PRIV37
bits : 5 - 5 (1 bit)
PRIV38 : PRIV38
bits : 6 - 6 (1 bit)
PRIV39 : PRIV39
bits : 7 - 7 (1 bit)
PRIV40 : PRIV40
bits : 8 - 8 (1 bit)
PRIV41 : PRIV41
bits : 9 - 9 (1 bit)
PRIV42 : PRIV42
bits : 10 - 10 (1 bit)
EXTI security enable register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC32 : SEC32
bits : 0 - 0 (1 bit)
SEC33 : SEC33
bits : 1 - 1 (1 bit)
SEC34 : SEC34
bits : 2 - 2 (1 bit)
SEC35 : SEC35
bits : 3 - 3 (1 bit)
SEC36 : SEC36
bits : 4 - 4 (1 bit)
SEC37 : SEC37
bits : 5 - 5 (1 bit)
SEC38 : SEC38
bits : 6 - 6 (1 bit)
SEC39 : SEC39
bits : 7 - 7 (1 bit)
SEC40 : SEC40
bits : 8 - 8 (1 bit)
SEC41 : SEC41
bits : 9 - 9 (1 bit)
SEC42 : SEC42
bits : 10 - 10 (1 bit)
EXTI falling trigger selection register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FT0 : Falling trigger event configuration bit of configurable event input x
bits : 0 - 0 (1 bit)
FT1 : Falling trigger event configuration bit of configurable event input x
bits : 1 - 1 (1 bit)
FT2 : Falling trigger event configuration bit of configurable event input x
bits : 2 - 2 (1 bit)
FT3 : Falling trigger event configuration bit of configurable event input x
bits : 3 - 3 (1 bit)
FT4 : Falling trigger event configuration bit of configurable event input x
bits : 4 - 4 (1 bit)
FT5 : Falling trigger event configuration bit of configurable event input x
bits : 5 - 5 (1 bit)
FT6 : Falling trigger event configuration bit of configurable event input x
bits : 6 - 6 (1 bit)
FT7 : Falling trigger event configuration bit of configurable event input x
bits : 7 - 7 (1 bit)
FT8 : Falling trigger event configuration bit of configurable event input x
bits : 8 - 8 (1 bit)
FT9 : Falling trigger event configuration bit of configurable event input x
bits : 9 - 9 (1 bit)
FT10 : Falling trigger event configuration bit of configurable event input x
bits : 10 - 10 (1 bit)
FT11 : Falling trigger event configuration bit of configurable event input x
bits : 11 - 11 (1 bit)
FT12 : Falling trigger event configuration bit of configurable event input x
bits : 12 - 12 (1 bit)
FT13 : Falling trigger event configuration bit of configurable event input x
bits : 13 - 13 (1 bit)
FT14 : Falling trigger event configuration bit of configurable event input x
bits : 14 - 14 (1 bit)
FT15 : Falling trigger event configuration bit of configurable event input x
bits : 15 - 15 (1 bit)
FT16 : Falling trigger event configuration bit of configurable event input x
bits : 16 - 16 (1 bit)
FT21 : Falling trigger event configuration bit of configurable event input x
bits : 21 - 21 (1 bit)
FT22 : Falling trigger event configuration bit of configurable event input x
bits : 22 - 22 (1 bit)
EXTI external interrupt selection register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI0_7 : EXTIm GPIO port selection
bits : 0 - 7 (8 bit)
EXTI8_15 : EXTIm+1 GPIO port selection
bits : 8 - 15 (8 bit)
EXTI16_23 : EXTIm+2 GPIO port selection
bits : 16 - 23 (8 bit)
EXTI24_31 : EXTIm+3 GPIO port selection
bits : 24 - 31 (8 bit)
EXTI external interrupt selection register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI0_7 : EXTIm GPIO port selection
bits : 0 - 7 (8 bit)
EXTI8_15 : EXTIm+1 GPIO port selection
bits : 8 - 15 (8 bit)
EXTI16_23 : EXTIm+2 GPIO port selection
bits : 16 - 23 (8 bit)
EXTI24_31 : EXTIm+3 GPIO port selection
bits : 24 - 31 (8 bit)
EXTI external interrupt selection register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI0_7 : EXTIm GPIO port selection
bits : 0 - 7 (8 bit)
EXTI8_15 : EXTIm+1 GPIO port selection
bits : 8 - 15 (8 bit)
EXTI16_23 : EXTIm+2 GPIO port selection
bits : 16 - 23 (8 bit)
EXTI24_31 : EXTIm+3 GPIO port selection
bits : 24 - 31 (8 bit)
EXTI external interrupt selection register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI0_7 : EXTIm GPIO port selection
bits : 0 - 7 (8 bit)
EXTI8_15 : EXTIm+1 GPIO port selection
bits : 8 - 15 (8 bit)
EXTI16_23 : EXTIm+2 GPIO port selection
bits : 16 - 23 (8 bit)
EXTI24_31 : EXTIm+3 GPIO port selection
bits : 24 - 31 (8 bit)
EXTI lock register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : LOCK
bits : 0 - 0 (1 bit)
EXTI software interrupt event register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWI0 : Software interrupt on event x
bits : 0 - 0 (1 bit)
SWI1 : Software interrupt on event x
bits : 1 - 1 (1 bit)
SWI2 : Software interrupt on event x
bits : 2 - 2 (1 bit)
SWI3 : Software interrupt on event x
bits : 3 - 3 (1 bit)
SWI4 : Software interrupt on event x
bits : 4 - 4 (1 bit)
SWI5 : Software interrupt on event x
bits : 5 - 5 (1 bit)
SWI6 : Software interrupt on event x
bits : 6 - 6 (1 bit)
SWI7 : Software interrupt on event x
bits : 7 - 7 (1 bit)
SWI8 : Software interrupt on event x
bits : 8 - 8 (1 bit)
SWI9 : Software interrupt on event x
bits : 9 - 9 (1 bit)
SWI10 : Software interrupt on event x
bits : 10 - 10 (1 bit)
SWI11 : Software interrupt on event x
bits : 11 - 11 (1 bit)
SWI12 : Software interrupt on event x
bits : 12 - 12 (1 bit)
SWI13 : Software interrupt on event x
bits : 13 - 13 (1 bit)
SWI14 : Software interrupt on event x
bits : 14 - 14 (1 bit)
SWI15 : Software interrupt on event x
bits : 15 - 15 (1 bit)
SWI16 : Software interrupt on event x
bits : 16 - 16 (1 bit)
SWI21 : Software interrupt on event x
bits : 21 - 21 (1 bit)
SWI22 : Software interrupt on event x
bits : 22 - 22 (1 bit)
EXTI CPU wakeup with interrupt mask register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM0 : CPU wakeup with interrupt mask on event input
bits : 0 - 0 (1 bit)
IM1 : CPU wakeup with interrupt mask on event input
bits : 1 - 1 (1 bit)
IM2 : CPU wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)
IM3 : CPU wakeup with interrupt mask on event input
bits : 3 - 3 (1 bit)
IM4 : CPU wakeup with interrupt mask on event input
bits : 4 - 4 (1 bit)
IM5 : CPU wakeup with interrupt mask on event input
bits : 5 - 5 (1 bit)
IM6 : CPU wakeup with interrupt mask on event input
bits : 6 - 6 (1 bit)
IM7 : CPU wakeup with interrupt mask on event input
bits : 7 - 7 (1 bit)
IM8 : CPU wakeup with interrupt mask on event input
bits : 8 - 8 (1 bit)
IM9 : CPU wakeup with interrupt mask on event input
bits : 9 - 9 (1 bit)
IM10 : CPU wakeup with interrupt mask on event input
bits : 10 - 10 (1 bit)
IM11 : CPU wakeup with interrupt mask on event input
bits : 11 - 11 (1 bit)
IM12 : CPU wakeup with interrupt mask on event input
bits : 12 - 12 (1 bit)
IM13 : CPU wakeup with interrupt mask on event input
bits : 13 - 13 (1 bit)
IM14 : CPU wakeup with interrupt mask on event input
bits : 14 - 14 (1 bit)
IM15 : CPU wakeup with interrupt mask on event input
bits : 15 - 15 (1 bit)
IM16 : CPU wakeup with interrupt mask on event input
bits : 16 - 16 (1 bit)
IM17 : CPU wakeup with interrupt mask on event input
bits : 17 - 17 (1 bit)
IM18 : CPU wakeup with interrupt mask on event input
bits : 18 - 18 (1 bit)
IM19 : CPU wakeup with interrupt mask on event input
bits : 19 - 19 (1 bit)
IM20 : CPU wakeup with interrupt mask on event input
bits : 20 - 20 (1 bit)
IM21 : CPU wakeup with interrupt mask on event input
bits : 21 - 21 (1 bit)
IM22 : CPU wakeup with interrupt mask on event input
bits : 22 - 22 (1 bit)
IM23 : CPU wakeup with interrupt mask on event input
bits : 23 - 23 (1 bit)
IM24 : CPU wakeup with interrupt mask on event input
bits : 24 - 24 (1 bit)
IM25 : CPU wakeup with interrupt mask on event input
bits : 25 - 25 (1 bit)
IM26 : CPU wakeup with interrupt mask on event input
bits : 26 - 26 (1 bit)
IM27 : CPU wakeup with interrupt mask on event input
bits : 27 - 27 (1 bit)
IM28 : CPU wakeup with interrupt mask on event input
bits : 28 - 28 (1 bit)
IM29 : CPU wakeup with interrupt mask on event input
bits : 29 - 29 (1 bit)
IM30 : CPU wakeup with interrupt mask on event input
bits : 30 - 30 (1 bit)
IM31 : CPU wakeup with interrupt mask on event input
bits : 31 - 31 (1 bit)
EXTI CPU wakeup with event mask register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM0 : CPU wakeup with interrupt mask on event input
bits : 0 - 0 (1 bit)
EM1 : CPU wakeup with interrupt mask on event input
bits : 1 - 1 (1 bit)
EM2 : CPU wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)
EM3 : CPU wakeup with interrupt mask on event input
bits : 3 - 3 (1 bit)
EM4 : CPU wakeup with interrupt mask on event input
bits : 4 - 4 (1 bit)
EM5 : CPU wakeup with interrupt mask on event input
bits : 5 - 5 (1 bit)
EM6 : CPU wakeup with interrupt mask on event input
bits : 6 - 6 (1 bit)
EM7 : CPU wakeup with interrupt mask on event input
bits : 7 - 7 (1 bit)
EM8 : CPU wakeup with interrupt mask on event input
bits : 8 - 8 (1 bit)
EM9 : CPU wakeup with interrupt mask on event input
bits : 9 - 9 (1 bit)
EM10 : CPU wakeup with interrupt mask on event input
bits : 10 - 10 (1 bit)
EM11 : CPU wakeup with interrupt mask on event input
bits : 11 - 11 (1 bit)
EM12 : CPU wakeup with interrupt mask on event input
bits : 12 - 12 (1 bit)
EM13 : CPU wakeup with interrupt mask on event input
bits : 13 - 13 (1 bit)
EM14 : CPU wakeup with interrupt mask on event input
bits : 14 - 14 (1 bit)
EM15 : CPU wakeup with interrupt mask on event input
bits : 15 - 15 (1 bit)
EM16 : CPU wakeup with interrupt mask on event input
bits : 16 - 16 (1 bit)
EM17 : CPU wakeup with interrupt mask on event input
bits : 17 - 17 (1 bit)
EM18 : CPU wakeup with interrupt mask on event input
bits : 18 - 18 (1 bit)
EM19 : CPU wakeup with interrupt mask on event input
bits : 19 - 19 (1 bit)
EM20 : CPU wakeup with interrupt mask on event input
bits : 20 - 20 (1 bit)
EM21 : CPU wakeup with interrupt mask on event input
bits : 21 - 21 (1 bit)
EM22 : CPU wakeup with interrupt mask on event input
bits : 22 - 22 (1 bit)
EM23 : CPU wakeup with interrupt mask on event input
bits : 23 - 23 (1 bit)
EM24 : CPU wakeup with interrupt mask on event input
bits : 24 - 24 (1 bit)
EM25 : CPU wakeup with interrupt mask on event input
bits : 25 - 25 (1 bit)
EM26 : CPU wakeup with interrupt mask on event input
bits : 26 - 26 (1 bit)
EM27 : CPU wakeup with interrupt mask on event input
bits : 27 - 27 (1 bit)
EM28 : CPU wakeup with interrupt mask on event input
bits : 28 - 28 (1 bit)
EM29 : CPU wakeup with interrupt mask on event input
bits : 29 - 29 (1 bit)
EM30 : CPU wakeup with interrupt mask on event input
bits : 30 - 30 (1 bit)
EM31 : CPU wakeup with interrupt mask on event input
bits : 31 - 31 (1 bit)
EXTI CPUm wakeup with interrupt mask register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM32 : CPU wakeup with interrupt mask on event input
bits : 0 - 0 (1 bit)
IM33 : CPU wakeup with interrupt mask on event input
bits : 1 - 1 (1 bit)
IM34 : CPU wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)
IM35 : CPU wakeup with interrupt mask on event input
bits : 3 - 3 (1 bit)
IM36 : CPU wakeup with interrupt mask on event input
bits : 4 - 4 (1 bit)
IM37 : CPU wakeup with interrupt mask on event input
bits : 5 - 5 (1 bit)
IM38 : CPU wakeup with interrupt mask on event input
bits : 6 - 6 (1 bit)
IM40 : CPU wakeup with interrupt mask on event input
bits : 8 - 8 (1 bit)
IM41 : CPU wakeup with interrupt mask on event input
bits : 9 - 9 (1 bit)
IM42 : CPU wakeup with interrupt mask on event input
bits : 10 - 10 (1 bit)
EXTI CPU wakeup with event mask register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM32 : CPU wakeup with interrupt mask on event input
bits : 0 - 0 (1 bit)
EM33 : CPU wakeup with interrupt mask on event input
bits : 1 - 1 (1 bit)
EM34 : CPU wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)
EM35 : CPU wakeup with interrupt mask on event input
bits : 3 - 3 (1 bit)
EM36 : CPU wakeup with interrupt mask on event input
bits : 4 - 4 (1 bit)
EM37 : CPU wakeup with interrupt mask on event input
bits : 5 - 5 (1 bit)
EM38 : CPU wakeup with interrupt mask on event input
bits : 6 - 6 (1 bit)
EM40 : CPU wakeup with interrupt mask on event input
bits : 8 - 8 (1 bit)
EM41 : CPU wakeup with interrupt mask on event input
bits : 9 - 9 (1 bit)
EM42 : CPU wakeup with interrupt mask on event input
bits : 10 - 10 (1 bit)
EXTI rising edge pending register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RPIF0 : configurable event inputs x rising edge pending bit
bits : 0 - 0 (1 bit)
RPIF1 : configurable event inputs x rising edge pending bit
bits : 1 - 1 (1 bit)
RPIF2 : configurable event inputs x rising edge pending bit
bits : 2 - 2 (1 bit)
RPIF3 : configurable event inputs x rising edge pending bit
bits : 3 - 3 (1 bit)
RPIF4 : configurable event inputs x rising edge pending bit
bits : 4 - 4 (1 bit)
RPIF5 : configurable event inputs x rising edge pending bit
bits : 5 - 5 (1 bit)
RPIF6 : configurable event inputs x rising edge pending bit
bits : 6 - 6 (1 bit)
RPIF7 : configurable event inputs x rising edge pending bit
bits : 7 - 7 (1 bit)
RPIF8 : configurable event inputs x rising edge pending bit
bits : 8 - 8 (1 bit)
RPIF9 : configurable event inputs x rising edge pending bit
bits : 9 - 9 (1 bit)
RPIF10 : configurable event inputs x rising edge pending bit
bits : 10 - 10 (1 bit)
RPIF11 : configurable event inputs x rising edge pending bit
bits : 11 - 11 (1 bit)
RPIF12 : configurable event inputs x rising edge pending bit
bits : 12 - 12 (1 bit)
RPIF13 : configurable event inputs x rising edge pending bit
bits : 13 - 13 (1 bit)
RPIF14 : configurable event inputs x rising edge pending bit
bits : 14 - 14 (1 bit)
RPIF15 : configurable event inputs x rising edge pending bit
bits : 15 - 15 (1 bit)
RPIF16 : configurable event inputs x rising edge pending bit
bits : 16 - 16 (1 bit)
RPIF21 : configurable event inputs x rising edge pending bit
bits : 21 - 21 (1 bit)
RPIF22 : configurable event inputs x rising edge pending bit
bits : 22 - 22 (1 bit)
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