\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
SDMA System Address Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDMASYSADDRARG : Physical SYS Memory ADDR Used for DMA Transfers or the Second Argument for the Auto CMD23
bits : 0 - 31 (32 bit)
access : read-write
Response0 and Response1 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDRESP0 : Command Response 0
bits : 0 - 31 (32 bit)
access : read-only
Response2 and Response3 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDRESP1 : Command Response 1
bits : 0 - 31 (32 bit)
access : read-only
Response4 and Response5 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDRESP2 : Command Response 2
bits : 0 - 31 (32 bit)
access : read-only
Response6 and Response7 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDRESP3 : Command Response 3
bits : 0 - 31 (32 bit)
access : read-only
Buffer Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFDAT : Buffer Data
bits : 0 - 31 (32 bit)
access : read-write
Present State Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDINHIBITCMD : Command Inhibit (CMD)
bits : 0 - 0 (1 bit)
access : read-only
CMDINHIBITDAT : Command Inhibit (DAT)
bits : 1 - 1 (1 bit)
access : read-only
DATLINEACTIVE : DAT Line Active
bits : 2 - 2 (1 bit)
access : read-only
RETUNINGREQ : Re-Tuning Request
bits : 3 - 3 (1 bit)
access : read-only
WRTRANACT : Write Transfer Active
bits : 8 - 8 (1 bit)
access : read-only
RDTRANACT : Read Transfer Active
bits : 9 - 9 (1 bit)
access : read-only
BUFFERWRITEENABLE : Buffer Write Enable
bits : 10 - 10 (1 bit)
access : read-only
BUFRDEN : Buffer Read Enable
bits : 11 - 11 (1 bit)
access : read-only
CARDINS : Card Inserted Status
bits : 16 - 16 (1 bit)
access : read-only
CARDSTATESTABLE : Card State Stable Status
bits : 17 - 17 (1 bit)
access : read-only
CARDDETPINLVL : Card Detect Pin Level
bits : 18 - 18 (1 bit)
access : read-only
WRPROTSWPINLVL : Write Protect Switch Pin Level
bits : 19 - 19 (1 bit)
access : read-only
DAT3TO0SIGLVL : DAT[3:0] Line Signal Level
bits : 20 - 23 (4 bit)
access : read-only
CMDSIGLVL : Command Line Signal Level
bits : 24 - 24 (1 bit)
access : read-only
DAT7TO4SIGLVL : DAT[7:4] Line Signal Level
bits : 25 - 28 (4 bit)
access : read-only
Host Control1, Power, Block Gap and Wakeup-up Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEDCTRL : LED Control
bits : 0 - 0 (1 bit)
access : read-write
DATTRANWD : Data Transfer Width 1-bit or 4-bit Mode
bits : 1 - 1 (1 bit)
access : read-write
HSEN : High Speed Enable
bits : 2 - 2 (1 bit)
access : read-write
DMASEL : DMA Select
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x00000000 : SDMA
SDMA selected
0x00000001 : ADMA1
32-bit ADMA1 selected
0x00000002 : ADMA2
32-bit ADMA2 selected
0x00000003 : 64BITADMA2
64-bit ADMA2 selected
End of enumeration elements list.
EXTDATTRANWD : Extended Data Transfer Width
bits : 5 - 5 (1 bit)
access : read-write
CDTSTLVL : Card Detect Test Level
bits : 6 - 6 (1 bit)
access : read-write
CDSIGDET : Card Detetct Signal Detection
bits : 7 - 7 (1 bit)
access : read-write
SDBUSPOWER : SD Bus Power
bits : 8 - 8 (1 bit)
access : read-write
SDBUSVOLTSEL : SD Bus Voltage Select
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0x00000005 : 1P8V
Select 1.8V
0x00000006 : 3P0V
Select 3.0V
0x00000007 : 3P3V
Select 3.3V
End of enumeration elements list.
HRDRST : Hardware Reset Signal
bits : 12 - 12 (1 bit)
access : read-write
STOPATBLKGAPREQ : Stop at Block Gap Request
bits : 16 - 16 (1 bit)
access : read-write
CONTINUEREQ : Continue Request
bits : 17 - 17 (1 bit)
access : read-write
RDWAITCTRL : Read Wait Control
bits : 18 - 18 (1 bit)
access : read-write
INTATBLKGAP : Interrupt at Block Gap
bits : 19 - 19 (1 bit)
access : read-write
SPIMODE : SPI Mode Enable
bits : 20 - 20 (1 bit)
access : read-write
BOOTEN : Boot Enable
bits : 21 - 21 (1 bit)
access : read-write
ALTBOOTEN : Alternate Boot Enable
bits : 22 - 22 (1 bit)
access : read-write
BOOTACKCHK : Boot Ack Check
bits : 23 - 23 (1 bit)
access : read-write
WKUPEVNTENONCARDINT : Wakeup Event Enable on Card Interrupt
bits : 24 - 24 (1 bit)
access : read-write
WKUPEVNTENONCINS : Wakeup Event Enable on SD Card Insertion
bits : 25 - 25 (1 bit)
access : read-write
WKUPEVNTENONCRM : Wakeup Event Enable on SD Card Removal
bits : 26 - 26 (1 bit)
access : read-write
Clock Control, Timeout Control and Software Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTCLKEN : Internal Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
INTCLKSTABLE : Internal Clock Stable
bits : 1 - 1 (1 bit)
access : read-only
SDCLKEN : SDIO_CLK Pin Clock Enable
bits : 2 - 2 (1 bit)
access : read-write
CLKGENSEL : Clock Generator Select
bits : 5 - 5 (1 bit)
access : read-write
UPPSDCLKFRE : Upper Bits of SD_CLK Frequency Select
bits : 6 - 7 (2 bit)
access : read-write
SDCLKFREQSEL : SD_CLK Frequency Select
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
0x00000000 : NODIVISION
None
End of enumeration elements list.
DATTOUTCNTVAL : Data Timeout Counter Value
bits : 16 - 19 (4 bit)
access : read-write
SFTRSTA : Software Reset for All
bits : 24 - 24 (1 bit)
access : read-write
SFTRSTCMD : Software Reset for CMD Line
bits : 25 - 25 (1 bit)
access : read-write
SFTRSTDAT : Software Reset for DAT Line
bits : 26 - 26 (1 bit)
access : read-write
Normal and Error Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCOM : Command Complete
bits : 0 - 0 (1 bit)
access : read-write
TRANCOM : Transfer Complete
bits : 1 - 1 (1 bit)
access : read-write
BLKGAPEVT : Block Gap Event
bits : 2 - 2 (1 bit)
access : read-write
DMAINT : DMA Interrupt
bits : 3 - 3 (1 bit)
access : read-write
BFRWRRDY : Buffer Write Ready
bits : 4 - 4 (1 bit)
access : read-write
BFRRDRDY : Buffer Read Ready
bits : 5 - 5 (1 bit)
access : read-write
CARDINS : Card Insertion
bits : 6 - 6 (1 bit)
access : read-write
CARDRM : Card Removal
bits : 7 - 7 (1 bit)
access : read-write
CARDINT : Card Interrupt
bits : 8 - 8 (1 bit)
access : read-only
RETUNINGEVT : Re-Tunning Event
bits : 12 - 12 (1 bit)
access : read-only
BOOTACKRCV : Boot Ack Received
bits : 13 - 13 (1 bit)
access : read-write
BOOTTERMINATE : Boot Terminate Interrupt
bits : 14 - 14 (1 bit)
access : read-write
ERRINT : Error Interrupt
bits : 15 - 15 (1 bit)
access : read-only
CMDTOUTERR : Command Timeout Error
bits : 16 - 16 (1 bit)
access : read-write
CMDCRCERR : CMD CRC Error
bits : 17 - 17 (1 bit)
access : read-write
CMDENDBITERR : Command End Bit Error
bits : 18 - 18 (1 bit)
access : read-write
CMDINDEXERR : Command Index Error
bits : 19 - 19 (1 bit)
access : read-write
DATTOUTERR : Data Time-out Error
bits : 20 - 20 (1 bit)
access : read-write
DATCRCERR : Data CRC Error
bits : 21 - 21 (1 bit)
access : read-write
DATENDBITERR : Data End Bit Error
bits : 22 - 22 (1 bit)
access : read-write
CURRENTLIMITERR : Current Limit Error
bits : 23 - 23 (1 bit)
access : read-write
AUTOCMDERR : Auto CMD Error
bits : 24 - 24 (1 bit)
access : read-write
ADMAERR : ADMA Error
bits : 25 - 25 (1 bit)
access : read-write
TARGETRESP : Specific Error STAT
bits : 28 - 28 (1 bit)
access : read-write
Normal and Error Interrupt Status Enable Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCOMEN : Command Complete Signal Enable
bits : 0 - 0 (1 bit)
access : read-write
TRANCOMEN : Transfer Complete Signal Enable
bits : 1 - 1 (1 bit)
access : read-write
BLKGAPEVTEN : Block Gap Event Signal Enable
bits : 2 - 2 (1 bit)
access : read-write
DMAINTEN : DMA Interrupt Signal Enable
bits : 3 - 3 (1 bit)
access : read-write
BUFWRRDYEN : Buffer Write Ready Signal Enable
bits : 4 - 4 (1 bit)
access : read-write
BUFRDRDYEN : Buffer Read Ready Signal Enable
bits : 5 - 5 (1 bit)
access : read-write
CARDINSEN : Card Insertion Signal Enable
bits : 6 - 6 (1 bit)
access : read-write
CARDRMEN : Card Removal Signal Enable
bits : 7 - 7 (1 bit)
access : read-write
CARDINTEN : Card Interrupt Signal Enable
bits : 8 - 8 (1 bit)
access : read-write
RETUNINGEVTEN : Re-Tunning Event Signal Enable
bits : 12 - 12 (1 bit)
access : read-write
BOOTACKRCVEN : Boot Ack Received Signal Enable
bits : 13 - 13 (1 bit)
access : read-write
BOOTTERMINATEEN : Boot Terminate Interrupt Signal Enable
bits : 14 - 14 (1 bit)
access : read-write
CMDTOUTERREN : Command Time-out Error Status Enable
bits : 16 - 16 (1 bit)
access : read-write
CMDCRCERREN : Command CRC Error Status Enable
bits : 17 - 17 (1 bit)
access : read-write
CMDENDBITERREN : Command End Bit Error Status Enable
bits : 18 - 18 (1 bit)
access : read-write
CMDINDEXERREN : Command Index Error Status Enable
bits : 19 - 19 (1 bit)
access : read-write
DATTOUTERREN : Data Timeout Error Status Enable
bits : 20 - 20 (1 bit)
access : read-write
DATCRCERREN : Data CRC Error Status Enable
bits : 21 - 21 (1 bit)
access : read-write
DATENDBITERREN : Data End Bit Error Status Enable
bits : 22 - 22 (1 bit)
access : read-write
CURRENTLIMITERREN : Current Limit Error Status Enable
bits : 23 - 23 (1 bit)
access : read-write
AUTOCMDERREN : Auto CMD12 Error Status Enable
bits : 24 - 24 (1 bit)
access : read-write
ADMAERREN : ADMA Error Status Enable
bits : 25 - 25 (1 bit)
access : read-write
TUNINGERREN : Tuning Error Status Enable
bits : 26 - 26 (1 bit)
access : read-write
TARGETRESPEN : Target Response/Host Error Status Enable
bits : 28 - 28 (1 bit)
access : read-write
Normal and Error Interrupt Signal Enable Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCOMSEN : Command Complete Signal Enable
bits : 0 - 0 (1 bit)
access : read-write
TRANCOMSEN : Transfer Complete Signal Enable
bits : 1 - 1 (1 bit)
access : read-write
BLKGAPEVTSEN : Block Gap Event Signal Enable
bits : 2 - 2 (1 bit)
access : read-write
DMAINTSEN : DMA Interrupt Signal Enable
bits : 3 - 3 (1 bit)
access : read-write
BUFWRRDYSEN : Buffer Write Ready Signal Enable
bits : 4 - 4 (1 bit)
access : read-write
BUFRDRDYSEN : Buffer Read Ready Signal Enable
bits : 5 - 5 (1 bit)
access : read-write
CARDINSSEN : Card Insertion Signal Enable
bits : 6 - 6 (1 bit)
access : read-write
CARDREMSEN : Card Removal Signal Enable
bits : 7 - 7 (1 bit)
access : read-write
CARDINTSEN : Card Interrupt Signal Enable
bits : 8 - 8 (1 bit)
access : read-write
RETUNINGEVTSEN : Re-Tuning Event Signal Enable
bits : 12 - 12 (1 bit)
access : read-write
BOOTACKRCVSEN : Boot Ack Received Signal Enable
bits : 13 - 13 (1 bit)
access : read-write
BOOTTERMINATESEN : Boot Terminate Interrupt Signal Enable
bits : 14 - 14 (1 bit)
access : read-write
CMDTOUTERRSEN : Command Timeout Error Signal Enable
bits : 16 - 16 (1 bit)
access : read-write
CMDCRCERRSEN : Command CRC Error Signal Enable
bits : 17 - 17 (1 bit)
access : read-write
CMDENDBITERRSEN : Command End Bit Error Signal Enable
bits : 18 - 18 (1 bit)
access : read-write
CMDINDEXERRSEN : Command Index Error Signal Enable
bits : 19 - 19 (1 bit)
access : read-write
DATTOUTERRSEN : Data Timeout Error Signal Enable
bits : 20 - 20 (1 bit)
access : read-write
DATCRCERRSEN : Data CRC Error Signal Enable
bits : 21 - 21 (1 bit)
access : read-write
DATENDBITERRSEN : Data End Bit Error Signal Enable
bits : 22 - 22 (1 bit)
access : read-write
CURRENTLIMITERRSEN : Current Limit Error Signal Enable
bits : 23 - 23 (1 bit)
access : read-write
AUTOCMDERRSEN : Auto CMD12 Error Signal Enable
bits : 24 - 24 (1 bit)
access : read-write
ADMAERRSEN : ADMA Error Signal Enable
bits : 25 - 25 (1 bit)
access : read-write
TUNINGERRSIGNALENABLE : Tuning Error Signal Enable
bits : 26 - 26 (1 bit)
access : read-write
TARGETRESPERRSEN : Target Response Error Signal Enable
bits : 28 - 28 (1 bit)
access : read-write
AUTO CMD12 Error Status and Host Control2 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AC12NOTEXE : Auto CMD12 Not Executed
bits : 0 - 0 (1 bit)
access : read-only
AC12TOE : Auto CMD12 Timeout Error
bits : 1 - 1 (1 bit)
access : read-only
AC12CRCERR : Auto CMD CRC Error
bits : 2 - 2 (1 bit)
access : read-only
AC12ENDBITERR : Auto CMD End Bit Error
bits : 3 - 3 (1 bit)
access : read-only
AC12INDEXERR : Auto CMD Index Error
bits : 4 - 4 (1 bit)
access : read-only
CNIBAC12ERR : Command Not Issued By Auto CMD12 Error
bits : 7 - 7 (1 bit)
access : read-only
UHSMODESEL : UHS Mode Select
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x00000000 : SDR12
SDR12
0x00000001 : SDR25
SDR25
0x00000002 : SDR50
SDR50
0x00000003 : SDR104
SDR104
0x00000004 : DDR50
DDR50
End of enumeration elements list.
SIGEN1P8V : Voltage 1.8V Signal Enable
bits : 19 - 19 (1 bit)
access : read-write
DRVSTNSEL : Driver Strength Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x00000000 : TYPEB
Driver Type B is selected (Default)
0x00000001 : TYPEA
Driver Type A is selected
0x00000002 : TYPEC
Driver Type C is selected
0x00000003 : TYPED
Driver Type D is selected
End of enumeration elements list.
EXETUNING : Execute Tuning
bits : 22 - 22 (1 bit)
access : read-write
SAMPCLKSEL : Sampling Clock Select
bits : 23 - 23 (1 bit)
access : read-write
ASYNCINTEN : Asynchronous Interrupt Enable
bits : 30 - 30 (1 bit)
access : read-write
PRSTVALEN : Preset Value Enable
bits : 31 - 31 (1 bit)
access : read-write
Block Size and Block Count Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFRBLKSIZE : Transfer Block Size, Specifies the Block Size for Block Data Transfers for CMD17, CMD18, CMD24, CMD25, and CMD53
bits : 0 - 11 (12 bit)
access : read-write
Enumeration:
0x00000000 : NOXFER
None
End of enumeration elements list.
HSTSDMABUFSIZE : Host SDMA Buffer Size
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x00000000 : SIZE4
4KB(Detects A11 Carry out)
0x00000001 : SIZE8
8KB(Detects A12 Carry out)
0x00000002 : SIZE16
16KB(Detects A13 Carry out)
0x00000003 : SIZE32
32KB(Detects A14 Carry out)
0x00000004 : SIZE64
64KB(Detects A15 Carry out)
0x00000005 : SIZE128
128KB(Detects A16 Carry out)
0x00000006 : SIZE256
256KB(Detects A17 Carry out)
0x00000007 : SIZE512
512KB(Detects A18 Carry out)
End of enumeration elements list.
BLKSCNTFORCURRTFR : Blocks Count for Current Transfer
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0x00000000 : STOPCNT
None
End of enumeration elements list.
Capabilities Register to Hold Bits 31~0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMOUTCLKFREQ : Timeout Clock Frequency
bits : 0 - 5 (6 bit)
access : read-only
TMOUTCLKUNIT : Timeout Clock Unit
bits : 7 - 7 (1 bit)
access : read-only
BASECLKFREQSD : Base Clock Frequency for SD_CLK
bits : 8 - 15 (8 bit)
access : read-only
MAXBLOCKLEN : Maximum Block Length
bits : 16 - 17 (2 bit)
access : read-only
EXTMEDIABUSSUP : Extended Media Bus Support
bits : 18 - 18 (1 bit)
access : read-only
ADMA2SUP : ADMA2 Support
bits : 19 - 19 (1 bit)
access : read-only
HSSUP : High Speed Support
bits : 21 - 21 (1 bit)
access : read-only
SDMASUP : SDMA Support
bits : 22 - 22 (1 bit)
access : read-only
SUSRESSUP : Suspend / Resume Support
bits : 23 - 23 (1 bit)
access : read-only
VOLTSUP3P3V : Voltage Support 3.3V
bits : 24 - 24 (1 bit)
access : read-only
VOLTSUP3P0V : Voltage Support 3.0V
bits : 25 - 25 (1 bit)
access : read-only
VOLTSUP1P8V : Voltage Support 1.8V
bits : 26 - 26 (1 bit)
access : read-only
SYSBUS64BSUP : System Bus 64-bit Support
bits : 28 - 28 (1 bit)
access : read-only
ASYNCINTSUP : Asynchronous Interrupt Support
bits : 29 - 29 (1 bit)
access : read-only
IFSLOTTYPE : Interface Card Slot Type
bits : 30 - 31 (2 bit)
access : read-only
Enumeration:
0x00000000 : REMOVABLE
Removable Card Slot
0x00000001 : EMBEDDED
Only one non-removable device is conected to a SD bus slot
0x00000002 : SHARED
Can be set if Host controller supports Shared Bus CTRL register
End of enumeration elements list.
Capabilities Register to Hold Bits 63~32
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SDR50SUP : SDR50 Support
bits : 0 - 0 (1 bit)
access : read-only
SDR104SUP : SDR104 Support
bits : 1 - 1 (1 bit)
access : read-only
DDR50SUP : DDR50 Support
bits : 2 - 2 (1 bit)
access : read-only
DRVTYPASUP : Driver Type a Support
bits : 4 - 4 (1 bit)
access : read-only
DRVTYPCSUP : Driver Type C Support
bits : 5 - 5 (1 bit)
access : read-only
DRVTYPDSUP : Driver Type D Support
bits : 6 - 6 (1 bit)
access : read-only
TIMCNTRETUN : Timer Count for Re-Tuning
bits : 8 - 11 (4 bit)
access : read-only
USETUNSDR50 : Use Tuning for SDR50
bits : 13 - 13 (1 bit)
access : read-only
RETUNEMODES : Re-tuning Modes
bits : 14 - 15 (2 bit)
access : read-only
CLOCKKMUL : Clock Multiplier
bits : 16 - 23 (8 bit)
access : read-only
SPIMODE : SPI Mode Support
bits : 24 - 24 (1 bit)
access : read-only
SPIBLOCKMODE : SPI Block Mode Support
bits : 25 - 25 (1 bit)
access : read-only
Maximum Current Capabilities Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MAXCUR3P3VAL : Maximum Current for 3.3V
bits : 0 - 7 (8 bit)
access : read-only
MAXCUR3P0VAL : Maximum Current for 3.0V
bits : 8 - 15 (8 bit)
access : read-only
MAXCUR1P8VAL : Maximum Current for 1.8V
bits : 16 - 23 (8 bit)
access : read-only
Force Event Register for Auto CMD Error Status
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AC12NEX : Force Event for Command Not Issued By Auto CM12 Not Executed
bits : 0 - 0 (1 bit)
access : read-write
AC12TOE : Force Event for Auto CMD Timeout Error
bits : 1 - 1 (1 bit)
access : read-write
AC12CRCE : Force Event for Auto CMD CRC Error
bits : 2 - 2 (1 bit)
access : read-write
AC12EBE : Force Event for Auto CMD End Bit Error
bits : 3 - 3 (1 bit)
access : read-write
AC12INDXE : Force Event for Auto CMD Index Error
bits : 4 - 4 (1 bit)
access : read-write
CNIBAC12E : Force Event for Command Not Issued By Auto CMD12 Error
bits : 7 - 7 (1 bit)
access : read-write
CMDTOE : Force Event for Command Timeout Error
bits : 16 - 16 (1 bit)
access : read-write
CMDCRCE : Force Event for Command CRC Error
bits : 17 - 17 (1 bit)
access : read-write
CMDEBE : Force Event for Command End Bit Error
bits : 18 - 18 (1 bit)
access : read-write
CMDINDXE : Force Event for Command Index Error
bits : 19 - 19 (1 bit)
access : read-write
DATTOE : Force Event for Data Timeout Error
bits : 20 - 20 (1 bit)
access : read-write
DATCRCE : Force Event for Data CRC Error
bits : 21 - 21 (1 bit)
access : read-write
DATEBE : Force Event for Data End Bit Error
bits : 22 - 22 (1 bit)
access : read-write
CURLIMITE : Force Event for Current Limit Error
bits : 23 - 23 (1 bit)
access : read-write
AC12E : Force Event for Auto CMD Error
bits : 24 - 24 (1 bit)
access : read-write
ADMAE : Force Event for ADMA Error
bits : 25 - 25 (1 bit)
access : read-write
TUNINGE : Force Event for Tuning Errro
bits : 26 - 26 (1 bit)
access : read-only
VENSPECE : Force Event for Vendox Specific Error Status
bits : 28 - 31 (4 bit)
access : read-only
ADMA Error Status Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADMAES : ADMA Error State
bits : 0 - 1 (2 bit)
access : read-only
ADMALME : ADMA Length Mismatch Error
bits : 2 - 2 (1 bit)
access : read-only
ADMA System Address Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADSADDR : ADMA System Address
bits : 0 - 31 (32 bit)
access : read-write
Preset Value for Initialization and Default Speed Mode
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INITSDCLKFREQVAL : SD_CLK Frequency Select Value for Initialization
bits : 0 - 9 (10 bit)
access : read-only
INITCLCKGENVAL : Clock Generator Select Value for Initialization
bits : 10 - 10 (1 bit)
access : read-only
INITDRVSTVAL : Driver Strength Select Value for Initialization
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x00000000 : TYPEB
Driver Type B is selected (Default)
0x00000001 : TYPEA
Driver Type A is selected
0x00000002 : TYPEC
Driver Type C is selected
0x00000003 : TYPED
Driver Type D is selected
End of enumeration elements list.
DSPSDCLKFREQVAL : SD_CLK Frequency Select Value for Default Speed
bits : 16 - 25 (10 bit)
access : read-only
DSPCLKGENVAL : Clock Generator Select Value for Default Speed
bits : 26 - 26 (1 bit)
access : read-only
DSPDRVSTVAL : Driver Strength Select Value for Default Speed
bits : 30 - 31 (2 bit)
access : read-only
Enumeration:
0x00000000 : TYPEB
Driver Type B is selected (Default)
0x00000001 : TYPEA
Driver Type A is selected
0x00000002 : TYPEC
Driver Type C is selected
0x00000003 : TYPED
Driver Type D is selected
End of enumeration elements list.
Preset Value for High Speed and SDR12 Modes
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HSPSDCLKFREQVAL : SD_CLK Frequency Select Value for High Speed
bits : 0 - 9 (10 bit)
access : read-only
HSPCLKGENVAL : Clock Generator Select Value for High Speed
bits : 10 - 10 (1 bit)
access : read-only
HSPDRVSTVAL : Driver Strength Select Value for High Speed
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x00000000 : TYPEB
Driver Type B is selected (Default)
0x00000001 : TYPEA
Driver Type A is selected
0x00000002 : TYPEC
Driver Type C is selected
0x00000003 : TYPED
Driver Type D is selected
End of enumeration elements list.
SDR12SDCLKFREQVAL : SD_CLK Frequency Select Value for SDR12
bits : 16 - 25 (10 bit)
access : read-only
SDR12CLKGENVAL : Clock Generator Select Value for SDR12
bits : 26 - 26 (1 bit)
access : read-only
SDR12DRVSTVAL : Driver Strength Select Value for SDR12
bits : 30 - 31 (2 bit)
access : read-only
Enumeration:
0x00000000 : TYPEB
Driver Type B is selected (Default)
0x00000001 : TYPEA
Driver Type A is selected
0x00000002 : TYPEC
Driver Type C is selected
0x00000003 : TYPED
Driver Type D is selected
End of enumeration elements list.
Preset Value for SDR25 and SDR50 Modes
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SDR25SDCLKFREQVAL : SD_CLK Frequency Select Value for SDR25
bits : 0 - 9 (10 bit)
access : read-only
SDR25CLKGENVAL : Clock Generator Select Value for SDR25
bits : 10 - 10 (1 bit)
access : read-only
SDR25DRVSTVAL : Driver Strength Select Value for SDR25
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x00000000 : TYPEB
Driver Type B is selected (Default)
0x00000001 : TYPEA
Driver Type A is selected
0x00000002 : TYPEC
Driver Type C is selected
0x00000003 : TYPED
Driver Type D is selected
End of enumeration elements list.
SDR50SDCLKFREQVAL : SD_CLK Frequency Select Value for SDR50
bits : 16 - 25 (10 bit)
access : read-only
SDR50CLCKGENVAL : Clock Generator Select Value for SDR50
bits : 26 - 26 (1 bit)
access : read-only
SDR50DRVSTVAL : Driver Strength Select Value for SDR50
bits : 30 - 31 (2 bit)
access : read-only
Enumeration:
0x00000000 : TYPEB
Driver Type B is selected (Default)
0x00000001 : TYPEA
Driver Type A is selected
0x00000002 : TYPEC
Driver Type C is selected
0x00000003 : TYPED
Driver Type D is selected
End of enumeration elements list.
Preset Value for SDR104 and DDR50 Modes
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SDR104SDCLKFREQVAL : SD_CLK Frequency Select Value for SDR104
bits : 0 - 9 (10 bit)
access : read-only
SDR104CLKGENVAL : Clock Generator Select Value for SDR104
bits : 10 - 10 (1 bit)
access : read-only
SDR104DRVSTVAL : Driver Strength Select Value for SDR104
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x00000000 : TYPEB
Driver Type B is selected (Default)
0x00000001 : TYPEA
Driver Type A is selected
0x00000002 : TYPEC
Driver Type C is selected
0x00000003 : TYPED
Driver Type D is selected
End of enumeration elements list.
DDR50SDCLKFREQVAL : SD_CLK Frequency Select Value for DDR50
bits : 16 - 25 (10 bit)
access : read-only
DDR50CLKGENVAL : Clock Generator Select Value for DDR50
bits : 26 - 26 (1 bit)
access : read-only
DDR50DRVSTVAL : Driver Strength Select Value for DDR50
bits : 30 - 31 (2 bit)
access : read-only
Enumeration:
0x00000000 : TYPEB
Driver Type B is selected (Default)
0x00000001 : TYPEA
Driver Type A is selected
0x00000002 : TYPEC
Driver Type C is selected
0x00000003 : TYPED
Driver Type D is selected
End of enumeration elements list.
Boot Timeout Control Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTDATTOCNT : Boot Data Timeout Counter Value
bits : 0 - 31 (32 bit)
access : read-write
SD Command Argument Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDARG1 : Command Argument 1
bits : 0 - 31 (32 bit)
access : read-write
Core Control Signals
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITAPDLYEN : Selective Tap Delay Line Enable on Rxclk_in
bits : 0 - 0 (1 bit)
access : read-write
ITAPDLYSEL : Selects One of 32 Taps on the Rxclk_in Line
bits : 1 - 5 (5 bit)
access : read-write
ITAPCHGWIN : Gating Signal for Tap Delay Change
bits : 6 - 6 (1 bit)
access : read-write
OTAPDLYEN : Selective Tap Delay Line Enable on SDIO_CLK Pin
bits : 7 - 7 (1 bit)
access : read-write
OTAPDLYSEL : Selects One of 32 Taps on the SDIO_CLK Pin
bits : 8 - 11 (4 bit)
access : read-write
TXDLYMUXSEL : TX Delay Mux Selection
bits : 16 - 17 (2 bit)
access : read-write
Core Configuration 0
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNINGCNT : Tuning Counter Value
bits : 0 - 5 (6 bit)
access : read-write
TOUTCLKFREQ : Timeout Clock Frequency
bits : 6 - 11 (6 bit)
access : read-write
TOUTCLKUNIT : Timeout Clock Unit in kHz or MHz
bits : 12 - 12 (1 bit)
access : read-write
BASECLKFREQ : Base Clock Frequency for SD_CLK
bits : 13 - 20 (8 bit)
access : read-write
MAXBLKLEN : MAX Block Length of Transfer
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0x00000000 : 512B
512 Bytes are Selected
0x00000001 : 1024B
1024 Bytes are Selected
0x00000002 : 2048B
2048 Bytes are Selected
End of enumeration elements list.
C8BITSUP : 8-bit Interface Support
bits : 23 - 23 (1 bit)
access : read-write
CADMA2SUP : ADMA2 Mode Support
bits : 24 - 24 (1 bit)
access : read-write
CHSSUP : High Speed Mode Support
bits : 25 - 25 (1 bit)
access : read-write
CSDMASUP : SDMA Mode Support
bits : 26 - 26 (1 bit)
access : read-write
CSUSPRESSUP : Suspend/Resume Support
bits : 27 - 27 (1 bit)
access : read-write
C3P3VSUP : Core 3P3V Support
bits : 28 - 28 (1 bit)
access : read-write
C3P0VSUP : 3P0V Support
bits : 29 - 29 (1 bit)
access : read-write
C1P8VSUP : 1P8V Support
bits : 30 - 30 (1 bit)
access : read-write
Core Configuration 1
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ASYNCINTRSUP : Asynchronous Interrupt Support
bits : 0 - 0 (1 bit)
access : read-write
SLOTTYPE : Slot Type
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x00000000 : RMSDSLOT
Removable SD Card Slot
0x00000001 : EMSDSLOT
Embedded SD Card Slot
0x00000002 : SHBUSSLOT
Shared SD Card Slot
End of enumeration elements list.
CSDR50SUP : Core Support SDR50
bits : 3 - 3 (1 bit)
access : read-write
CSDR104SUP : Support SDR104
bits : 4 - 4 (1 bit)
access : read-write
CDDR50SUP : Support DDR50
bits : 5 - 5 (1 bit)
access : read-write
CDRVASUP : Support Type a Driver
bits : 6 - 6 (1 bit)
access : read-write
CDRVCSUP : Support Type C Driver
bits : 7 - 7 (1 bit)
access : read-write
CDRVDSUP : Support Type D Driver
bits : 8 - 8 (1 bit)
access : read-write
RETUNTMRCTL : Retuning Timer Control
bits : 9 - 12 (4 bit)
access : read-write
TUNSDR50 : Tuning for SDR50
bits : 13 - 13 (1 bit)
access : read-write
RETUNMODES : Retuning Modes
bits : 14 - 15 (2 bit)
access : read-write
SPISUP : SPI Support
bits : 16 - 16 (1 bit)
access : read-write
ASYNCWKUPEN : Asynchronous Wakeup Enable
bits : 18 - 18 (1 bit)
access : read-write
Core Configuration Preset Value 0
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INITSDCLKFREQ : Initial SD_CLK Frequency
bits : 0 - 9 (10 bit)
access : read-write
INITCLKGENEN : Initial Clock Gen Enable
bits : 10 - 10 (1 bit)
access : read-write
INITDRVST : Initial Drive Strength
bits : 11 - 12 (2 bit)
access : read-write
DSPSDCLKFREQ : Preset Value for Default Speed of SD_CLK
bits : 16 - 25 (10 bit)
access : read-write
DSPCLKGENEN : Default Speed Clock Gen Enable
bits : 26 - 26 (1 bit)
access : read-write
DSPDRVST : Default Speed Drive Strength
bits : 27 - 28 (2 bit)
access : read-write
Core Configuration Preset Value 1
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSPSDCLKFREQ : High Speed SD_CLK Frequency
bits : 0 - 9 (10 bit)
access : read-write
HSPCLKGENEN : High Speed SD_CLK Gen Enable
bits : 10 - 10 (1 bit)
access : read-write
HSPDRVST : High Speed SD Drive Strength
bits : 11 - 12 (2 bit)
access : read-write
SDR12SDCLKFREQ : Preset Value for SDR12 Speed of SD_CLK
bits : 16 - 25 (10 bit)
access : read-write
SDR12CLKGENEN : SDR12 Speed Clock Gen Enable
bits : 26 - 26 (1 bit)
access : read-write
SDR12DRVST : SDR12 Speed Drive Strength
bits : 27 - 28 (2 bit)
access : read-write
Core Configuration Preset Value 2
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDR25SDCLKFREQ : SDR25 SD_CLK Frequency
bits : 0 - 9 (10 bit)
access : read-write
SDR25CLKGENEN : SDR25 SD_CLK Gen Enable
bits : 10 - 10 (1 bit)
access : read-write
SDR25DRVST : SDR25 SD Drive Strength
bits : 11 - 12 (2 bit)
access : read-write
SDR50SDCLKFREQ : Preset Value for SDR50 Speed of SD_CLK
bits : 16 - 25 (10 bit)
access : read-write
SDR50CLKGENEN : SDR50 Speed Clock Gen Enable
bits : 26 - 26 (1 bit)
access : read-write
SDR50DRVST : SDR50 Speed Drive Strength
bits : 27 - 28 (2 bit)
access : read-write
Core Configuration Preset Value 3
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDR104SDCLKFREQ : SDR104 SD_CLK Frequency
bits : 0 - 9 (10 bit)
access : read-write
SDR104CLKGENEN : SDR104 SD_CLK Gen Enable
bits : 10 - 10 (1 bit)
access : read-write
SDR104DRVST : SDR104 SD Drive Strength
bits : 11 - 12 (2 bit)
access : read-write
DDR50SDCLKFREQ : Preset Value for DDR50 Speed of SD_CLK
bits : 16 - 25 (10 bit)
access : read-write
DDR50CLKGENEN : DDR50 Speed Clock Gen Enable
bits : 26 - 26 (1 bit)
access : read-write
DDR50DRVST : DDR50 Speed Drive Strength
bits : 27 - 28 (2 bit)
access : read-write
I/O LOCATION Register
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATLOC : I/O Location for D0-7 Pins
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
End of enumeration elements list.
CDLOC : I/O Location for CD
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
End of enumeration elements list.
WPLOC : I/O Location for WP
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
End of enumeration elements list.
CLKLOC : I/O Location for CLK
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
End of enumeration elements list.
I/O LOCATION Register
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDLOC : I/O Location for CMD Pin
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
End of enumeration elements list.
I/O LOCATION Enable Register
address_offset : 0x824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKPEN : CLK I/O Enable
bits : 0 - 0 (1 bit)
access : read-write
CMDPEN : CMD I/O Enable
bits : 1 - 1 (1 bit)
access : read-write
D0PEN : Dat0 I/O Enable
bits : 2 - 2 (1 bit)
access : read-write
D1PEN : Dat1 I/O Enable
bits : 3 - 3 (1 bit)
access : read-write
D2PEN : Dat2 I/O Enable
bits : 4 - 4 (1 bit)
access : read-write
D3PEN : Dat3 I/O Enable
bits : 5 - 5 (1 bit)
access : read-write
D4PEN : Dat4 I/O Enable
bits : 6 - 6 (1 bit)
access : read-write
D5PEN : Dat5 Enable
bits : 7 - 7 (1 bit)
access : read-write
D6PEN : Dat6 Enable
bits : 8 - 8 (1 bit)
access : read-write
D7PEN : Data7 I/O Enable
bits : 9 - 9 (1 bit)
access : read-write
Transfer Mode and Command Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
BLKCNTEN : Block Count Enable
bits : 1 - 1 (1 bit)
access : read-write
AUTOCMDEN : Auto Command Enable
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x00000000 : ACMDDISABLED
Auto CMD Disabled
0x00000001 : ACMD12EN
Auto CMD12 Enable
0x00000002 : ACMD23EN
Auto CMD23 Enable
End of enumeration elements list.
DATDIRSEL : Data Transfer Direction Select
bits : 4 - 4 (1 bit)
access : read-write
MULTSINGBLKSEL : Multiple or Single Block Data Transfer Selection
bits : 5 - 5 (1 bit)
access : read-write
RESPTYPESEL : Response Type Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x00000000 : NORESP
No RESP
0x00000001 : RESP136
RESP Length 136
0x00000002 : RESP48
RESP Length 48
0x00000003 : BUSYAFTRESP
RESP Length 48 check busy after RESP
End of enumeration elements list.
CMDCRCCHKEN : Command CRC Check Enable
bits : 19 - 19 (1 bit)
access : read-write
CMDINDXCHKEN : Command Index Check Enable
bits : 20 - 20 (1 bit)
access : read-write
DATPRESSEL : Data Present Select
bits : 21 - 21 (1 bit)
access : read-write
CMDTYPE : Command Type
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0x00000000 : NORMAL
Normal Command
0x00000001 : SUSPEND
Suspend command
0x00000002 : RESUME
Resume command
0x00000003 : ABORT
Abort command
End of enumeration elements list.
CMDINDEX : Command Index
bits : 24 - 29 (6 bit)
access : read-write
Slot Interrupt Status Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTSLOT0 : Interrupt Signal for Slot#0
bits : 0 - 0 (1 bit)
access : read-only
SPECVERNUM : Host Controller Compliant Spec Version Number
bits : 16 - 23 (8 bit)
access : read-only
VENDVERNUM : Vendor Version Number
bits : 24 - 31 (8 bit)
access : read-only
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