\n
address_offset : 0x0 Bytes (0x0)
size : 0x800 byte (0x0)
mem_usage : registers
protection : not protected
endpoint 0 register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Endpoint address
bits : 0 - 3 (4 bit)
STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)
EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)
endpoint 4 register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Endpoint address
bits : 0 - 3 (4 bit)
STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)
EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)
endpoint 5 register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Endpoint address
bits : 0 - 3 (4 bit)
STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)
EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)
endpoint 6 register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Endpoint address
bits : 0 - 3 (4 bit)
STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)
EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)
endpoint 7 register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Endpoint address
bits : 0 - 3 (4 bit)
STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)
EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)
endpoint 1 register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Endpoint address
bits : 0 - 3 (4 bit)
STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)
EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)
control register
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRES : Force USB Reset
bits : 0 - 0 (1 bit)
PDWN : Power down
bits : 1 - 1 (1 bit)
LPMODE : Low-power mode
bits : 2 - 2 (1 bit)
FSUSP : Force suspend
bits : 3 - 3 (1 bit)
RESUME : Resume request
bits : 4 - 4 (1 bit)
L1RESUME : LPM L1 Resume request
bits : 5 - 5 (1 bit)
L1REQM : LPM L1 state request interrupt mask
bits : 7 - 7 (1 bit)
ESOFM : Expected start of frame interrupt mask
bits : 8 - 8 (1 bit)
SOFM : Start of frame interrupt mask
bits : 9 - 9 (1 bit)
RESETM : USB reset interrupt mask
bits : 10 - 10 (1 bit)
SUSPM : Suspend mode interrupt mask
bits : 11 - 11 (1 bit)
WKUPM : Wakeup interrupt mask
bits : 12 - 12 (1 bit)
ERRM : Error interrupt mask
bits : 13 - 13 (1 bit)
PMAOVRM : Packet memory area over / underrun interrupt mask
bits : 14 - 14 (1 bit)
CTRM : Correct transfer interrupt mask
bits : 15 - 15 (1 bit)
interrupt status register
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP_ID : Endpoint Identifier
bits : 0 - 3 (4 bit)
access : read-only
DIR : Direction of transaction
bits : 4 - 4 (1 bit)
access : read-only
L1REQ : LPM L1 state request
bits : 7 - 7 (1 bit)
access : read-write
ESOF : Expected start frame
bits : 8 - 8 (1 bit)
access : read-write
SOF : start of frame
bits : 9 - 9 (1 bit)
access : read-write
RESET : reset request
bits : 10 - 10 (1 bit)
access : read-write
SUSP : Suspend mode request
bits : 11 - 11 (1 bit)
access : read-write
WKUP : Wakeup
bits : 12 - 12 (1 bit)
access : read-write
ERR : Error
bits : 13 - 13 (1 bit)
access : read-write
PMAOVR : Packet memory area over / underrun
bits : 14 - 14 (1 bit)
access : read-write
CTR : Correct transfer
bits : 15 - 15 (1 bit)
access : read-only
frame number register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FN : Frame number
bits : 0 - 10 (11 bit)
LSOF : Lost SOF
bits : 11 - 12 (2 bit)
LCK : Locked
bits : 13 - 13 (1 bit)
RXDM : Receive data - line status
bits : 14 - 14 (1 bit)
RXDP : Receive data + line status
bits : 15 - 15 (1 bit)
device address
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADD : Device address
bits : 0 - 6 (7 bit)
EF : Enable function
bits : 7 - 7 (1 bit)
Buffer table address
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTABLE : Buffer table
bits : 3 - 15 (13 bit)
Transmission byte count 0
address_offset : 0x52 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT0_TX : Transmission byte count
bits : 0 - 9 (10 bit)
LPM control and status register
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPMEN : LPM support enable
bits : 0 - 0 (1 bit)
LPMACK : LPM Token acknowledge enable
bits : 1 - 1 (1 bit)
REMWAKE : RemoteWake value
bits : 3 - 3 (1 bit)
BESL : BESL value
bits : 4 - 7 (4 bit)
Reception byte count 0
address_offset : 0x56 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT0_RX : Reception byte count
bits : 0 - 9 (10 bit)
access : read-only
NUM_BLOCK : Number of blocks
bits : 10 - 14 (5 bit)
access : read-write
BL_SIZE : Block size
bits : 15 - 15 (1 bit)
access : read-write
Battery charging detector
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCDEN : Battery charging detector (BCD) enable
bits : 0 - 0 (1 bit)
DCDEN : Data contact detection (DCD) mode enable
bits : 1 - 1 (1 bit)
PDEN : Primary detection (PD) mode enable
bits : 2 - 2 (1 bit)
SDEN : Secondary detection (SD) mode enable
bits : 3 - 3 (1 bit)
DCDET : Data contact detection (DCD) status
bits : 4 - 4 (1 bit)
PDET : Primary detection (PD) status
bits : 5 - 5 (1 bit)
SDET : Secondary detection (SD) status
bits : 6 - 6 (1 bit)
PS2DET : DM pull-up detection status
bits : 7 - 7 (1 bit)
DPPU : DP pull-up control
bits : 15 - 15 (1 bit)
Transmission byte count 0
address_offset : 0x5A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT1_TX : Transmission byte count
bits : 0 - 9 (10 bit)
Reception buffer address 0
address_offset : 0x5C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR0_RX : Reception buffer address
bits : 1 - 15 (15 bit)
Reception byte count 0
address_offset : 0x5E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT1_RX : Reception byte count
bits : 0 - 9 (10 bit)
access : read-only
NUM_BLOCK : Number of blocks
bits : 10 - 14 (5 bit)
access : read-write
BL_SIZE : Block size
bits : 15 - 15 (1 bit)
access : read-write
Transmission byte count 0
address_offset : 0x62 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT2_TX : Transmission byte count
bits : 0 - 9 (10 bit)
Reception buffer address 0
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR1_RX : Reception buffer address
bits : 1 - 15 (15 bit)
Reception byte count 0
address_offset : 0x66 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT2_RX : Reception byte count
bits : 0 - 9 (10 bit)
access : read-only
NUM_BLOCK : Number of blocks
bits : 10 - 14 (5 bit)
access : read-write
BL_SIZE : Block size
bits : 15 - 15 (1 bit)
access : read-write
Transmission byte count 0
address_offset : 0x6A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT3_TX : Transmission byte count
bits : 0 - 9 (10 bit)
Reception buffer address 0
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR2_RX : Reception buffer address
bits : 1 - 15 (15 bit)
Reception byte count 0
address_offset : 0x6E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT3_RX : Reception byte count
bits : 0 - 9 (10 bit)
access : read-only
NUM_BLOCK : Number of blocks
bits : 10 - 14 (5 bit)
access : read-write
BL_SIZE : Block size
bits : 15 - 15 (1 bit)
access : read-write
Transmission byte count 0
address_offset : 0x72 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT4_TX : Transmission byte count
bits : 0 - 9 (10 bit)
Reception buffer address 0
address_offset : 0x74 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR3_RX : Reception buffer address
bits : 1 - 15 (15 bit)
Reception byte count 0
address_offset : 0x76 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT4_RX : Reception byte count
bits : 0 - 9 (10 bit)
access : read-only
NUM_BLOCK : Number of blocks
bits : 10 - 14 (5 bit)
access : read-write
BL_SIZE : Block size
bits : 15 - 15 (1 bit)
access : read-write
Transmission byte count 0
address_offset : 0x7A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT5_TX : Transmission byte count
bits : 0 - 9 (10 bit)
Reception buffer address 0
address_offset : 0x7C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR4_RX : Reception buffer address
bits : 1 - 15 (15 bit)
Reception byte count 0
address_offset : 0x7E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT5_RX : Reception byte count
bits : 0 - 9 (10 bit)
access : read-only
NUM_BLOCK : Number of blocks
bits : 10 - 14 (5 bit)
access : read-write
BL_SIZE : Block size
bits : 15 - 15 (1 bit)
access : read-write
endpoint 2 register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Endpoint address
bits : 0 - 3 (4 bit)
STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)
EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)
Transmission byte count 0
address_offset : 0x82 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT6_TX : Transmission byte count
bits : 0 - 9 (10 bit)
Reception buffer address 0
address_offset : 0x84 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR5_RX : Reception buffer address
bits : 1 - 15 (15 bit)
Reception byte count 0
address_offset : 0x86 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT6_RX : Reception byte count
bits : 0 - 9 (10 bit)
access : read-only
NUM_BLOCK : Number of blocks
bits : 10 - 14 (5 bit)
access : read-write
BL_SIZE : Block size
bits : 15 - 15 (1 bit)
access : read-write
Transmission byte count 0
address_offset : 0x8A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT7_TX : Transmission byte count
bits : 0 - 9 (10 bit)
Reception buffer address 0
address_offset : 0x8C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR6_RX : Reception buffer address
bits : 1 - 15 (15 bit)
Reception byte count 0
address_offset : 0x8E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT7_RX : Reception byte count
bits : 0 - 9 (10 bit)
access : read-only
NUM_BLOCK : Number of blocks
bits : 10 - 14 (5 bit)
access : read-write
BL_SIZE : Block size
bits : 15 - 15 (1 bit)
access : read-write
Reception buffer address 0
address_offset : 0x94 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR7_RX : Reception buffer address
bits : 1 - 15 (15 bit)
endpoint 3 register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Endpoint address
bits : 0 - 3 (4 bit)
STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)
EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)
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