\n
address_offset : 0x0 Bytes (0x0)
size : 0xC00 byte (0x0)
mem_usage : registers
protection : not protected
FDCAN Core Release Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DAY : Timestamp Day
bits : 0 - 7 (8 bit)
MON : Timestamp Month
bits : 8 - 15 (8 bit)
YEAR : Timestamp Year
bits : 16 - 19 (4 bit)
SUBSTEP : Sub-step of Core release
bits : 20 - 23 (4 bit)
STEP : Step of Core release
bits : 24 - 27 (4 bit)
REL : Core release
bits : 28 - 31 (4 bit)
FDCAN Test Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LBCK : Loop Back mode
bits : 4 - 4 (1 bit)
access : read-write
TX : Loop Back mode
bits : 5 - 6 (2 bit)
access : read-write
RX : Control of Transmit Pin
bits : 7 - 7 (1 bit)
access : read-only
FDCAN TT Trigger Memory Configuration Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDIV : PDIV
bits : 0 - 3 (4 bit)
FDCAN RAM Watchdog Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDC : Watchdog configuration
bits : 0 - 7 (8 bit)
access : read-write
WDV : Watchdog value
bits : 8 - 15 (8 bit)
access : read-only
FDCAN CC Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initialization
bits : 0 - 0 (1 bit)
CCE : Configuration Change Enable
bits : 1 - 1 (1 bit)
ASM : ASM Restricted Operation Mode
bits : 2 - 2 (1 bit)
CSA : Clock Stop Acknowledge
bits : 3 - 3 (1 bit)
CSR : Clock Stop Request
bits : 4 - 4 (1 bit)
MON : Bus Monitoring Mode
bits : 5 - 5 (1 bit)
DAR : Disable Automatic Retransmission
bits : 6 - 6 (1 bit)
TEST : Test Mode Enable
bits : 7 - 7 (1 bit)
FDOE : FD Operation Enable
bits : 8 - 8 (1 bit)
BSE : FDCAN Bit Rate Switching
bits : 9 - 9 (1 bit)
PXHD : Protocol Exception Handling Disable
bits : 12 - 12 (1 bit)
EFBI : Edge Filtering during Bus Integration
bits : 13 - 13 (1 bit)
TXP : TXP
bits : 14 - 14 (1 bit)
NISO : Non ISO Operation
bits : 15 - 15 (1 bit)
FDCAN Nominal Bit Timing and Prescaler Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEG2 : Nominal Time segment after sample point
bits : 0 - 6 (7 bit)
NTSEG1 : Nominal Time segment before sample point
bits : 8 - 15 (8 bit)
NBRP : Bit Rate Prescaler
bits : 16 - 24 (9 bit)
NSJW : NSJW: Nominal (Re)Synchronization Jump Width
bits : 25 - 31 (7 bit)
FDCAN Timestamp Counter Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSS : Timestamp Select
bits : 0 - 1 (2 bit)
TCP : Timestamp Counter Prescaler
bits : 16 - 19 (4 bit)
FDCAN Timestamp Counter Value Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSC : Timestamp Counter
bits : 0 - 15 (16 bit)
FDCAN Timeout Counter Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETOC : Enable Timeout Counter
bits : 0 - 0 (1 bit)
TOS : Timeout Select
bits : 1 - 2 (2 bit)
TOP : Timeout Period
bits : 16 - 31 (16 bit)
FDCAN Timeout Counter Value Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOC : Timeout Counter
bits : 0 - 15 (16 bit)
FDCAN Core Release Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ETV : Endiannes Test Value
bits : 0 - 31 (32 bit)
FDCAN Error Counter Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEC : Transmit Error Counter
bits : 0 - 7 (8 bit)
access : read-only
REC : Receive Error Counter
bits : 8 - 14 (7 bit)
access : read-only
RP : Receive Error Passive
bits : 15 - 15 (1 bit)
access : read-write
CEL : AN Error Logging
bits : 16 - 23 (8 bit)
access : read-write
FDCAN Protocol Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEC : Last Error Code
bits : 0 - 2 (3 bit)
access : read-write
ACT : Activity
bits : 3 - 4 (2 bit)
access : read-only
EP : Error Passive
bits : 5 - 5 (1 bit)
access : read-only
EW : Warning Status
bits : 6 - 6 (1 bit)
access : read-only
BO : Bus_Off Status
bits : 7 - 7 (1 bit)
access : read-only
DLEC : Data Last Error Code
bits : 8 - 10 (3 bit)
access : read-write
RESI : ESI flag of last received FDCAN Message
bits : 11 - 11 (1 bit)
access : read-write
RBRS : BRS flag of last received FDCAN Message
bits : 12 - 12 (1 bit)
access : read-write
REDL : Received FDCAN Message
bits : 13 - 13 (1 bit)
access : read-write
PXE : Protocol Exception Event
bits : 14 - 14 (1 bit)
access : read-write
TDCV : Transmitter Delay Compensation Value
bits : 16 - 22 (7 bit)
access : read-only
FDCAN Transmitter Delay Compensation Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDCF : Transmitter Delay Compensation Filter Window Length
bits : 0 - 6 (7 bit)
TDCO : Transmitter Delay Compensation Offset
bits : 8 - 14 (7 bit)
FDCAN Interrupt Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0N : RF0N
bits : 0 - 0 (1 bit)
RF0F : RF0F
bits : 1 - 1 (1 bit)
RF0L : RF0L
bits : 2 - 2 (1 bit)
RF1N : RF1N
bits : 3 - 3 (1 bit)
RF1F : RF1F
bits : 4 - 4 (1 bit)
RF1L : RF1L
bits : 5 - 5 (1 bit)
HPM : HPM
bits : 6 - 6 (1 bit)
TC : TC
bits : 7 - 7 (1 bit)
TCF : TCF
bits : 8 - 8 (1 bit)
TFE : TFE
bits : 9 - 9 (1 bit)
TEFN : TEFN
bits : 10 - 10 (1 bit)
TEFF : TEFF
bits : 11 - 11 (1 bit)
TEFL : TEFL
bits : 12 - 12 (1 bit)
TSW : TSW
bits : 13 - 13 (1 bit)
MRAF : MRAF
bits : 14 - 14 (1 bit)
TOO : TOO
bits : 15 - 15 (1 bit)
ELO : ELO
bits : 16 - 16 (1 bit)
EP : EP
bits : 17 - 17 (1 bit)
EW : EW
bits : 18 - 18 (1 bit)
BO : BO
bits : 19 - 19 (1 bit)
WDI : WDI
bits : 20 - 20 (1 bit)
PEA : PEA
bits : 21 - 21 (1 bit)
PED : PED
bits : 22 - 22 (1 bit)
ARA : ARA
bits : 23 - 23 (1 bit)
FDCAN Interrupt Enable Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0NE : Rx FIFO 0 New Message Enable
bits : 0 - 0 (1 bit)
RF0FE : Rx FIFO 0 Full Enable
bits : 1 - 1 (1 bit)
RF0LE : Rx FIFO 0 Message Lost Enable
bits : 2 - 2 (1 bit)
RF1NE : Rx FIFO 1 New Message Enable
bits : 3 - 3 (1 bit)
RF1FE : Rx FIFO 1 Watermark Reached Enable
bits : 4 - 4 (1 bit)
RF1LE : Rx FIFO 1 Message Lost Enable
bits : 5 - 5 (1 bit)
HPME : High Priority Message Enable
bits : 6 - 6 (1 bit)
TCE : Transmission Completed Enable
bits : 7 - 7 (1 bit)
TCFE : Transmission Cancellation Finished Enable
bits : 8 - 8 (1 bit)
TEFE : Tx FIFO Empty Enable
bits : 9 - 9 (1 bit)
TEFNE : Tx Event FIFO New Entry Enable
bits : 10 - 10 (1 bit)
TEFFE : Tx Event FIFO Full Enable
bits : 11 - 11 (1 bit)
TEFLE : Tx Event FIFO Element Lost Enable
bits : 12 - 12 (1 bit)
MRAFE : Message RAM Access Failure Enable
bits : 13 - 13 (1 bit)
TOOE : Timeout Occurred Enable
bits : 14 - 14 (1 bit)
ELOE : Error Logging Overflow Enable
bits : 15 - 15 (1 bit)
EPE : Error Passive Enable
bits : 16 - 16 (1 bit)
EWE : Warning Status Enable
bits : 17 - 17 (1 bit)
BOE : Bus_Off Status Enable
bits : 18 - 18 (1 bit)
WDIE : Watchdog Interrupt Enable
bits : 19 - 19 (1 bit)
PEAE : Protocol Error in Arbitration Phase Enable
bits : 20 - 20 (1 bit)
PEDE : Protocol Error in Data Phase Enable
bits : 21 - 21 (1 bit)
ARAE : Access to Reserved Address Enable
bits : 22 - 22 (1 bit)
FDCAN Interrupt Line Select Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RxFIFO0 : RxFIFO0
bits : 0 - 0 (1 bit)
RxFIFO1 : RxFIFO1
bits : 1 - 1 (1 bit)
SMSG : SMSG
bits : 2 - 2 (1 bit)
TFERR : TFERR
bits : 3 - 3 (1 bit)
MISC : MISC
bits : 4 - 4 (1 bit)
BERR : BERR
bits : 5 - 5 (1 bit)
PERR : PERR
bits : 6 - 6 (1 bit)
FDCAN Interrupt Line Enable Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EINT0 : Enable Interrupt Line 0
bits : 0 - 0 (1 bit)
EINT1 : Enable Interrupt Line 1
bits : 1 - 1 (1 bit)
FDCAN Global Filter Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRFE : Reject Remote Frames Extended
bits : 0 - 0 (1 bit)
RRFS : Reject Remote Frames Standard
bits : 1 - 1 (1 bit)
ANFE : Accept Non-matching Frames Extended
bits : 2 - 3 (2 bit)
ANFS : Accept Non-matching Frames Standard
bits : 4 - 5 (2 bit)
F1OM : F1OM
bits : 8 - 8 (1 bit)
F0OM : F0OM
bits : 9 - 9 (1 bit)
LSS : LSS
bits : 16 - 20 (5 bit)
LSE : LSE
bits : 24 - 27 (4 bit)
FDCAN Extended ID and Mask Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIDM : Extended ID Mask
bits : 0 - 28 (29 bit)
FDCAN High Priority Message Status Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIDX : Buffer Index
bits : 0 - 2 (3 bit)
MSI : Message Storage Indicator
bits : 6 - 7 (2 bit)
FIDX : Filter Index
bits : 8 - 12 (5 bit)
FLST : Filter List
bits : 15 - 15 (1 bit)
FDCAN Rx FIFO 0 Status Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0FL : Rx FIFO 0 Fill Level
bits : 0 - 3 (4 bit)
F0GI : Rx FIFO 0 Get Index
bits : 8 - 9 (2 bit)
F0PI : Rx FIFO 0 Put Index
bits : 16 - 17 (2 bit)
F0F : Rx FIFO 0 Full
bits : 24 - 24 (1 bit)
RF0L : Rx FIFO 0 Message Lost
bits : 25 - 25 (1 bit)
CAN Rx FIFO 0 Acknowledge Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0AI : Rx FIFO 0 Acknowledge Index
bits : 0 - 2 (3 bit)
FDCAN Rx FIFO 1 Status Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1FL : Rx FIFO 1 Fill Level
bits : 0 - 3 (4 bit)
access : read-write
F1GI : Rx FIFO 1 Get Index
bits : 8 - 9 (2 bit)
access : read-only
F1PI : Rx FIFO 1 Put Index
bits : 16 - 17 (2 bit)
access : read-only
F1F : Rx FIFO 1 Full
bits : 24 - 24 (1 bit)
access : read-only
RF1L : Rx FIFO 1 Message Lost
bits : 25 - 25 (1 bit)
access : read-only
FDCAN Rx FIFO 1 Acknowledge Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1AI : Rx FIFO 1 Acknowledge Index
bits : 0 - 2 (3 bit)
FDCAN Data Bit Timing and Prescaler Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSJW : Synchronization Jump Width
bits : 0 - 3 (4 bit)
DTSEG2 : Data time segment after sample point
bits : 4 - 7 (4 bit)
DTSEG1 : Data time segment after sample point
bits : 8 - 12 (5 bit)
DBRP : Data BIt Rate Prescaler
bits : 16 - 20 (5 bit)
TDC : Transceiver Delay Compensation
bits : 23 - 23 (1 bit)
FDCAN Tx buffer configuration register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFQM : Tx FIFO/Queue Mode
bits : 24 - 24 (1 bit)
FDCAN Tx FIFO/Queue Status Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TFFL : Tx FIFO Free Level
bits : 0 - 2 (3 bit)
TFGI : TFGI
bits : 8 - 9 (2 bit)
TFQPI : Tx FIFO/Queue Put Index
bits : 16 - 17 (2 bit)
TFQF : Tx FIFO/Queue Full
bits : 21 - 21 (1 bit)
FDCAN Tx Buffer Request Pending Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TRP : Transmission Request Pending
bits : 0 - 2 (3 bit)
FDCAN Tx Buffer Add Request Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR : Add Request
bits : 0 - 2 (3 bit)
FDCAN Tx Buffer Cancellation Request Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CR : Cancellation Request
bits : 0 - 2 (3 bit)
FDCAN Tx Buffer Transmission Occurred Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TO : Transmission Occurred.
bits : 0 - 2 (3 bit)
FDCAN Tx Buffer Cancellation Finished Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CF : Cancellation Finished
bits : 0 - 2 (3 bit)
FDCAN Tx Buffer Transmission Interrupt Enable Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIE : Transmission Interrupt Enable
bits : 0 - 2 (3 bit)
FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CF : Cancellation Finished Interrupt Enable
bits : 0 - 2 (3 bit)
FDCAN Tx Event FIFO Status Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EFFL : Event FIFO Fill Level
bits : 0 - 2 (3 bit)
EFGI : Event FIFO Get Index.
bits : 8 - 9 (2 bit)
EFPI : Event FIFO Put Index
bits : 16 - 17 (2 bit)
EFF : Event FIFO Full.
bits : 24 - 24 (1 bit)
TEFL : Tx Event FIFO Element Lost.
bits : 25 - 25 (1 bit)
FDCAN Tx Event FIFO Acknowledge Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFAI : Event FIFO Acknowledge Index
bits : 0 - 1 (2 bit)
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