\n
address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
Source Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Interrupt Vector Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQV : Interrupt Vector Register
bits : 0 - 31 (32 bit)
access : read-only
FIQ Interrupt Vector Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FIQV : FIQ Vector Register
bits : 0 - 31 (32 bit)
access : read-only
Source Mode Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Interrupt Status Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQID : Current Interrupt Identifier
bits : 0 - 4 (5 bit)
access : read-only
Interrupt Pending Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FIQ : Interrupt Pending
bits : 0 - 0 (1 bit)
access : read-only
SYS : Interrupt Pending
bits : 1 - 1 (1 bit)
access : read-only
PID2 : Interrupt Pending
bits : 2 - 2 (1 bit)
access : read-only
PID3 : Interrupt Pending
bits : 3 - 3 (1 bit)
access : read-only
PID4 : Interrupt Pending
bits : 4 - 4 (1 bit)
access : read-only
PID5 : Interrupt Pending
bits : 5 - 5 (1 bit)
access : read-only
PID6 : Interrupt Pending
bits : 6 - 6 (1 bit)
access : read-only
PID7 : Interrupt Pending
bits : 7 - 7 (1 bit)
access : read-only
PID8 : Interrupt Pending
bits : 8 - 8 (1 bit)
access : read-only
PID9 : Interrupt Pending
bits : 9 - 9 (1 bit)
access : read-only
PID10 : Interrupt Pending
bits : 10 - 10 (1 bit)
access : read-only
PID11 : Interrupt Pending
bits : 11 - 11 (1 bit)
access : read-only
PID12 : Interrupt Pending
bits : 12 - 12 (1 bit)
access : read-only
PID13 : Interrupt Pending
bits : 13 - 13 (1 bit)
access : read-only
PID14 : Interrupt Pending
bits : 14 - 14 (1 bit)
access : read-only
PID15 : Interrupt Pending
bits : 15 - 15 (1 bit)
access : read-only
PID16 : Interrupt Pending
bits : 16 - 16 (1 bit)
access : read-only
PID17 : Interrupt Pending
bits : 17 - 17 (1 bit)
access : read-only
PID18 : Interrupt Pending
bits : 18 - 18 (1 bit)
access : read-only
PID19 : Interrupt Pending
bits : 19 - 19 (1 bit)
access : read-only
PID20 : Interrupt Pending
bits : 20 - 20 (1 bit)
access : read-only
PID21 : Interrupt Pending
bits : 21 - 21 (1 bit)
access : read-only
PID22 : Interrupt Pending
bits : 22 - 22 (1 bit)
access : read-only
PID23 : Interrupt Pending
bits : 23 - 23 (1 bit)
access : read-only
PID24 : Interrupt Pending
bits : 24 - 24 (1 bit)
access : read-only
PID25 : Interrupt Pending
bits : 25 - 25 (1 bit)
access : read-only
PID26 : Interrupt Pending
bits : 26 - 26 (1 bit)
access : read-only
PID27 : Interrupt Pending
bits : 27 - 27 (1 bit)
access : read-only
PID28 : Interrupt Pending
bits : 28 - 28 (1 bit)
access : read-only
PID29 : Interrupt Pending
bits : 29 - 29 (1 bit)
access : read-only
PID30 : Interrupt Pending
bits : 30 - 30 (1 bit)
access : read-only
PID31 : Interrupt Pending
bits : 31 - 31 (1 bit)
access : read-only
Source Vector Register
address_offset : 0x10D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Interrupt Mask Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FIQ : Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
SYS : Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
PID2 : Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
PID3 : Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
PID4 : Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
PID5 : Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
PID6 : Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
PID7 : Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only
PID8 : Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
PID9 : Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
PID10 : Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
PID11 : Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only
PID12 : Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only
PID13 : Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
PID14 : Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only
PID15 : Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only
PID16 : Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
PID17 : Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only
PID18 : Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only
PID19 : Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only
PID20 : Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only
PID21 : Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only
PID22 : Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only
PID23 : Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only
PID24 : Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only
PID25 : Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only
PID26 : Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only
PID27 : Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only
PID28 : Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only
PID29 : Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-only
PID30 : Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only
PID31 : Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-only
Core Interrupt Status Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFIQ : NFIQ Status
bits : 0 - 0 (1 bit)
access : read-only
NIRQ : NIRQ Status
bits : 1 - 1 (1 bit)
access : read-only
Source Vector Register
address_offset : 0x11B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Interrupt Enable Command Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FIQ : Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
SYS : Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
PID2 : Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
PID3 : Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
PID4 : Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
PID5 : Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
PID6 : Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
PID7 : Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
PID8 : Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
PID9 : Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
PID10 : Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
PID11 : Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
PID12 : Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
PID13 : Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
PID14 : Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
PID15 : Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
PID16 : Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
PID17 : Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only
PID18 : Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
PID19 : Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
PID20 : Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only
PID21 : Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only
PID22 : Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only
PID23 : Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only
PID24 : Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only
PID25 : Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only
PID26 : Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only
PID27 : Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only
PID28 : Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only
PID29 : Interrupt Enable
bits : 29 - 29 (1 bit)
access : write-only
PID30 : Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only
PID31 : Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
Interrupt Disable Command Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FIQ : Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
SYS : Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
PID2 : Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
PID3 : Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
PID4 : Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
PID5 : Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
PID6 : Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
PID7 : Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
PID8 : Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
PID9 : Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
PID10 : Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
PID11 : Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
PID12 : Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
PID13 : Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
PID14 : Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
PID15 : Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
PID16 : Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
PID17 : Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only
PID18 : Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
PID19 : Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
PID20 : Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only
PID21 : Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only
PID22 : Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only
PID23 : Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only
PID24 : Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only
PID25 : Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only
PID26 : Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only
PID27 : Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only
PID28 : Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only
PID29 : Interrupt Disable
bits : 29 - 29 (1 bit)
access : write-only
PID30 : Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only
PID31 : Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
Interrupt Clear Command Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FIQ : Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
SYS : Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
PID2 : Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
PID3 : Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
PID4 : Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
PID5 : Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
PID6 : Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
PID7 : Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
PID8 : Interrupt Clear
bits : 8 - 8 (1 bit)
access : write-only
PID9 : Interrupt Clear
bits : 9 - 9 (1 bit)
access : write-only
PID10 : Interrupt Clear
bits : 10 - 10 (1 bit)
access : write-only
PID11 : Interrupt Clear
bits : 11 - 11 (1 bit)
access : write-only
PID12 : Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only
PID13 : Interrupt Clear
bits : 13 - 13 (1 bit)
access : write-only
PID14 : Interrupt Clear
bits : 14 - 14 (1 bit)
access : write-only
PID15 : Interrupt Clear
bits : 15 - 15 (1 bit)
access : write-only
PID16 : Interrupt Clear
bits : 16 - 16 (1 bit)
access : write-only
PID17 : Interrupt Clear
bits : 17 - 17 (1 bit)
access : write-only
PID18 : Interrupt Clear
bits : 18 - 18 (1 bit)
access : write-only
PID19 : Interrupt Clear
bits : 19 - 19 (1 bit)
access : write-only
PID20 : Interrupt Clear
bits : 20 - 20 (1 bit)
access : write-only
PID21 : Interrupt Clear
bits : 21 - 21 (1 bit)
access : write-only
PID22 : Interrupt Clear
bits : 22 - 22 (1 bit)
access : write-only
PID23 : Interrupt Clear
bits : 23 - 23 (1 bit)
access : write-only
PID24 : Interrupt Clear
bits : 24 - 24 (1 bit)
access : write-only
PID25 : Interrupt Clear
bits : 25 - 25 (1 bit)
access : write-only
PID26 : Interrupt Clear
bits : 26 - 26 (1 bit)
access : write-only
PID27 : Interrupt Clear
bits : 27 - 27 (1 bit)
access : write-only
PID28 : Interrupt Clear
bits : 28 - 28 (1 bit)
access : write-only
PID29 : Interrupt Clear
bits : 29 - 29 (1 bit)
access : write-only
PID30 : Interrupt Clear
bits : 30 - 30 (1 bit)
access : write-only
PID31 : Interrupt Clear
bits : 31 - 31 (1 bit)
access : write-only
Source Vector Register
address_offset : 0x1294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Interrupt Set Command Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FIQ : Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
SYS : Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
PID2 : Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
PID3 : Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
PID4 : Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
PID5 : Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
PID6 : Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
PID7 : Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
PID8 : Interrupt Set
bits : 8 - 8 (1 bit)
access : write-only
PID9 : Interrupt Set
bits : 9 - 9 (1 bit)
access : write-only
PID10 : Interrupt Set
bits : 10 - 10 (1 bit)
access : write-only
PID11 : Interrupt Set
bits : 11 - 11 (1 bit)
access : write-only
PID12 : Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only
PID13 : Interrupt Set
bits : 13 - 13 (1 bit)
access : write-only
PID14 : Interrupt Set
bits : 14 - 14 (1 bit)
access : write-only
PID15 : Interrupt Set
bits : 15 - 15 (1 bit)
access : write-only
PID16 : Interrupt Set
bits : 16 - 16 (1 bit)
access : write-only
PID17 : Interrupt Set
bits : 17 - 17 (1 bit)
access : write-only
PID18 : Interrupt Set
bits : 18 - 18 (1 bit)
access : write-only
PID19 : Interrupt Set
bits : 19 - 19 (1 bit)
access : write-only
PID20 : Interrupt Set
bits : 20 - 20 (1 bit)
access : write-only
PID21 : Interrupt Set
bits : 21 - 21 (1 bit)
access : write-only
PID22 : Interrupt Set
bits : 22 - 22 (1 bit)
access : write-only
PID23 : Interrupt Set
bits : 23 - 23 (1 bit)
access : write-only
PID24 : Interrupt Set
bits : 24 - 24 (1 bit)
access : write-only
PID25 : Interrupt Set
bits : 25 - 25 (1 bit)
access : write-only
PID26 : Interrupt Set
bits : 26 - 26 (1 bit)
access : write-only
PID27 : Interrupt Set
bits : 27 - 27 (1 bit)
access : write-only
PID28 : Interrupt Set
bits : 28 - 28 (1 bit)
access : write-only
PID29 : Interrupt Set
bits : 29 - 29 (1 bit)
access : write-only
PID30 : Interrupt Set
bits : 30 - 30 (1 bit)
access : write-only
PID31 : Interrupt Set
bits : 31 - 31 (1 bit)
access : write-only
End of Interrupt Command Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
Spurious Interrupt Vector Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIVR : Spurious Interrupt Vector Register
bits : 0 - 31 (32 bit)
access : read-write
Source Vector Register
address_offset : 0x137C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Debug Control Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROT : Protection Mode
bits : 0 - 0 (1 bit)
access : read-write
GMSK : General Mask
bits : 1 - 1 (1 bit)
access : read-write
Fast Forcing Enable Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SYS : Fast Forcing Enable
bits : 1 - 1 (1 bit)
access : write-only
PID2 : Fast Forcing Enable
bits : 2 - 2 (1 bit)
access : write-only
PID3 : Fast Forcing Enable
bits : 3 - 3 (1 bit)
access : write-only
PID4 : Fast Forcing Enable
bits : 4 - 4 (1 bit)
access : write-only
PID5 : Fast Forcing Enable
bits : 5 - 5 (1 bit)
access : write-only
PID6 : Fast Forcing Enable
bits : 6 - 6 (1 bit)
access : write-only
PID7 : Fast Forcing Enable
bits : 7 - 7 (1 bit)
access : write-only
PID8 : Fast Forcing Enable
bits : 8 - 8 (1 bit)
access : write-only
PID9 : Fast Forcing Enable
bits : 9 - 9 (1 bit)
access : write-only
PID10 : Fast Forcing Enable
bits : 10 - 10 (1 bit)
access : write-only
PID11 : Fast Forcing Enable
bits : 11 - 11 (1 bit)
access : write-only
PID12 : Fast Forcing Enable
bits : 12 - 12 (1 bit)
access : write-only
PID13 : Fast Forcing Enable
bits : 13 - 13 (1 bit)
access : write-only
PID14 : Fast Forcing Enable
bits : 14 - 14 (1 bit)
access : write-only
PID15 : Fast Forcing Enable
bits : 15 - 15 (1 bit)
access : write-only
PID16 : Fast Forcing Enable
bits : 16 - 16 (1 bit)
access : write-only
PID17 : Fast Forcing Enable
bits : 17 - 17 (1 bit)
access : write-only
PID18 : Fast Forcing Enable
bits : 18 - 18 (1 bit)
access : write-only
PID19 : Fast Forcing Enable
bits : 19 - 19 (1 bit)
access : write-only
PID20 : Fast Forcing Enable
bits : 20 - 20 (1 bit)
access : write-only
PID21 : Fast Forcing Enable
bits : 21 - 21 (1 bit)
access : write-only
PID22 : Fast Forcing Enable
bits : 22 - 22 (1 bit)
access : write-only
PID23 : Fast Forcing Enable
bits : 23 - 23 (1 bit)
access : write-only
PID24 : Fast Forcing Enable
bits : 24 - 24 (1 bit)
access : write-only
PID25 : Fast Forcing Enable
bits : 25 - 25 (1 bit)
access : write-only
PID26 : Fast Forcing Enable
bits : 26 - 26 (1 bit)
access : write-only
PID27 : Fast Forcing Enable
bits : 27 - 27 (1 bit)
access : write-only
PID28 : Fast Forcing Enable
bits : 28 - 28 (1 bit)
access : write-only
PID29 : Fast Forcing Enable
bits : 29 - 29 (1 bit)
access : write-only
PID30 : Fast Forcing Enable
bits : 30 - 30 (1 bit)
access : write-only
PID31 : Fast Forcing Enable
bits : 31 - 31 (1 bit)
access : write-only
Fast Forcing Disable Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SYS : Fast Forcing Disable
bits : 1 - 1 (1 bit)
access : write-only
PID2 : Fast Forcing Disable
bits : 2 - 2 (1 bit)
access : write-only
PID3 : Fast Forcing Disable
bits : 3 - 3 (1 bit)
access : write-only
PID4 : Fast Forcing Disable
bits : 4 - 4 (1 bit)
access : write-only
PID5 : Fast Forcing Disable
bits : 5 - 5 (1 bit)
access : write-only
PID6 : Fast Forcing Disable
bits : 6 - 6 (1 bit)
access : write-only
PID7 : Fast Forcing Disable
bits : 7 - 7 (1 bit)
access : write-only
PID8 : Fast Forcing Disable
bits : 8 - 8 (1 bit)
access : write-only
PID9 : Fast Forcing Disable
bits : 9 - 9 (1 bit)
access : write-only
PID10 : Fast Forcing Disable
bits : 10 - 10 (1 bit)
access : write-only
PID11 : Fast Forcing Disable
bits : 11 - 11 (1 bit)
access : write-only
PID12 : Fast Forcing Disable
bits : 12 - 12 (1 bit)
access : write-only
PID13 : Fast Forcing Disable
bits : 13 - 13 (1 bit)
access : write-only
PID14 : Fast Forcing Disable
bits : 14 - 14 (1 bit)
access : write-only
PID15 : Fast Forcing Disable
bits : 15 - 15 (1 bit)
access : write-only
PID16 : Fast Forcing Disable
bits : 16 - 16 (1 bit)
access : write-only
PID17 : Fast Forcing Disable
bits : 17 - 17 (1 bit)
access : write-only
PID18 : Fast Forcing Disable
bits : 18 - 18 (1 bit)
access : write-only
PID19 : Fast Forcing Disable
bits : 19 - 19 (1 bit)
access : write-only
PID20 : Fast Forcing Disable
bits : 20 - 20 (1 bit)
access : write-only
PID21 : Fast Forcing Disable
bits : 21 - 21 (1 bit)
access : write-only
PID22 : Fast Forcing Disable
bits : 22 - 22 (1 bit)
access : write-only
PID23 : Fast Forcing Disable
bits : 23 - 23 (1 bit)
access : write-only
PID24 : Fast Forcing Disable
bits : 24 - 24 (1 bit)
access : write-only
PID25 : Fast Forcing Disable
bits : 25 - 25 (1 bit)
access : write-only
PID26 : Fast Forcing Disable
bits : 26 - 26 (1 bit)
access : write-only
PID27 : Fast Forcing Disable
bits : 27 - 27 (1 bit)
access : write-only
PID28 : Fast Forcing Disable
bits : 28 - 28 (1 bit)
access : write-only
PID29 : Fast Forcing Disable
bits : 29 - 29 (1 bit)
access : write-only
PID30 : Fast Forcing Disable
bits : 30 - 30 (1 bit)
access : write-only
PID31 : Fast Forcing Disable
bits : 31 - 31 (1 bit)
access : write-only
Source Vector Register
address_offset : 0x1468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Fast Forcing Status Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYS : Fast Forcing Status
bits : 1 - 1 (1 bit)
access : read-only
PID2 : Fast Forcing Status
bits : 2 - 2 (1 bit)
access : read-only
PID3 : Fast Forcing Status
bits : 3 - 3 (1 bit)
access : read-only
PID4 : Fast Forcing Status
bits : 4 - 4 (1 bit)
access : read-only
PID5 : Fast Forcing Status
bits : 5 - 5 (1 bit)
access : read-only
PID6 : Fast Forcing Status
bits : 6 - 6 (1 bit)
access : read-only
PID7 : Fast Forcing Status
bits : 7 - 7 (1 bit)
access : read-only
PID8 : Fast Forcing Status
bits : 8 - 8 (1 bit)
access : read-only
PID9 : Fast Forcing Status
bits : 9 - 9 (1 bit)
access : read-only
PID10 : Fast Forcing Status
bits : 10 - 10 (1 bit)
access : read-only
PID11 : Fast Forcing Status
bits : 11 - 11 (1 bit)
access : read-only
PID12 : Fast Forcing Status
bits : 12 - 12 (1 bit)
access : read-only
PID13 : Fast Forcing Status
bits : 13 - 13 (1 bit)
access : read-only
PID14 : Fast Forcing Status
bits : 14 - 14 (1 bit)
access : read-only
PID15 : Fast Forcing Status
bits : 15 - 15 (1 bit)
access : read-only
PID16 : Fast Forcing Status
bits : 16 - 16 (1 bit)
access : read-only
PID17 : Fast Forcing Status
bits : 17 - 17 (1 bit)
access : read-only
PID18 : Fast Forcing Status
bits : 18 - 18 (1 bit)
access : read-only
PID19 : Fast Forcing Status
bits : 19 - 19 (1 bit)
access : read-only
PID20 : Fast Forcing Status
bits : 20 - 20 (1 bit)
access : read-only
PID21 : Fast Forcing Status
bits : 21 - 21 (1 bit)
access : read-only
PID22 : Fast Forcing Status
bits : 22 - 22 (1 bit)
access : read-only
PID23 : Fast Forcing Status
bits : 23 - 23 (1 bit)
access : read-only
PID24 : Fast Forcing Status
bits : 24 - 24 (1 bit)
access : read-only
PID25 : Fast Forcing Status
bits : 25 - 25 (1 bit)
access : read-only
PID26 : Fast Forcing Status
bits : 26 - 26 (1 bit)
access : read-only
PID27 : Fast Forcing Status
bits : 27 - 27 (1 bit)
access : read-only
PID28 : Fast Forcing Status
bits : 28 - 28 (1 bit)
access : read-only
PID29 : Fast Forcing Status
bits : 29 - 29 (1 bit)
access : read-only
PID30 : Fast Forcing Status
bits : 30 - 30 (1 bit)
access : read-only
PID31 : Fast Forcing Status
bits : 31 - 31 (1 bit)
access : read-only
Source Vector Register
address_offset : 0x1558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Vector Register
address_offset : 0x164C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0x1744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Vector Register
address_offset : 0x1840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Mode Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Write Protect Mode Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protect KEY
bits : 8 - 31 (24 bit)
access : read-write
Write Protect Status Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protect Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protect Violation Source
bits : 8 - 23 (16 bit)
access : read-only
Source Vector Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Mode Register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Mode Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Mode Register
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Mode Register
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Mode Register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Mode Register
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Mode Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Mode Register
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Mode Register
address_offset : 0x6CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0x6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Mode Register
address_offset : 0x744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Vector Register
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Vector Register
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Vector Register
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0xBE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0xCAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Vector Register
address_offset : 0xD78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Mode Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write
SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : INT_LEVEL_SENSITIVE
High level Sensitive for internal sourceLow level Sensitive for external source
0x1 : INT_EDGE_TRIGGERED
Positive edge triggered for internal sourceNegative edge triggered for external source
0x2 : EXT_HIGH_LEVEL
High level Sensitive for internal sourceHigh level Sensitive for external source
0x3 : EXT_POSITIVE_EDGE
Positive edge triggered for internal sourcePositive edge triggered for external source
End of enumeration elements list.
Source Vector Register
address_offset : 0xE48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Vector Register
address_offset : 0xF1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
Source Vector Register
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write
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