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FMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC00 byte (0x0)
mem_usage : registers
protection : not protected

Registers

BCR1

BCR3

BWTR1

BWTR2

BWTR3

BWTR4

BTR3

BCR4

BTR4

BTR1

PCR2

SR2

PMEM2

PATT2

ECCR2

BCR2

PCR3

SR3

PMEM3

PATT3

ECCR3

PCR4

SR4

PMEM4

PATT4

PIO4

BTR2


BCR1

SRAM/NOR-Flash chip-select control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR1 BCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBKEN MUXEN MTYP MWID FACCEN BURSTEN WAITPOL WAITCFG WREN WAITEN EXTMOD ASYNCWAIT CBURSTRW CCLKEN

MBKEN : MBKEN
bits : 0 - 0 (1 bit)

MUXEN : MUXEN
bits : 1 - 1 (1 bit)

MTYP : MTYP
bits : 2 - 3 (2 bit)

MWID : MWID
bits : 4 - 5 (2 bit)

FACCEN : FACCEN
bits : 6 - 6 (1 bit)

BURSTEN : BURSTEN
bits : 8 - 8 (1 bit)

WAITPOL : WAITPOL
bits : 9 - 9 (1 bit)

WAITCFG : WAITCFG
bits : 11 - 11 (1 bit)

WREN : WREN
bits : 12 - 12 (1 bit)

WAITEN : WAITEN
bits : 13 - 13 (1 bit)

EXTMOD : EXTMOD
bits : 14 - 14 (1 bit)

ASYNCWAIT : ASYNCWAIT
bits : 15 - 15 (1 bit)

CBURSTRW : CBURSTRW
bits : 19 - 19 (1 bit)

CCLKEN : CCLKEN
bits : 20 - 20 (1 bit)


BCR3

SRAM/NOR-Flash chip-select control register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR3 BCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBKEN MUXEN MTYP MWID FACCEN BURSTEN WAITPOL WRAPMOD WAITCFG WREN WAITEN EXTMOD ASYNCWAIT CBURSTRW

MBKEN : MBKEN
bits : 0 - 0 (1 bit)

MUXEN : MUXEN
bits : 1 - 1 (1 bit)

MTYP : MTYP
bits : 2 - 3 (2 bit)

MWID : MWID
bits : 4 - 5 (2 bit)

FACCEN : FACCEN
bits : 6 - 6 (1 bit)

BURSTEN : BURSTEN
bits : 8 - 8 (1 bit)

WAITPOL : WAITPOL
bits : 9 - 9 (1 bit)

WRAPMOD : WRAPMOD
bits : 10 - 10 (1 bit)

WAITCFG : WAITCFG
bits : 11 - 11 (1 bit)

WREN : WREN
bits : 12 - 12 (1 bit)

WAITEN : WAITEN
bits : 13 - 13 (1 bit)

EXTMOD : EXTMOD
bits : 14 - 14 (1 bit)

ASYNCWAIT : ASYNCWAIT
bits : 15 - 15 (1 bit)

CBURSTRW : CBURSTRW
bits : 19 - 19 (1 bit)


BWTR1

SRAM/NOR-Flash write timing registers 1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BWTR1 BWTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BWTR2

SRAM/NOR-Flash write timing registers 2
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BWTR2 BWTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BWTR3

SRAM/NOR-Flash write timing registers 3
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BWTR3 BWTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BWTR4

SRAM/NOR-Flash write timing registers 4
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BWTR4 BWTR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BTR3

SRAM/NOR-Flash chip-select timing register 3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR3 BTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

BUSTURN : BUSTURN
bits : 16 - 19 (4 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BCR4

SRAM/NOR-Flash chip-select control register 4
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR4 BCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBKEN MUXEN MTYP MWID FACCEN BURSTEN WAITPOL WRAPMOD WAITCFG WREN WAITEN EXTMOD ASYNCWAIT CBURSTRW

MBKEN : MBKEN
bits : 0 - 0 (1 bit)

MUXEN : MUXEN
bits : 1 - 1 (1 bit)

MTYP : MTYP
bits : 2 - 3 (2 bit)

MWID : MWID
bits : 4 - 5 (2 bit)

FACCEN : FACCEN
bits : 6 - 6 (1 bit)

BURSTEN : BURSTEN
bits : 8 - 8 (1 bit)

WAITPOL : WAITPOL
bits : 9 - 9 (1 bit)

WRAPMOD : WRAPMOD
bits : 10 - 10 (1 bit)

WAITCFG : WAITCFG
bits : 11 - 11 (1 bit)

WREN : WREN
bits : 12 - 12 (1 bit)

WAITEN : WAITEN
bits : 13 - 13 (1 bit)

EXTMOD : EXTMOD
bits : 14 - 14 (1 bit)

ASYNCWAIT : ASYNCWAIT
bits : 15 - 15 (1 bit)

CBURSTRW : CBURSTRW
bits : 19 - 19 (1 bit)


BTR4

SRAM/NOR-Flash chip-select timing register 4
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR4 BTR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

BUSTURN : BUSTURN
bits : 16 - 19 (4 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


BTR1

SRAM/NOR-Flash chip-select timing register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR1 BTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

BUSTURN : BUSTURN
bits : 16 - 19 (4 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)


PCR2

PC Card/NAND Flash control register 2
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR2 PCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWAITEN PBKEN PTYP PWID ECCEN TCLR TAR ECCPS

PWAITEN : PWAITEN
bits : 1 - 1 (1 bit)

PBKEN : PBKEN
bits : 2 - 2 (1 bit)

PTYP : PTYP
bits : 3 - 3 (1 bit)

PWID : PWID
bits : 4 - 5 (2 bit)

ECCEN : ECCEN
bits : 6 - 6 (1 bit)

TCLR : TCLR
bits : 9 - 12 (4 bit)

TAR : TAR
bits : 13 - 16 (4 bit)

ECCPS : ECCPS
bits : 17 - 19 (3 bit)


SR2

FIFO status and interrupt register 2
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR2 SR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRS ILS IFS IREN ILEN IFEN FEMPT

IRS : IRS
bits : 0 - 0 (1 bit)
access : read-write

ILS : ILS
bits : 1 - 1 (1 bit)
access : read-write

IFS : IFS
bits : 2 - 2 (1 bit)
access : read-write

IREN : IREN
bits : 3 - 3 (1 bit)
access : read-write

ILEN : ILEN
bits : 4 - 4 (1 bit)
access : read-write

IFEN : IFEN
bits : 5 - 5 (1 bit)
access : read-write

FEMPT : FEMPT
bits : 6 - 6 (1 bit)
access : read-only


PMEM2

Common memory space timing register 2
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMEM2 PMEM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMSETx MEMWAITx MEMHOLDx MEMHIZx

MEMSETx : MEMSETx
bits : 0 - 7 (8 bit)

MEMWAITx : MEMWAITx
bits : 8 - 15 (8 bit)

MEMHOLDx : MEMHOLDx
bits : 16 - 23 (8 bit)

MEMHIZx : MEMHIZx
bits : 24 - 31 (8 bit)


PATT2

Attribute memory space timing register 2
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATT2 PATT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATTSETx ATTWAITx ATTHOLDx ATTHIZx

ATTSETx : ATTSETx
bits : 0 - 7 (8 bit)

ATTWAITx : ATTWAITx
bits : 8 - 15 (8 bit)

ATTHOLDx : ATTHOLDx
bits : 16 - 23 (8 bit)

ATTHIZx : ATTHIZx
bits : 24 - 31 (8 bit)


ECCR2

ECC result register 2
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECCR2 ECCR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCx

ECCx : ECCx
bits : 0 - 31 (32 bit)


BCR2

SRAM/NOR-Flash chip-select control register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR2 BCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBKEN MUXEN MTYP MWID FACCEN BURSTEN WAITPOL WRAPMOD WAITCFG WREN WAITEN EXTMOD ASYNCWAIT CBURSTRW

MBKEN : MBKEN
bits : 0 - 0 (1 bit)

MUXEN : MUXEN
bits : 1 - 1 (1 bit)

MTYP : MTYP
bits : 2 - 3 (2 bit)

MWID : MWID
bits : 4 - 5 (2 bit)

FACCEN : FACCEN
bits : 6 - 6 (1 bit)

BURSTEN : BURSTEN
bits : 8 - 8 (1 bit)

WAITPOL : WAITPOL
bits : 9 - 9 (1 bit)

WRAPMOD : WRAPMOD
bits : 10 - 10 (1 bit)

WAITCFG : WAITCFG
bits : 11 - 11 (1 bit)

WREN : WREN
bits : 12 - 12 (1 bit)

WAITEN : WAITEN
bits : 13 - 13 (1 bit)

EXTMOD : EXTMOD
bits : 14 - 14 (1 bit)

ASYNCWAIT : ASYNCWAIT
bits : 15 - 15 (1 bit)

CBURSTRW : CBURSTRW
bits : 19 - 19 (1 bit)


PCR3

PC Card/NAND Flash control register 3
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR3 PCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWAITEN PBKEN PTYP PWID ECCEN TCLR TAR ECCPS

PWAITEN : PWAITEN
bits : 1 - 1 (1 bit)

PBKEN : PBKEN
bits : 2 - 2 (1 bit)

PTYP : PTYP
bits : 3 - 3 (1 bit)

PWID : PWID
bits : 4 - 5 (2 bit)

ECCEN : ECCEN
bits : 6 - 6 (1 bit)

TCLR : TCLR
bits : 9 - 12 (4 bit)

TAR : TAR
bits : 13 - 16 (4 bit)

ECCPS : ECCPS
bits : 17 - 19 (3 bit)


SR3

FIFO status and interrupt register 3
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR3 SR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRS ILS IFS IREN ILEN IFEN FEMPT

IRS : IRS
bits : 0 - 0 (1 bit)
access : read-write

ILS : ILS
bits : 1 - 1 (1 bit)
access : read-write

IFS : IFS
bits : 2 - 2 (1 bit)
access : read-write

IREN : IREN
bits : 3 - 3 (1 bit)
access : read-write

ILEN : ILEN
bits : 4 - 4 (1 bit)
access : read-write

IFEN : IFEN
bits : 5 - 5 (1 bit)
access : read-write

FEMPT : FEMPT
bits : 6 - 6 (1 bit)
access : read-only


PMEM3

Common memory space timing register 3
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMEM3 PMEM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMSETx MEMWAITx MEMHOLDx MEMHIZx

MEMSETx : MEMSETx
bits : 0 - 7 (8 bit)

MEMWAITx : MEMWAITx
bits : 8 - 15 (8 bit)

MEMHOLDx : MEMHOLDx
bits : 16 - 23 (8 bit)

MEMHIZx : MEMHIZx
bits : 24 - 31 (8 bit)


PATT3

Attribute memory space timing register 3
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATT3 PATT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATTSETx ATTWAITx ATTHOLDx ATTHIZx

ATTSETx : ATTSETx
bits : 0 - 7 (8 bit)

ATTWAITx : ATTWAITx
bits : 8 - 15 (8 bit)

ATTHOLDx : ATTHOLDx
bits : 16 - 23 (8 bit)

ATTHIZx : ATTHIZx
bits : 24 - 31 (8 bit)


ECCR3

ECC result register 3
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECCR3 ECCR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCx

ECCx : ECCx
bits : 0 - 31 (32 bit)


PCR4

PC Card/NAND Flash control register 4
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR4 PCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWAITEN PBKEN PTYP PWID ECCEN TCLR TAR ECCPS

PWAITEN : PWAITEN
bits : 1 - 1 (1 bit)

PBKEN : PBKEN
bits : 2 - 2 (1 bit)

PTYP : PTYP
bits : 3 - 3 (1 bit)

PWID : PWID
bits : 4 - 5 (2 bit)

ECCEN : ECCEN
bits : 6 - 6 (1 bit)

TCLR : TCLR
bits : 9 - 12 (4 bit)

TAR : TAR
bits : 13 - 16 (4 bit)

ECCPS : ECCPS
bits : 17 - 19 (3 bit)


SR4

FIFO status and interrupt register 4
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR4 SR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRS ILS IFS IREN ILEN IFEN FEMPT

IRS : IRS
bits : 0 - 0 (1 bit)
access : read-write

ILS : ILS
bits : 1 - 1 (1 bit)
access : read-write

IFS : IFS
bits : 2 - 2 (1 bit)
access : read-write

IREN : IREN
bits : 3 - 3 (1 bit)
access : read-write

ILEN : ILEN
bits : 4 - 4 (1 bit)
access : read-write

IFEN : IFEN
bits : 5 - 5 (1 bit)
access : read-write

FEMPT : FEMPT
bits : 6 - 6 (1 bit)
access : read-only


PMEM4

Common memory space timing register 4
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMEM4 PMEM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMSETx MEMWAITx MEMHOLDx MEMHIZx

MEMSETx : MEMSETx
bits : 0 - 7 (8 bit)

MEMWAITx : MEMWAITx
bits : 8 - 15 (8 bit)

MEMHOLDx : MEMHOLDx
bits : 16 - 23 (8 bit)

MEMHIZx : MEMHIZx
bits : 24 - 31 (8 bit)


PATT4

Attribute memory space timing register 4
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATT4 PATT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATTSETx ATTWAITx ATTHOLDx ATTHIZx

ATTSETx : ATTSETx
bits : 0 - 7 (8 bit)

ATTWAITx : ATTWAITx
bits : 8 - 15 (8 bit)

ATTHOLDx : ATTHOLDx
bits : 16 - 23 (8 bit)

ATTHIZx : ATTHIZx
bits : 24 - 31 (8 bit)


PIO4

I/O space timing register 4
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO4 PIO4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSETx IOWAITx IOHOLDx IOHIZx

IOSETx : IOSETx
bits : 0 - 7 (8 bit)

IOWAITx : IOWAITx
bits : 8 - 15 (8 bit)

IOHOLDx : IOHOLDx
bits : 16 - 23 (8 bit)

IOHIZx : IOHIZx
bits : 24 - 31 (8 bit)


BTR2

SRAM/NOR-Flash chip-select timing register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR2 BTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : ADDSET
bits : 0 - 3 (4 bit)

ADDHLD : ADDHLD
bits : 4 - 7 (4 bit)

DATAST : DATAST
bits : 8 - 15 (8 bit)

BUSTURN : BUSTURN
bits : 16 - 19 (4 bit)

CLKDIV : CLKDIV
bits : 20 - 23 (4 bit)

DATLAT : DATLAT
bits : 24 - 27 (4 bit)

ACCMOD : ACCMOD
bits : 28 - 29 (2 bit)



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