\n

MATRIX

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MCFG

SCFG[1]

SCFG[2]

TCR

SCFG[3]

EBI_CSA

USB_PUCR

SCFG[4]

SCFG[0]


MCFG

Master Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MCFG MCFG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCB0 RCB1

RCB0 : Remap Command Bit for AHB Master 0
bits : 0 - 0 (1 bit)
access : write-only

RCB1 : Remap Command Bit for AHB Master 1
bits : 1 - 1 (1 bit)
access : write-only


SCFG[1]

Slave Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[1] SCFG[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write

DEFMSTR_TYPE :
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 20 (3 bit)
access : read-write


SCFG[2]

Slave Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[2] SCFG[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write

DEFMSTR_TYPE :
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 20 (3 bit)
access : read-write


TCR

MATRIX TCM Configuration Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITCM_SIZE DTCM_SIZE

ITCM_SIZE : Size of ITCM enabled memory block
bits : 0 - 3 (4 bit)
access : read-write

DTCM_SIZE : Size of DTCM enabled memory block
bits : 4 - 7 (4 bit)
access : read-write


SCFG[3]

Slave Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[3] SCFG[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write

DEFMSTR_TYPE :
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 20 (3 bit)
access : read-write


EBI_CSA

EBI Chip Select Assignment Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EBI_CSA EBI_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EBI_CS1A EBI_CS3A EBI_CS4A EBI_CS5A EBI_DBPUC

EBI_CS1A : EBI Chip Select 1 Assignment
bits : 1 - 1 (1 bit)
access : read-write

EBI_CS3A : EBI Chip Select 3 Assignment
bits : 3 - 3 (1 bit)
access : read-write

EBI_CS4A : EBI Chip Select 4 Assignment
bits : 4 - 4 (1 bit)
access : read-write

EBI_CS5A : EBI Chip Select 5 Assignment
bits : 5 - 5 (1 bit)
access : read-write

EBI_DBPUC : EBI Data Bus Pull-Up Configuration
bits : 8 - 8 (1 bit)
access : read-write


USB_PUCR

USB Pad Pull-up Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB_PUCR USB_PUCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDP_PUP_ON

UDP_PUP_ON : UDP Pad Pull-up Enable
bits : 30 - 30 (1 bit)
access : read-write


SCFG[4]

Slave Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[4] SCFG[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write

DEFMSTR_TYPE :
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 20 (3 bit)
access : read-write


SCFG[0]

Slave Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[0] SCFG[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write

DEFMSTR_TYPE :
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 20 (3 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.