\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
CMU Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HFXOMODE : HFXO Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x00000000 : XTAL
4-25 MHz crystal oscillator.
0x00000001 : BUFEXTCLK
An AC coupled buffer is coupled in series with HFXTAL_N, suitable for external sine wave (4-25 MHz). The sine wave should have a minimum of 200 mV peak to peak.
0x00000002 : DIGEXTCLK
Digital external clock on HFXTAL_N pin. Oscillator is effectively bypassed.
End of enumeration elements list.
HFXOBOOST : HFXO Start-up Boost Current
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x00000000 : 50PCENT
50 %.
0x00000001 : 70PCENT
70 %.
0x00000002 : 80PCENT
80 %.
0x00000003 : 100PCENT
100 % (default).
End of enumeration elements list.
HFXOBUFCUR : HFXO Boost Buffer Current
bits : 5 - 6 (2 bit)
access : read-write
HFXOGLITCHDETEN : HFXO Glitch Detector Enable
bits : 7 - 7 (1 bit)
access : read-write
HFXOTIMEOUT : HFXO Timeout
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
0x00000000 : 8CYCLES
Timeout period of 8 cycles.
0x00000001 : 256CYCLES
Timeout period of 256 cycles.
0x00000002 : 1KCYCLES
Timeout period of 1024 cycles.
0x00000003 : 16KCYCLES
Timeout period of 16384 cycles.
End of enumeration elements list.
LFXOMODE : LFXO Mode
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x00000000 : XTAL
32.768 kHz crystal oscillator.
0x00000001 : BUFEXTCLK
An AC coupled buffer is coupled in series with LFXTAL_N pin, suitable for external sinus wave (32.768 kHz).
0x00000002 : DIGEXTCLK
Digital external clock on LFXTAL_N pin. Oscillator is effectively bypassed.
End of enumeration elements list.
LFXOBOOST : LFXO Start-up Boost Current
bits : 13 - 13 (1 bit)
access : read-write
HFCLKDIV : HFCLK Division
bits : 14 - 16 (3 bit)
access : read-write
LFXOBUFCUR : LFXO Boost Buffer Current
bits : 17 - 17 (1 bit)
access : read-write
LFXOTIMEOUT : LFXO Timeout
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : 8CYCLES
Timeout period of 8 cycles.
0x00000001 : 1KCYCLES
Timeout period of 1024 cycles.
0x00000002 : 16KCYCLES
Timeout period of 16384 cycles.
0x00000003 : 32KCYCLES
Timeout period of 32768 cycles.
End of enumeration elements list.
CLKOUTSEL0 : Clock Output Select 0
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0x00000000 : HFRCO
HFRCO (directly from oscillator).
0x00000001 : HFXO
HFXO (directly from oscillator).
0x00000002 : HFCLK2
HFCLK/2.
0x00000003 : HFCLK4
HFCLK/4.
0x00000004 : HFCLK8
HFCLK/8.
0x00000005 : HFCLK16
HFCLK/16.
0x00000006 : ULFRCO
ULFRCO (directly from oscillator).
0x00000007 : AUXHFRCO
AUXHFRCO (directly from oscillator).
End of enumeration elements list.
CLKOUTSEL1 : Clock Output Select 1
bits : 23 - 26 (4 bit)
access : read-write
Enumeration:
0x00000000 : LFRCO
LFRCO (directly from oscillator).
0x00000001 : LFXO
LFXO (directly from oscillator).
0x00000002 : HFCLK
HFCLK (undivided).
0x00000003 : LFXOQ
LFXO (qualified).
0x00000004 : HFXOQ
HFXO (qualified).
0x00000005 : LFRCOQ
LFRCO (qualified).
0x00000006 : HFRCOQ
HFRCO (qualified).
0x00000007 : AUXHFRCOQ
AUXHFRCO (qualified).
0x00000008 : USHFRCO
USHFRCO
End of enumeration elements list.
LFRCO Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNING : LFRCO Tuning Value
bits : 0 - 6 (7 bit)
access : read-write
AUXHFRCO Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNING : AUXHFRCO Tuning Value
bits : 0 - 7 (8 bit)
access : read-write
BAND : AUXHFRCO Band Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x00000000 : 14MHZ
14 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.
0x00000001 : 11MHZ
11 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.
0x00000002 : 7MHZ
7 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.
0x00000003 : 1MHZ
1 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.
0x00000007 : 21MHZ
21 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.
End of enumeration elements list.
Calibration Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPSEL : Calibration Up-counter Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x00000000 : HFXO
Select HFXO as up-counter.
0x00000001 : LFXO
Select LFXO as up-counter.
0x00000002 : HFRCO
Select HFRCO as up-counter.
0x00000003 : LFRCO
Select LFRCO as up-counter.
0x00000004 : AUXHFRCO
Select AUXHFRCO as up-counter.
0x00000005 : USHFRCO
Select USHFRCO as up-counter.
End of enumeration elements list.
DOWNSEL : Calibration Down-counter Select
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0x00000000 : HFCLK
Select HFCLK for down-counter.
0x00000001 : HFXO
Select HFXO for down-counter.
0x00000002 : LFXO
Select LFXO for down-counter.
0x00000003 : HFRCO
Select HFRCO for down-counter.
0x00000004 : LFRCO
Select LFRCO for down-counter.
0x00000005 : AUXHFRCO
Select AUXHFRCO for down-counter.
0x00000006 : USHFRCO
Select USHFRCO for down-counter.
End of enumeration elements list.
CONT : Continuous Calibration
bits : 6 - 6 (1 bit)
access : read-write
Calibration Counter Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALCNT : Calibration Counter
bits : 0 - 19 (20 bit)
access : read-write
Oscillator Enable/Disable Command Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
HFRCOEN : HFRCO Enable
bits : 0 - 0 (1 bit)
access : write-only
HFRCODIS : HFRCO Disable
bits : 1 - 1 (1 bit)
access : write-only
HFXOEN : HFXO Enable
bits : 2 - 2 (1 bit)
access : write-only
HFXODIS : HFXO Disable
bits : 3 - 3 (1 bit)
access : write-only
AUXHFRCOEN : AUXHFRCO Enable
bits : 4 - 4 (1 bit)
access : write-only
AUXHFRCODIS : AUXHFRCO Disable
bits : 5 - 5 (1 bit)
access : write-only
LFRCOEN : LFRCO Enable
bits : 6 - 6 (1 bit)
access : write-only
LFRCODIS : LFRCO Disable
bits : 7 - 7 (1 bit)
access : write-only
LFXOEN : LFXO Enable
bits : 8 - 8 (1 bit)
access : write-only
LFXODIS : LFXO Disable
bits : 9 - 9 (1 bit)
access : write-only
USHFRCOEN : USHFRCO Enable
bits : 10 - 10 (1 bit)
access : write-only
USHFRCODIS : USHFRCO Disable
bits : 11 - 11 (1 bit)
access : write-only
Command Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
HFCLKSEL : HFCLK Select
bits : 0 - 2 (3 bit)
access : write-only
Enumeration:
0x00000001 : HFRCO
Select HFRCO as HFCLK.
0x00000002 : HFXO
Select HFXO as HFCLK.
0x00000003 : LFRCO
Select LFRCO as HFCLK.
0x00000004 : LFXO
Select LFXO as HFCLK.
0x00000005 : USHFRCODIV2
Select USHFRCO divided by two as HFCLK.
End of enumeration elements list.
CALSTART : Calibration Start
bits : 3 - 3 (1 bit)
access : write-only
CALSTOP : Calibration Stop
bits : 4 - 4 (1 bit)
access : write-only
USBCCLKSEL : USB Core Clock Select
bits : 5 - 7 (3 bit)
access : write-only
Enumeration:
0x00000002 : LFXO
Select LFXO as HFCORECLKUSBC.
0x00000003 : LFRCO
Select LFRCO as HFCORECLKUSBC.
0x00000004 : USHFRCO
Select USHFRCO as HFCORECLKUSBC.
End of enumeration elements list.
Low Frequency Clock Select Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LFA : Clock Select for LFA
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
LFACLK is disabled
0x00000001 : LFRCO
LFRCO selected as LFACLK
0x00000002 : LFXO
LFXO selected as LFACLK
0x00000003 : HFCORECLKLEDIV2
HFCORECLKLE divided by two or four is selected as LFACLK. The division factor is determined by CMU_CTRL_HFLE and CMU_HFCORECLKDIV_HFCORECLKLEDIV.
End of enumeration elements list.
LFB : Clock Select for LFB
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
LFBCLK is disabled
0x00000001 : LFRCO
LFRCO selected as LFBCLK
0x00000002 : LFXO
LFXO selected as LFBCLK
0x00000003 : HFCORECLKLEDIV2
HFCORECLKLE divided by two or four is selected as LFACLK. The division factor is determined by CMU_CTRL_HFLE and CMU_HFCORECLKDIV_HFCORECLKLEDIV.
End of enumeration elements list.
LFC : Clock Select for LFC
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
LFCCLK clock disabled.
0x00000001 : LFRCO
LFRCO selected as LFCCLK clock
0x00000002 : LFXO
LFXO selected as LFCCLK clock
End of enumeration elements list.
LFAE : Clock Select for LFA Extended
bits : 16 - 16 (1 bit)
access : read-write
LFBE : Clock Select for LFB Extended
bits : 20 - 20 (1 bit)
access : read-write
Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HFRCOENS : HFRCO Enable Status
bits : 0 - 0 (1 bit)
access : read-only
HFRCORDY : HFRCO Ready
bits : 1 - 1 (1 bit)
access : read-only
HFXOENS : HFXO Enable Status
bits : 2 - 2 (1 bit)
access : read-only
HFXORDY : HFXO Ready
bits : 3 - 3 (1 bit)
access : read-only
AUXHFRCOENS : AUXHFRCO Enable Status
bits : 4 - 4 (1 bit)
access : read-only
AUXHFRCORDY : AUXHFRCO Ready
bits : 5 - 5 (1 bit)
access : read-only
LFRCOENS : LFRCO Enable Status
bits : 6 - 6 (1 bit)
access : read-only
LFRCORDY : LFRCO Ready
bits : 7 - 7 (1 bit)
access : read-only
LFXOENS : LFXO Enable Status
bits : 8 - 8 (1 bit)
access : read-only
LFXORDY : LFXO Ready
bits : 9 - 9 (1 bit)
access : read-only
HFRCOSEL : HFRCO Selected
bits : 10 - 10 (1 bit)
access : read-only
HFXOSEL : HFXO Selected
bits : 11 - 11 (1 bit)
access : read-only
LFRCOSEL : LFRCO Selected
bits : 12 - 12 (1 bit)
access : read-only
LFXOSEL : LFXO Selected
bits : 13 - 13 (1 bit)
access : read-only
CALBSY : Calibration Busy
bits : 14 - 14 (1 bit)
access : read-only
USBCLFXOSEL : USBC LFXO Selected
bits : 16 - 16 (1 bit)
access : read-only
USBCLFRCOSEL : USBC LFRCO Selected
bits : 17 - 17 (1 bit)
access : read-only
USBCUSHFRCOSEL : USBC USHFRCO Selected
bits : 18 - 18 (1 bit)
access : read-only
USBCHFCLKSYNC : USBC is synchronous to HFCLK
bits : 20 - 20 (1 bit)
access : read-only
USHFRCOENS : USHFRCO Enable Status
bits : 21 - 21 (1 bit)
access : read-only
USHFRCORDY : USHFRCO Ready
bits : 22 - 22 (1 bit)
access : read-only
USHFRCOSUSPEND : USHFRCO is suspended
bits : 23 - 23 (1 bit)
access : read-only
USHFRCODIV2SEL : USHFRCODIV2 Selected
bits : 26 - 26 (1 bit)
access : read-only
Interrupt Flag Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HFRCORDY : HFRCO Ready Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only
HFXORDY : HFXO Ready Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only
LFRCORDY : LFRCO Ready Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only
LFXORDY : LFXO Ready Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only
AUXHFRCORDY : AUXHFRCO Ready Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-only
CALRDY : Calibration Ready Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-only
CALOF : Calibration Overflow Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-only
USHFRCORDY : USHFRCO Ready Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-only
USBCHFOSCSEL : USBC HF-oscillator Selected Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-only
Interrupt Flag Set Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
HFRCORDY : HFRCO Ready Interrupt Flag Set
bits : 0 - 0 (1 bit)
access : write-only
HFXORDY : HFXO Ready Interrupt Flag Set
bits : 1 - 1 (1 bit)
access : write-only
LFRCORDY : LFRCO Ready Interrupt Flag Set
bits : 2 - 2 (1 bit)
access : write-only
LFXORDY : LFXO Ready Interrupt Flag Set
bits : 3 - 3 (1 bit)
access : write-only
AUXHFRCORDY : AUXHFRCO Ready Interrupt Flag Set
bits : 4 - 4 (1 bit)
access : write-only
CALRDY : Calibration Ready Interrupt Flag Set
bits : 5 - 5 (1 bit)
access : write-only
CALOF : Calibration Overflow Interrupt Flag Set
bits : 6 - 6 (1 bit)
access : write-only
USHFRCORDY : USHFRCO Ready Interrupt Flag Set
bits : 8 - 8 (1 bit)
access : write-only
USBCHFOSCSEL : USBC HF-oscillator Selected Interrupt Flag Set
bits : 9 - 9 (1 bit)
access : write-only
Interrupt Flag Clear Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
HFRCORDY : HFRCO Ready Interrupt Flag Clear
bits : 0 - 0 (1 bit)
access : write-only
HFXORDY : HFXO Ready Interrupt Flag Clear
bits : 1 - 1 (1 bit)
access : write-only
LFRCORDY : LFRCO Ready Interrupt Flag Clear
bits : 2 - 2 (1 bit)
access : write-only
LFXORDY : LFXO Ready Interrupt Flag Clear
bits : 3 - 3 (1 bit)
access : write-only
AUXHFRCORDY : AUXHFRCO Ready Interrupt Flag Clear
bits : 4 - 4 (1 bit)
access : write-only
CALRDY : Calibration Ready Interrupt Flag Clear
bits : 5 - 5 (1 bit)
access : write-only
CALOF : Calibration Overflow Interrupt Flag Clear
bits : 6 - 6 (1 bit)
access : write-only
USHFRCORDY : USHFRCO Ready Interrupt Flag Clear
bits : 8 - 8 (1 bit)
access : write-only
USBCHFOSCSEL : USBC HF-oscillator Selected Interrupt Flag Clear
bits : 9 - 9 (1 bit)
access : write-only
Interrupt Enable Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HFRCORDY : HFRCO Ready Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
HFXORDY : HFXO Ready Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
LFRCORDY : LFRCO Ready Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
LFXORDY : LFXO Ready Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
AUXHFRCORDY : AUXHFRCO Ready Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
CALRDY : Calibration Ready Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
CALOF : Calibration Overflow Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
USHFRCORDY : USHFRCO Ready Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
USBCHFOSCSEL : USBC HF-oscillator Selected Interrupt Flag Clear
bits : 9 - 9 (1 bit)
access : read-write
High Frequency Core Clock Division Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HFCORECLKDIV : HFCORECLK Divider
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x00000000 : HFCLK
HFCORECLK = HFCLK.
0x00000001 : HFCLK2
HFCORECLK = HFCLK/2.
0x00000002 : HFCLK4
HFCORECLK = HFCLK/4.
0x00000003 : HFCLK8
HFCORECLK = HFCLK/8.
0x00000004 : HFCLK16
HFCORECLK = HFCLK/16.
0x00000005 : HFCLK32
HFCORECLK = HFCLK/32.
0x00000006 : HFCLK64
HFCORECLK = HFCLK/64.
0x00000007 : HFCLK128
HFCORECLK = HFCLK/128.
0x00000008 : HFCLK256
HFCORECLK = HFCLK/256.
0x00000009 : HFCLK512
HFCORECLK = HFCLK/512.
End of enumeration elements list.
HFCORECLKLEDIV : Additional Division Factor For HFCORECLKLE
bits : 8 - 8 (1 bit)
access : read-write
High Frequency Core Clock Enable Register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : Direct Memory Access Controller Clock Enable
bits : 1 - 1 (1 bit)
access : read-write
LE : Low Energy Peripheral Interface Clock Enable
bits : 2 - 2 (1 bit)
access : read-write
USBC : Universal Serial Bus Interface Core Clock Enable
bits : 3 - 3 (1 bit)
access : read-write
USB : Universal Serial Bus Interface Clock Enable
bits : 4 - 4 (1 bit)
access : read-write
High Frequency Peripheral Clock Enable Register 0
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER0 : Timer 0 Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
TIMER1 : Timer 1 Clock Enable
bits : 1 - 1 (1 bit)
access : read-write
TIMER2 : Timer 2 Clock Enable
bits : 2 - 2 (1 bit)
access : read-write
USART0 : Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable
bits : 3 - 3 (1 bit)
access : read-write
USART1 : Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable
bits : 4 - 4 (1 bit)
access : read-write
ACMP0 : Analog Comparator 0 Clock Enable
bits : 5 - 5 (1 bit)
access : read-write
PRS : Peripheral Reflex System Clock Enable
bits : 6 - 6 (1 bit)
access : read-write
GPIO : General purpose Input/Output Clock Enable
bits : 8 - 8 (1 bit)
access : read-write
VCMP : Voltage Comparator Clock Enable
bits : 9 - 9 (1 bit)
access : read-write
I2C0 : I2C 0 Clock Enable
bits : 11 - 11 (1 bit)
access : read-write
Synchronization Busy Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LFACLKEN0 : Low Frequency A Clock Enable 0 Busy
bits : 0 - 0 (1 bit)
access : read-only
LFAPRESC0 : Low Frequency A Prescaler 0 Busy
bits : 2 - 2 (1 bit)
access : read-only
LFBCLKEN0 : Low Frequency B Clock Enable 0 Busy
bits : 4 - 4 (1 bit)
access : read-only
LFBPRESC0 : Low Frequency B Prescaler 0 Busy
bits : 6 - 6 (1 bit)
access : read-only
LFCCLKEN0 : Low Frequency C Clock Enable 0 Busy
bits : 8 - 8 (1 bit)
access : read-only
Freeze Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGFREEZE : Register Update Freeze
bits : 0 - 0 (1 bit)
access : read-write
Low Frequency A Clock Enable Register 0 (Async Reg)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC : Real-Time Counter Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Low Frequency B Clock Enable Register 0 (Async Reg)
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEUART0 : Low Energy UART 0 Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Low Frequency C Clock Enable Register 0 (Async Reg)
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBLE : Universal Serial Bus Low Energy Clock Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Low Frequency A Prescaler Register 0 (Async Reg)
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC : Real-Time Counter Prescaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x00000000 : DIV1
LFACLKRTC = LFACLK
0x00000001 : DIV2
LFACLKRTC = LFACLK/2
0x00000002 : DIV4
LFACLKRTC = LFACLK/4
0x00000003 : DIV8
LFACLKRTC = LFACLK/8
0x00000004 : DIV16
LFACLKRTC = LFACLK/16
0x00000005 : DIV32
LFACLKRTC = LFACLK/32
0x00000006 : DIV64
LFACLKRTC = LFACLK/64
0x00000007 : DIV128
LFACLKRTC = LFACLK/128
0x00000008 : DIV256
LFACLKRTC = LFACLK/256
0x00000009 : DIV512
LFACLKRTC = LFACLK/512
0x0000000A : DIV1024
LFACLKRTC = LFACLK/1024
0x0000000B : DIV2048
LFACLKRTC = LFACLK/2048
0x0000000C : DIV4096
LFACLKRTC = LFACLK/4096
0x0000000D : DIV8192
LFACLKRTC = LFACLK/8192
0x0000000E : DIV16384
LFACLKRTC = LFACLK/16384
0x0000000F : DIV32768
LFACLKRTC = LFACLK/32768
End of enumeration elements list.
Low Frequency B Prescaler Register 0 (Async Reg)
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEUART0 : Low Energy UART 0 Prescaler
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x00000000 : DIV1
LFBCLKLEUART0 = LFBCLK
0x00000001 : DIV2
LFBCLKLEUART0 = LFBCLK/2
0x00000002 : DIV4
LFBCLKLEUART0 = LFBCLK/4
0x00000003 : DIV8
LFBCLKLEUART0 = LFBCLK/8
End of enumeration elements list.
PCNT Control Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCNT0CLKEN : PCNT0 Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
PCNT0CLKSEL : PCNT0 Clock Select
bits : 1 - 1 (1 bit)
access : read-write
High Frequency Peripheral Clock Division Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HFPERCLKDIV : HFPERCLK Divider
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x00000000 : HFCLK
HFPERCLK = HFCLK.
0x00000001 : HFCLK2
HFPERCLK = HFCLK/2.
0x00000002 : HFCLK4
HFPERCLK = HFCLK/4.
0x00000003 : HFCLK8
HFPERCLK = HFCLK/8.
0x00000004 : HFCLK16
HFPERCLK = HFCLK/16.
0x00000005 : HFCLK32
HFPERCLK = HFCLK/32.
0x00000006 : HFCLK64
HFPERCLK = HFCLK/64.
0x00000007 : HFCLK128
HFPERCLK = HFCLK/128.
0x00000008 : HFCLK256
HFPERCLK = HFCLK/256.
0x00000009 : HFCLK512
HFPERCLK = HFCLK/512.
End of enumeration elements list.
HFPERCLKEN : HFPERCLK Enable
bits : 8 - 8 (1 bit)
access : read-write
I/O Routing Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKOUT0PEN : CLKOUT0 Pin Enable
bits : 0 - 0 (1 bit)
access : read-write
CLKOUT1PEN : CLKOUT1 Pin Enable
bits : 1 - 1 (1 bit)
access : read-write
LOCATION : I/O Location
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
End of enumeration elements list.
Configuration Lock Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKKEY : Configuration Lock Key
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0x00000000 : UNLOCKED
0x00000001 : LOCKED
End of enumeration elements list.
HFRCO Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNING : HFRCO Tuning Value
bits : 0 - 7 (8 bit)
access : read-write
BAND : HFRCO Band Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x00000000 : 1MHZ
1 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.
0x00000001 : 7MHZ
7 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.
0x00000002 : 11MHZ
11 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.
0x00000003 : 14MHZ
14 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.
0x00000004 : 21MHZ
21 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.
End of enumeration elements list.
SUDELAY : HFRCO Start-up Delay
bits : 12 - 16 (5 bit)
access : read-write
USB Clock Recovery Control
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Clock Recovery Enable
bits : 0 - 0 (1 bit)
access : read-write
LSMODE : Low Speed Clock Recovery Mode
bits : 1 - 1 (1 bit)
access : read-write
USHFRCO Control
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNING : USHFRCO frequency adjust
bits : 0 - 6 (7 bit)
access : read-write
DITHEN : USHFRCO dither enable
bits : 8 - 8 (1 bit)
access : read-write
SUSPEND : USHFRCO suspend
bits : 9 - 9 (1 bit)
access : read-write
TIMEOUT : USHFRCO Timeout
bits : 12 - 19 (8 bit)
access : read-write
USHFRCO Frequency Tune
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FINETUNING : Oscillator fine frequency adjust
bits : 0 - 5 (6 bit)
access : read-write
USHFRCO Configuration
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BAND : USHFRCO Band Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x00000001 : 48MHZ
48 MHz band. NOTE: Also set the TUNING and FINETUNING value when changing band.
0x00000003 : 24MHZ
24 MHz band. NOTE: Also set the TUNING and FINETUNING value when changing band.
End of enumeration elements list.
USHFRCODIV2DIS : USHFRCO divider for HFCLK disable
bits : 4 - 4 (1 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.