\n
address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected
DMA Status Registers
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Enable Status
bits : 0 - 0 (1 bit)
access : read-only
STATE : Control Current State
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
0x00000000 : IDLE
Idle
0x00000001 : RDCHCTRLDATA
Reading channel controller data
0x00000002 : RDSRCENDPTR
Reading source data end pointer
0x00000003 : RDDSTENDPTR
Reading destination data end pointer
0x00000004 : RDSRCDATA
Reading source data
0x00000005 : WRDSTDATA
Writing destination data
0x00000006 : WAITREQCLR
Waiting for DMA request to clear
0x00000007 : WRCHCTRLDATA
Writing channel controller data
0x00000008 : STALLED
Stalled
0x00000009 : DONE
Done
0x0000000A : PERSCATTRANS
Peripheral scatter-gather transition
End of enumeration elements list.
CHNUM : Channel Number
bits : 16 - 20 (5 bit)
access : read-only
Channel Wait on Request Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0WAITSTATUS : Channel 0 Wait on Request Status
bits : 0 - 0 (1 bit)
access : read-only
CH1WAITSTATUS : Channel 1 Wait on Request Status
bits : 1 - 1 (1 bit)
access : read-only
CH2WAITSTATUS : Channel 2 Wait on Request Status
bits : 2 - 2 (1 bit)
access : read-only
CH3WAITSTATUS : Channel 3 Wait on Request Status
bits : 3 - 3 (1 bit)
access : read-only
CH4WAITSTATUS : Channel 4 Wait on Request Status
bits : 4 - 4 (1 bit)
access : read-only
CH5WAITSTATUS : Channel 5 Wait on Request Status
bits : 5 - 5 (1 bit)
access : read-only
Interrupt Flag Register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0DONE : DMA Channel 0 Complete Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only
CH1DONE : DMA Channel 1 Complete Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only
CH2DONE : DMA Channel 2 Complete Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only
CH3DONE : DMA Channel 3 Complete Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only
CH4DONE : DMA Channel 4 Complete Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-only
CH5DONE : DMA Channel 5 Complete Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-only
ERR : DMA Error Interrupt Flag
bits : 31 - 31 (1 bit)
access : read-only
Interrupt Flag Set Register
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0DONE : DMA Channel 0 Complete Interrupt Flag Set
bits : 0 - 0 (1 bit)
access : write-only
CH1DONE : DMA Channel 1 Complete Interrupt Flag Set
bits : 1 - 1 (1 bit)
access : write-only
CH2DONE : DMA Channel 2 Complete Interrupt Flag Set
bits : 2 - 2 (1 bit)
access : write-only
CH3DONE : DMA Channel 3 Complete Interrupt Flag Set
bits : 3 - 3 (1 bit)
access : write-only
CH4DONE : DMA Channel 4 Complete Interrupt Flag Set
bits : 4 - 4 (1 bit)
access : write-only
CH5DONE : DMA Channel 5 Complete Interrupt Flag Set
bits : 5 - 5 (1 bit)
access : write-only
ERR : DMA Error Interrupt Flag Set
bits : 31 - 31 (1 bit)
access : write-only
Interrupt Flag Clear Register
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0DONE : DMA Channel 0 Complete Interrupt Flag Clear
bits : 0 - 0 (1 bit)
access : write-only
CH1DONE : DMA Channel 1 Complete Interrupt Flag Clear
bits : 1 - 1 (1 bit)
access : write-only
CH2DONE : DMA Channel 2 Complete Interrupt Flag Clear
bits : 2 - 2 (1 bit)
access : write-only
CH3DONE : DMA Channel 3 Complete Interrupt Flag Clear
bits : 3 - 3 (1 bit)
access : write-only
CH4DONE : DMA Channel 4 Complete Interrupt Flag Clear
bits : 4 - 4 (1 bit)
access : write-only
CH5DONE : DMA Channel 5 Complete Interrupt Flag Clear
bits : 5 - 5 (1 bit)
access : write-only
ERR : DMA Error Interrupt Flag Clear
bits : 31 - 31 (1 bit)
access : write-only
Interrupt Enable register
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0DONE : DMA Channel 0 Complete Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
CH1DONE : DMA Channel 1 Complete Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
CH2DONE : DMA Channel 2 Complete Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
CH3DONE : DMA Channel 3 Complete Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
CH4DONE : DMA Channel 4 Complete Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
CH5DONE : DMA Channel 5 Complete Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
ERR : DMA Error Interrupt Flag Enable
bits : 31 - 31 (1 bit)
access : read-write
Channel Control Register
address_offset : 0x1100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write
SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000008 : ADC0
Analog to Digital Converter 0
0x0000000C : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x0000000D : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x00000010 : LEUART0
Low Energy UART 0
0x00000014 : I2C0
I2C 0
0x00000018 : TIMER0
Timer 0
0x00000019 : TIMER1
Timer 1
0x0000001A : TIMER2
Timer 2
0x00000030 : MSC
End of enumeration elements list.
Channel Control Register
address_offset : 0x1104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write
SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000008 : ADC0
Analog to Digital Converter 0
0x0000000C : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x0000000D : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x00000010 : LEUART0
Low Energy UART 0
0x00000014 : I2C0
I2C 0
0x00000018 : TIMER0
Timer 0
0x00000019 : TIMER1
Timer 1
0x0000001A : TIMER2
Timer 2
0x00000030 : MSC
End of enumeration elements list.
Channel Control Register
address_offset : 0x1108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write
SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000008 : ADC0
Analog to Digital Converter 0
0x0000000C : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x0000000D : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x00000010 : LEUART0
Low Energy UART 0
0x00000014 : I2C0
I2C 0
0x00000018 : TIMER0
Timer 0
0x00000019 : TIMER1
Timer 1
0x0000001A : TIMER2
Timer 2
0x00000030 : MSC
End of enumeration elements list.
Channel Control Register
address_offset : 0x110C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write
SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000008 : ADC0
Analog to Digital Converter 0
0x0000000C : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x0000000D : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x00000010 : LEUART0
Low Energy UART 0
0x00000014 : I2C0
I2C 0
0x00000018 : TIMER0
Timer 0
0x00000019 : TIMER1
Timer 1
0x0000001A : TIMER2
Timer 2
0x00000030 : MSC
End of enumeration elements list.
Channel Control Register
address_offset : 0x1110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write
SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000008 : ADC0
Analog to Digital Converter 0
0x0000000C : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x0000000D : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x00000010 : LEUART0
Low Energy UART 0
0x00000014 : I2C0
I2C 0
0x00000018 : TIMER0
Timer 0
0x00000019 : TIMER1
Timer 1
0x0000001A : TIMER2
Timer 2
0x00000030 : MSC
End of enumeration elements list.
Channel Control Register
address_offset : 0x1114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write
SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000008 : ADC0
Analog to Digital Converter 0
0x0000000C : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x0000000D : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x00000010 : LEUART0
Low Energy UART 0
0x00000014 : I2C0
I2C 0
0x00000018 : TIMER0
Timer 0
0x00000019 : TIMER1
Timer 1
0x0000001A : TIMER2
Timer 2
0x00000030 : MSC
End of enumeration elements list.
Channel Software Request Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0SWREQ : Channel 0 Software Request
bits : 0 - 0 (1 bit)
access : write-only
CH1SWREQ : Channel 1 Software Request
bits : 1 - 1 (1 bit)
access : write-only
CH2SWREQ : Channel 2 Software Request
bits : 2 - 2 (1 bit)
access : write-only
CH3SWREQ : Channel 3 Software Request
bits : 3 - 3 (1 bit)
access : write-only
CH4SWREQ : Channel 4 Software Request
bits : 4 - 4 (1 bit)
access : write-only
CH5SWREQ : Channel 5 Software Request
bits : 5 - 5 (1 bit)
access : write-only
Channel Useburst Set Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0USEBURSTS : Channel 0 Useburst Set
bits : 0 - 0 (1 bit)
access : read-write
CH1USEBURSTS : Channel 1 Useburst Set
bits : 1 - 1 (1 bit)
access : read-write
CH2USEBURSTS : Channel 2 Useburst Set
bits : 2 - 2 (1 bit)
access : read-write
CH3USEBURSTS : Channel 3 Useburst Set
bits : 3 - 3 (1 bit)
access : read-write
CH4USEBURSTS : Channel 4 Useburst Set
bits : 4 - 4 (1 bit)
access : read-write
CH5USEBURSTS : Channel 5 Useburst Set
bits : 5 - 5 (1 bit)
access : read-write
Channel Useburst Clear Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0USEBURSTC : Channel 0 Useburst Clear
bits : 0 - 0 (1 bit)
access : write-only
CH1USEBURSTC : Channel 1 Useburst Clear
bits : 1 - 1 (1 bit)
access : write-only
CH2USEBURSTC : Channel 2 Useburst Clear
bits : 2 - 2 (1 bit)
access : write-only
CH3USEBURSTC : Channel 3 Useburst Clear
bits : 3 - 3 (1 bit)
access : write-only
CH4USEBURSTC : Channel 4 Useburst Clear
bits : 4 - 4 (1 bit)
access : write-only
CH5USEBURSTC : Channel 5 Useburst Clear
bits : 5 - 5 (1 bit)
access : write-only
Channel Request Mask Set Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0REQMASKS : Channel 0 Request Mask Set
bits : 0 - 0 (1 bit)
access : write-only
CH1REQMASKS : Channel 1 Request Mask Set
bits : 1 - 1 (1 bit)
access : write-only
CH2REQMASKS : Channel 2 Request Mask Set
bits : 2 - 2 (1 bit)
access : write-only
CH3REQMASKS : Channel 3 Request Mask Set
bits : 3 - 3 (1 bit)
access : write-only
CH4REQMASKS : Channel 4 Request Mask Set
bits : 4 - 4 (1 bit)
access : write-only
CH5REQMASKS : Channel 5 Request Mask Set
bits : 5 - 5 (1 bit)
access : write-only
Channel Request Mask Clear Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0REQMASKC : Channel 0 Request Mask Clear
bits : 0 - 0 (1 bit)
access : write-only
CH1REQMASKC : Channel 1 Request Mask Clear
bits : 1 - 1 (1 bit)
access : write-only
CH2REQMASKC : Channel 2 Request Mask Clear
bits : 2 - 2 (1 bit)
access : write-only
CH3REQMASKC : Channel 3 Request Mask Clear
bits : 3 - 3 (1 bit)
access : write-only
CH4REQMASKC : Channel 4 Request Mask Clear
bits : 4 - 4 (1 bit)
access : write-only
CH5REQMASKC : Channel 5 Request Mask Clear
bits : 5 - 5 (1 bit)
access : write-only
Channel Enable Set Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0ENS : Channel 0 Enable Set
bits : 0 - 0 (1 bit)
access : write-only
CH1ENS : Channel 1 Enable Set
bits : 1 - 1 (1 bit)
access : write-only
CH2ENS : Channel 2 Enable Set
bits : 2 - 2 (1 bit)
access : write-only
CH3ENS : Channel 3 Enable Set
bits : 3 - 3 (1 bit)
access : write-only
CH4ENS : Channel 4 Enable Set
bits : 4 - 4 (1 bit)
access : write-only
CH5ENS : Channel 5 Enable Set
bits : 5 - 5 (1 bit)
access : write-only
Channel Enable Clear Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0ENC : Channel 0 Enable Clear
bits : 0 - 0 (1 bit)
access : write-only
CH1ENC : Channel 1 Enable Clear
bits : 1 - 1 (1 bit)
access : write-only
CH2ENC : Channel 2 Enable Clear
bits : 2 - 2 (1 bit)
access : write-only
CH3ENC : Channel 3 Enable Clear
bits : 3 - 3 (1 bit)
access : write-only
CH4ENC : Channel 4 Enable Clear
bits : 4 - 4 (1 bit)
access : write-only
CH5ENC : Channel 5 Enable Clear
bits : 5 - 5 (1 bit)
access : write-only
Channel Alternate Set Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0ALTS : Channel 0 Alternate Structure Set
bits : 0 - 0 (1 bit)
access : write-only
CH1ALTS : Channel 1 Alternate Structure Set
bits : 1 - 1 (1 bit)
access : write-only
CH2ALTS : Channel 2 Alternate Structure Set
bits : 2 - 2 (1 bit)
access : write-only
CH3ALTS : Channel 3 Alternate Structure Set
bits : 3 - 3 (1 bit)
access : write-only
CH4ALTS : Channel 4 Alternate Structure Set
bits : 4 - 4 (1 bit)
access : write-only
CH5ALTS : Channel 5 Alternate Structure Set
bits : 5 - 5 (1 bit)
access : write-only
Channel Alternate Clear Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0ALTC : Channel 0 Alternate Clear
bits : 0 - 0 (1 bit)
access : write-only
CH1ALTC : Channel 1 Alternate Clear
bits : 1 - 1 (1 bit)
access : write-only
CH2ALTC : Channel 2 Alternate Clear
bits : 2 - 2 (1 bit)
access : write-only
CH3ALTC : Channel 3 Alternate Clear
bits : 3 - 3 (1 bit)
access : write-only
CH4ALTC : Channel 4 Alternate Clear
bits : 4 - 4 (1 bit)
access : write-only
CH5ALTC : Channel 5 Alternate Clear
bits : 5 - 5 (1 bit)
access : write-only
Channel Priority Set Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0PRIS : Channel 0 High Priority Set
bits : 0 - 0 (1 bit)
access : write-only
CH1PRIS : Channel 1 High Priority Set
bits : 1 - 1 (1 bit)
access : write-only
CH2PRIS : Channel 2 High Priority Set
bits : 2 - 2 (1 bit)
access : write-only
CH3PRIS : Channel 3 High Priority Set
bits : 3 - 3 (1 bit)
access : write-only
CH4PRIS : Channel 4 High Priority Set
bits : 4 - 4 (1 bit)
access : write-only
CH5PRIS : Channel 5 High Priority Set
bits : 5 - 5 (1 bit)
access : write-only
Channel Priority Clear Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0PRIC : Channel 0 High Priority Clear
bits : 0 - 0 (1 bit)
access : write-only
CH1PRIC : Channel 1 High Priority Clear
bits : 1 - 1 (1 bit)
access : write-only
CH2PRIC : Channel 2 High Priority Clear
bits : 2 - 2 (1 bit)
access : write-only
CH3PRIC : Channel 3 High Priority Clear
bits : 3 - 3 (1 bit)
access : write-only
CH4PRIC : Channel 4 High Priority Clear
bits : 4 - 4 (1 bit)
access : write-only
CH5PRIC : Channel 5 High Priority Clear
bits : 5 - 5 (1 bit)
access : write-only
DMA Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EN : Enable DMA
bits : 0 - 0 (1 bit)
access : write-only
CHPROT : Channel Protection Control
bits : 5 - 5 (1 bit)
access : write-only
Bus Error Clear Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERRORC : Bus Error Clear
bits : 0 - 0 (1 bit)
access : read-write
Channel Control Data Base Pointer Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRLBASE : Channel Control Data Base Pointer
bits : 0 - 31 (32 bit)
access : read-write
Channel Alternate Control Data Base Pointer Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ALTCTRLBASE : Channel Alternate Control Data Base Pointer
bits : 0 - 31 (32 bit)
access : read-only
Channel Request Status
address_offset : 0xE10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0REQSTATUS : Channel 0 Request Status
bits : 0 - 0 (1 bit)
access : read-only
CH1REQSTATUS : Channel 1 Request Status
bits : 1 - 1 (1 bit)
access : read-only
CH2REQSTATUS : Channel 2 Request Status
bits : 2 - 2 (1 bit)
access : read-only
CH3REQSTATUS : Channel 3 Request Status
bits : 3 - 3 (1 bit)
access : read-only
CH4REQSTATUS : Channel 4 Request Status
bits : 4 - 4 (1 bit)
access : read-only
CH5REQSTATUS : Channel 5 Request Status
bits : 5 - 5 (1 bit)
access : read-only
Channel Single Request Status
address_offset : 0xE18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0SREQSTATUS : Channel 0 Single Request Status
bits : 0 - 0 (1 bit)
access : read-only
CH1SREQSTATUS : Channel 1 Single Request Status
bits : 1 - 1 (1 bit)
access : read-only
CH2SREQSTATUS : Channel 2 Single Request Status
bits : 2 - 2 (1 bit)
access : read-only
CH3SREQSTATUS : Channel 3 Single Request Status
bits : 3 - 3 (1 bit)
access : read-only
CH4SREQSTATUS : Channel 4 Single Request Status
bits : 4 - 4 (1 bit)
access : read-only
CH5SREQSTATUS : Channel 5 Single Request Status
bits : 5 - 5 (1 bit)
access : read-only
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