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HSMCI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

ARGR

FIFO[93]

FIFO[6]

FIFO[94]

FIFO[95]

FIFO[96]

FIFO[97]

FIFO[98]

FIFO[99]

FIFO[100]

FIFO[101]

FIFO[102]

FIFO[103]

FIFO[7]

FIFO[104]

FIFO[105]

FIFO[106]

FIFO[107]

FIFO[108]

FIFO[109]

FIFO[110]

CMDR

FIFO[111]

FIFO[112]

FIFO[8]

FIFO[113]

FIFO[114]

FIFO[115]

FIFO[116]

FIFO[117]

FIFO[118]

FIFO[119]

FIFO[120]

FIFO[121]

FIFO[9]

FIFO[122]

FIFO[123]

FIFO[124]

FIFO[125]

FIFO[126]

BLKR

FIFO[127]

FIFO[128]

FIFO[129]

FIFO[130]

FIFO[10]

FIFO[131]

FIFO[132]

FIFO[133]

FIFO[134]

FIFO[135]

FIFO[136]

FIFO[137]

FIFO[138]

FIFO[11]

FIFO[139]

FIFO[140]

FIFO[141]

FIFO[142]

CSTOR

FIFO[143]

FIFO[144]

FIFO[145]

FIFO[146]

FIFO[12]

FIFO[147]

FIFO[148]

FIFO[149]

FIFO[150]

FIFO[151]

FIFO[152]

FIFO[153]

FIFO[154]

FIFO[13]

FIFO[155]

FIFO[156]

FIFO[157]

FIFO[158]

FIFO[159]

FIFO[160]

FIFO[161]

FIFO[162]

FIFO[14]

FIFO[163]

FIFO[164]

FIFO[165]

FIFO[166]

FIFO[167]

FIFO[168]

FIFO[169]

FIFO[170]

FIFO[15]

FIFO[171]

FIFO[172]

FIFO[173]

FIFO[174]

FIFO[175]

FIFO[176]

FIFO[177]

FIFO[178]

FIFO[16]

FIFO[179]

FIFO[180]

FIFO[181]

FIFO[182]

FIFO[183]

FIFO[184]

FIFO[185]

FIFO[17]

FIFO[186]

FIFO[187]

FIFO[188]

FIFO[189]

FIFO[190]

FIFO[191]

FIFO[192]

FIFO[193]

FIFO[18]

FIFO[194]

FIFO[195]

FIFO[196]

FIFO[197]

FIFO[198]

FIFO[199]

FIFO[200]

FIFO[19]

FIFO[201]

FIFO[202]

FIFO[203]

FIFO[204]

FIFO[205]

FIFO[206]

FIFO[207]

FIFO[20]

FIFO[208]

FIFO[209]

RDR

FIFO[210]

FIFO[211]

FIFO[212]

FIFO[213]

FIFO[214]

FIFO[21]

FIFO[215]

FIFO[216]

FIFO[217]

FIFO[218]

FIFO[219]

FIFO[220]

FIFO[221]

FIFO[22]

TDR

FIFO[222]

FIFO[223]

FIFO[224]

FIFO[225]

FIFO[226]

FIFO[227]

FIFO[228]

FIFO[23]

FIFO[229]

FIFO[230]

FIFO[231]

FIFO[232]

FIFO[233]

FIFO[234]

FIFO[24]

FIFO[235]

FIFO[236]

FIFO[237]

FIFO[238]

FIFO[239]

FIFO[240]

FIFO[241]

FIFO[25]

FIFO[242]

FIFO[243]

FIFO[244]

FIFO[245]

FIFO[246]

FIFO[247]

FIFO[248]

FIFO[26]

FIFO[249]

FIFO[250]

FIFO[251]

FIFO[252]

FIFO[253]

FIFO[254]

FIFO[27]

MR

RSPR[0]

SR

FIFO[0]

FIFO[255]

FIFO[28]

IER

FIFO[29]

FIFO[30]

IDR

FIFO[31]

IMR

FIFO[32]

FIFO[33]

DMA

FIFO[34]

FIFO[35]

CFG

FIFO[36]

FIFO[37]

FIFO[38]

FIFO[39]

FIFO[1]

FIFO[40]

FIFO[41]

RSPR[1]

FIFO[42]

FIFO[43]

FIFO[44]

FIFO[45]

FIFO[46]

FIFO[47]

FIFO[48]

FIFO[49]

FIFO[50]

FIFO[51]

DTOR

FIFO[2]

FIFO[52]

FIFO[53]

FIFO[54]

FIFO[55]

RSPR[2]

FIFO[56]

FIFO[57]

FIFO[58]

FIFO[59]

FIFO[60]

FIFO[61]

FIFO[62]

FIFO[3]

FIFO[63]

FIFO[64]

FIFO[65]

FIFO[66]

FIFO[67]

FIFO[68]

FIFO[69]

FIFO[70]

RSPR[3]

FIFO[71]

FIFO[72]

SDCR

FIFO[73]

FIFO[4]

FIFO[74]

FIFO[75]

FIFO[76]

FIFO[77]

FIFO[78]

FIFO[79]

FIFO[80]

FIFO[81]

FIFO[82]

FIFO[83]

FIFO[5]

FIFO[84]

WPMR

FIFO[85]

WPSR

FIFO[86]

FIFO[87]

FIFO[88]

FIFO[89]

FIFO[90]

FIFO[91]

FIFO[92]


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCIEN MCIDIS PWSEN PWSDIS SWRST

MCIEN : Multi-Media Interface Enable
bits : 0 - 0 (1 bit)
access : write-only

MCIDIS : Multi-Media Interface Disable
bits : 1 - 1 (1 bit)
access : write-only

PWSEN : Power Save Mode Enable
bits : 2 - 2 (1 bit)
access : write-only

PWSDIS : Power Save Mode Disable
bits : 3 - 3 (1 bit)
access : write-only

SWRST : Software Reset
bits : 7 - 7 (1 bit)
access : write-only


ARGR

Argument Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARGR ARGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARG

ARG : Command Argument
bits : 0 - 31 (32 bit)
access : read-write


FIFO[93]

FIFO Memory Aperture0
address_offset : 0x1024C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[93] FIFO[93] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[6]

FIFO Memory Aperture0
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[6] FIFO[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[94]

FIFO Memory Aperture0
address_offset : 0x105C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[94] FIFO[94] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[95]

FIFO Memory Aperture0
address_offset : 0x10940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[95] FIFO[95] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[96]

FIFO Memory Aperture0
address_offset : 0x10CC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[96] FIFO[96] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[97]

FIFO Memory Aperture0
address_offset : 0x11044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[97] FIFO[97] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[98]

FIFO Memory Aperture0
address_offset : 0x113CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[98] FIFO[98] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[99]

FIFO Memory Aperture0
address_offset : 0x11758 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[99] FIFO[99] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[100]

FIFO Memory Aperture0
address_offset : 0x11AE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[100] FIFO[100] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[101]

FIFO Memory Aperture0
address_offset : 0x11E7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[101] FIFO[101] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[102]

FIFO Memory Aperture0
address_offset : 0x12214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[102] FIFO[102] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[103]

FIFO Memory Aperture0
address_offset : 0x125B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[103] FIFO[103] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[7]

FIFO Memory Aperture0
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[7] FIFO[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[104]

FIFO Memory Aperture0
address_offset : 0x12950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[104] FIFO[104] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[105]

FIFO Memory Aperture0
address_offset : 0x12CF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[105] FIFO[105] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[106]

FIFO Memory Aperture0
address_offset : 0x1309C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[106] FIFO[106] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[107]

FIFO Memory Aperture0
address_offset : 0x13448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[107] FIFO[107] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[108]

FIFO Memory Aperture0
address_offset : 0x137F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[108] FIFO[108] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[109]

FIFO Memory Aperture0
address_offset : 0x13BAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[109] FIFO[109] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[110]

FIFO Memory Aperture0
address_offset : 0x13F64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[110] FIFO[110] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


CMDR

Command Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMDR CMDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDNB RSPTYP SPCMD OPDCMD MAXLAT TRCMD TRDIR TRTYP IOSPCMD ATACS BOOT_ACK

CMDNB : Command Number
bits : 0 - 5 (6 bit)
access : write-only

RSPTYP : Response Type
bits : 6 - 7 (2 bit)
access : write-only

Enumeration:

0x0 : NORESP

No response.

0x1 : 48_BIT

48-bit response.

0x2 : 136_BIT

136-bit response.

0x3 : R1B

R1b response type

End of enumeration elements list.

SPCMD : Special Command
bits : 8 - 10 (3 bit)
access : write-only

Enumeration:

0x0 : STD

Not a special CMD.

0x1 : INIT

Initialization CMD: 74 clock cycles for initialization sequence.

0x2 : SYNC

Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command.

0x3 : CE_ATA

CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line.

0x4 : IT_CMD

Interrupt command: Corresponds to the Interrupt Mode (CMD40).

0x5 : IT_RESP

Interrupt response: Corresponds to the Interrupt Mode (CMD40).

0x6 : BOR

Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly.

0x7 : EBO

End Boot Operation. This command allows the host processor to terminate the boot operation mode.

End of enumeration elements list.

OPDCMD : Open Drain Command
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0 : PUSHPULL

Push pull command.

1 : OPENDRAIN

Open drain command.

End of enumeration elements list.

MAXLAT : Max Latency for Command to Response
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0 : 5

5-cycle max latency.

1 : 64

64-cycle max latency.

End of enumeration elements list.

TRCMD : Transfer Command
bits : 16 - 17 (2 bit)
access : write-only

Enumeration:

0x0 : NO_DATA

No data transfer

0x1 : START_DATA

Start data transfer

0x2 : STOP_DATA

Stop data transfer

End of enumeration elements list.

TRDIR : Transfer Direction
bits : 18 - 18 (1 bit)
access : write-only

Enumeration:

0 : WRITE

Write.

1 : READ

Read.

End of enumeration elements list.

TRTYP : Transfer Type
bits : 19 - 21 (3 bit)
access : write-only

Enumeration:

0x0 : SINGLE

MMC/SD Card Single Block

0x1 : MULTIPLE

MMC/SD Card Multiple Block

0x2 : STREAM

MMC Stream

0x4 : BYTE

SDIO Byte

0x5 : BLOCK

SDIO Block

End of enumeration elements list.

IOSPCMD : SDIO Special Command
bits : 24 - 25 (2 bit)
access : write-only

Enumeration:

0x0 : STD

Not an SDIO Special Command

0x1 : SUSPEND

SDIO Suspend Command

0x2 : RESUME

SDIO Resume Command

End of enumeration elements list.

ATACS : ATA with Command Completion Signal
bits : 26 - 26 (1 bit)
access : write-only

Enumeration:

0 : NORMAL

Normal operation mode.

1 : COMPLETION

This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR).

End of enumeration elements list.

BOOT_ACK : Boot Operation Acknowledge.
bits : 27 - 27 (1 bit)
access : write-only


FIFO[111]

FIFO Memory Aperture0
address_offset : 0x14320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[111] FIFO[111] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[112]

FIFO Memory Aperture0
address_offset : 0x146E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[112] FIFO[112] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[8]

FIFO Memory Aperture0
address_offset : 0x1490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[8] FIFO[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[113]

FIFO Memory Aperture0
address_offset : 0x14AA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[113] FIFO[113] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[114]

FIFO Memory Aperture0
address_offset : 0x14E6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[114] FIFO[114] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[115]

FIFO Memory Aperture0
address_offset : 0x15238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[115] FIFO[115] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[116]

FIFO Memory Aperture0
address_offset : 0x15608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[116] FIFO[116] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[117]

FIFO Memory Aperture0
address_offset : 0x159DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[117] FIFO[117] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[118]

FIFO Memory Aperture0
address_offset : 0x15DB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[118] FIFO[118] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[119]

FIFO Memory Aperture0
address_offset : 0x16190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[119] FIFO[119] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[120]

FIFO Memory Aperture0
address_offset : 0x16570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[120] FIFO[120] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[121]

FIFO Memory Aperture0
address_offset : 0x16954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[121] FIFO[121] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[9]

FIFO Memory Aperture0
address_offset : 0x16B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[9] FIFO[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[122]

FIFO Memory Aperture0
address_offset : 0x16D3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[122] FIFO[122] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[123]

FIFO Memory Aperture0
address_offset : 0x17128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[123] FIFO[123] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[124]

FIFO Memory Aperture0
address_offset : 0x17518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[124] FIFO[124] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[125]

FIFO Memory Aperture0
address_offset : 0x1790C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[125] FIFO[125] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[126]

FIFO Memory Aperture0
address_offset : 0x17D04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[126] FIFO[126] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


BLKR

Block Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLKR BLKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCNT BLKLEN

BCNT : MMC/SDIO Block Count - SDIO Byte Count
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0x0 : MULTIPLE

MMC/SD CARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer.

0x4 : BYTE

SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden.

0x5 : BLOCK

SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden.

End of enumeration elements list.

BLKLEN : Data Block Length
bits : 16 - 31 (16 bit)
access : read-write


FIFO[127]

FIFO Memory Aperture0
address_offset : 0x18100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[127] FIFO[127] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[128]

FIFO Memory Aperture0
address_offset : 0x18500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[128] FIFO[128] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[129]

FIFO Memory Aperture0
address_offset : 0x18904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[129] FIFO[129] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[130]

FIFO Memory Aperture0
address_offset : 0x18D0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[130] FIFO[130] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[10]

FIFO Memory Aperture0
address_offset : 0x18DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[10] FIFO[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[131]

FIFO Memory Aperture0
address_offset : 0x19118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[131] FIFO[131] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[132]

FIFO Memory Aperture0
address_offset : 0x19528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[132] FIFO[132] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[133]

FIFO Memory Aperture0
address_offset : 0x1993C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[133] FIFO[133] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[134]

FIFO Memory Aperture0
address_offset : 0x19D54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[134] FIFO[134] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[135]

FIFO Memory Aperture0
address_offset : 0x1A170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[135] FIFO[135] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[136]

FIFO Memory Aperture0
address_offset : 0x1A590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[136] FIFO[136] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[137]

FIFO Memory Aperture0
address_offset : 0x1A9B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[137] FIFO[137] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[138]

FIFO Memory Aperture0
address_offset : 0x1ADDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[138] FIFO[138] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[11]

FIFO Memory Aperture0
address_offset : 0x1B08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[11] FIFO[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[139]

FIFO Memory Aperture0
address_offset : 0x1B208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[139] FIFO[139] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[140]

FIFO Memory Aperture0
address_offset : 0x1B638 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[140] FIFO[140] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[141]

FIFO Memory Aperture0
address_offset : 0x1BA6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[141] FIFO[141] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[142]

FIFO Memory Aperture0
address_offset : 0x1BEA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[142] FIFO[142] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


CSTOR

Completion Signal Timeout Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSTOR CSTOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSTOCYC CSTOMUL

CSTOCYC : Completion Signal Timeout Cycle Number
bits : 0 - 3 (4 bit)
access : read-write

CSTOMUL : Completion Signal Timeout Multiplier
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 1

CSTOCYC x 1

0x1 : 16

CSTOCYC x 16

0x2 : 128

CSTOCYC x 128

0x3 : 256

CSTOCYC x 256

0x4 : 1024

CSTOCYC x 1024

0x5 : 4096

CSTOCYC x 4096

0x6 : 65536

CSTOCYC x 65536

0x7 : 1048576

CSTOCYC x 1048576

End of enumeration elements list.


FIFO[143]

FIFO Memory Aperture0
address_offset : 0x1C2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[143] FIFO[143] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[144]

FIFO Memory Aperture0
address_offset : 0x1C720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[144] FIFO[144] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[145]

FIFO Memory Aperture0
address_offset : 0x1CB64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[145] FIFO[145] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[146]

FIFO Memory Aperture0
address_offset : 0x1CFAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[146] FIFO[146] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[12]

FIFO Memory Aperture0
address_offset : 0x1D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[12] FIFO[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[147]

FIFO Memory Aperture0
address_offset : 0x1D3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[147] FIFO[147] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[148]

FIFO Memory Aperture0
address_offset : 0x1D848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[148] FIFO[148] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[149]

FIFO Memory Aperture0
address_offset : 0x1DC9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[149] FIFO[149] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[150]

FIFO Memory Aperture0
address_offset : 0x1E0F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[150] FIFO[150] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[151]

FIFO Memory Aperture0
address_offset : 0x1E550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[151] FIFO[151] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[152]

FIFO Memory Aperture0
address_offset : 0x1E9B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[152] FIFO[152] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[153]

FIFO Memory Aperture0
address_offset : 0x1EE14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[153] FIFO[153] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[154]

FIFO Memory Aperture0
address_offset : 0x1F27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[154] FIFO[154] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[13]

FIFO Memory Aperture0
address_offset : 0x1F6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[13] FIFO[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[155]

FIFO Memory Aperture0
address_offset : 0x1F6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[155] FIFO[155] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[156]

FIFO Memory Aperture0
address_offset : 0x1FB58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[156] FIFO[156] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[157]

FIFO Memory Aperture0
address_offset : 0x1FFCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[157] FIFO[157] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[158]

FIFO Memory Aperture0
address_offset : 0x20444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[158] FIFO[158] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[159]

FIFO Memory Aperture0
address_offset : 0x208C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[159] FIFO[159] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[160]

FIFO Memory Aperture0
address_offset : 0x20D40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[160] FIFO[160] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[161]

FIFO Memory Aperture0
address_offset : 0x211C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[161] FIFO[161] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[162]

FIFO Memory Aperture0
address_offset : 0x2164C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[162] FIFO[162] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[14]

FIFO Memory Aperture0
address_offset : 0x21A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[14] FIFO[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[163]

FIFO Memory Aperture0
address_offset : 0x21AD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[163] FIFO[163] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[164]

FIFO Memory Aperture0
address_offset : 0x21F68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[164] FIFO[164] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[165]

FIFO Memory Aperture0
address_offset : 0x223FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[165] FIFO[165] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[166]

FIFO Memory Aperture0
address_offset : 0x22894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[166] FIFO[166] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[167]

FIFO Memory Aperture0
address_offset : 0x22D30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[167] FIFO[167] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[168]

FIFO Memory Aperture0
address_offset : 0x231D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[168] FIFO[168] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[169]

FIFO Memory Aperture0
address_offset : 0x23674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[169] FIFO[169] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[170]

FIFO Memory Aperture0
address_offset : 0x23B1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[170] FIFO[170] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[15]

FIFO Memory Aperture0
address_offset : 0x23E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[15] FIFO[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[171]

FIFO Memory Aperture0
address_offset : 0x23FC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[171] FIFO[171] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[172]

FIFO Memory Aperture0
address_offset : 0x24478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[172] FIFO[172] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[173]

FIFO Memory Aperture0
address_offset : 0x2492C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[173] FIFO[173] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[174]

FIFO Memory Aperture0
address_offset : 0x24DE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[174] FIFO[174] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[175]

FIFO Memory Aperture0
address_offset : 0x252A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[175] FIFO[175] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[176]

FIFO Memory Aperture0
address_offset : 0x25760 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[176] FIFO[176] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[177]

FIFO Memory Aperture0
address_offset : 0x25C24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[177] FIFO[177] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[178]

FIFO Memory Aperture0
address_offset : 0x260EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[178] FIFO[178] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[16]

FIFO Memory Aperture0
address_offset : 0x2620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[16] FIFO[16] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[179]

FIFO Memory Aperture0
address_offset : 0x265B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[179] FIFO[179] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[180]

FIFO Memory Aperture0
address_offset : 0x26A88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[180] FIFO[180] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[181]

FIFO Memory Aperture0
address_offset : 0x26F5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[181] FIFO[181] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[182]

FIFO Memory Aperture0
address_offset : 0x27434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[182] FIFO[182] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[183]

FIFO Memory Aperture0
address_offset : 0x27910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[183] FIFO[183] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[184]

FIFO Memory Aperture0
address_offset : 0x27DF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[184] FIFO[184] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[185]

FIFO Memory Aperture0
address_offset : 0x282D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[185] FIFO[185] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[17]

FIFO Memory Aperture0
address_offset : 0x2864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[17] FIFO[17] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[186]

FIFO Memory Aperture0
address_offset : 0x287BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[186] FIFO[186] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[187]

FIFO Memory Aperture0
address_offset : 0x28CA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[187] FIFO[187] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[188]

FIFO Memory Aperture0
address_offset : 0x29198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[188] FIFO[188] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[189]

FIFO Memory Aperture0
address_offset : 0x2968C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[189] FIFO[189] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[190]

FIFO Memory Aperture0
address_offset : 0x29B84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[190] FIFO[190] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[191]

FIFO Memory Aperture0
address_offset : 0x2A080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[191] FIFO[191] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[192]

FIFO Memory Aperture0
address_offset : 0x2A580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[192] FIFO[192] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[193]

FIFO Memory Aperture0
address_offset : 0x2AA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[193] FIFO[193] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[18]

FIFO Memory Aperture0
address_offset : 0x2AAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[18] FIFO[18] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[194]

FIFO Memory Aperture0
address_offset : 0x2AF8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[194] FIFO[194] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[195]

FIFO Memory Aperture0
address_offset : 0x2B498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[195] FIFO[195] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[196]

FIFO Memory Aperture0
address_offset : 0x2B9A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[196] FIFO[196] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[197]

FIFO Memory Aperture0
address_offset : 0x2BEBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[197] FIFO[197] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[198]

FIFO Memory Aperture0
address_offset : 0x2C3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[198] FIFO[198] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[199]

FIFO Memory Aperture0
address_offset : 0x2C8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[199] FIFO[199] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[200]

FIFO Memory Aperture0
address_offset : 0x2CE10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[200] FIFO[200] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[19]

FIFO Memory Aperture0
address_offset : 0x2CF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[19] FIFO[19] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[201]

FIFO Memory Aperture0
address_offset : 0x2D334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[201] FIFO[201] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[202]

FIFO Memory Aperture0
address_offset : 0x2D85C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[202] FIFO[202] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[203]

FIFO Memory Aperture0
address_offset : 0x2DD88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[203] FIFO[203] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[204]

FIFO Memory Aperture0
address_offset : 0x2E2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[204] FIFO[204] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[205]

FIFO Memory Aperture0
address_offset : 0x2E7EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[205] FIFO[205] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[206]

FIFO Memory Aperture0
address_offset : 0x2ED24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[206] FIFO[206] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[207]

FIFO Memory Aperture0
address_offset : 0x2F260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[207] FIFO[207] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[20]

FIFO Memory Aperture0
address_offset : 0x2F48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[20] FIFO[20] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[208]

FIFO Memory Aperture0
address_offset : 0x2F7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[208] FIFO[208] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[209]

FIFO Memory Aperture0
address_offset : 0x2FCE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[209] FIFO[209] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


RDR

Receive Data Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDR RDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read
bits : 0 - 31 (32 bit)
access : read-only


FIFO[210]

FIFO Memory Aperture0
address_offset : 0x3022C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[210] FIFO[210] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[211]

FIFO Memory Aperture0
address_offset : 0x30778 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[211] FIFO[211] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[212]

FIFO Memory Aperture0
address_offset : 0x30CC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[212] FIFO[212] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[213]

FIFO Memory Aperture0
address_offset : 0x3121C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[213] FIFO[213] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[214]

FIFO Memory Aperture0
address_offset : 0x31774 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[214] FIFO[214] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[21]

FIFO Memory Aperture0
address_offset : 0x319C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[21] FIFO[21] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[215]

FIFO Memory Aperture0
address_offset : 0x31CD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[215] FIFO[215] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[216]

FIFO Memory Aperture0
address_offset : 0x32230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[216] FIFO[216] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[217]

FIFO Memory Aperture0
address_offset : 0x32794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[217] FIFO[217] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[218]

FIFO Memory Aperture0
address_offset : 0x32CFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[218] FIFO[218] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[219]

FIFO Memory Aperture0
address_offset : 0x33268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[219] FIFO[219] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[220]

FIFO Memory Aperture0
address_offset : 0x337D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[220] FIFO[220] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[221]

FIFO Memory Aperture0
address_offset : 0x33D4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[221] FIFO[221] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[22]

FIFO Memory Aperture0
address_offset : 0x33F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[22] FIFO[22] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


TDR

Transmit Data Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TDR TDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Write
bits : 0 - 31 (32 bit)
access : write-only


FIFO[222]

FIFO Memory Aperture0
address_offset : 0x342C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[222] FIFO[222] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[223]

FIFO Memory Aperture0
address_offset : 0x34840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[223] FIFO[223] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[224]

FIFO Memory Aperture0
address_offset : 0x34DC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[224] FIFO[224] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[225]

FIFO Memory Aperture0
address_offset : 0x35344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[225] FIFO[225] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[226]

FIFO Memory Aperture0
address_offset : 0x358CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[226] FIFO[226] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[227]

FIFO Memory Aperture0
address_offset : 0x35E58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[227] FIFO[227] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[228]

FIFO Memory Aperture0
address_offset : 0x363E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[228] FIFO[228] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[23]

FIFO Memory Aperture0
address_offset : 0x3650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[23] FIFO[23] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[229]

FIFO Memory Aperture0
address_offset : 0x3697C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[229] FIFO[229] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[230]

FIFO Memory Aperture0
address_offset : 0x36F14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[230] FIFO[230] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[231]

FIFO Memory Aperture0
address_offset : 0x374B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[231] FIFO[231] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[232]

FIFO Memory Aperture0
address_offset : 0x37A50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[232] FIFO[232] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[233]

FIFO Memory Aperture0
address_offset : 0x37FF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[233] FIFO[233] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[234]

FIFO Memory Aperture0
address_offset : 0x3859C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[234] FIFO[234] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[24]

FIFO Memory Aperture0
address_offset : 0x38B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[24] FIFO[24] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[235]

FIFO Memory Aperture0
address_offset : 0x38B48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[235] FIFO[235] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[236]

FIFO Memory Aperture0
address_offset : 0x390F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[236] FIFO[236] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[237]

FIFO Memory Aperture0
address_offset : 0x396AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[237] FIFO[237] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[238]

FIFO Memory Aperture0
address_offset : 0x39C64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[238] FIFO[238] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[239]

FIFO Memory Aperture0
address_offset : 0x3A220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[239] FIFO[239] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[240]

FIFO Memory Aperture0
address_offset : 0x3A7E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[240] FIFO[240] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[241]

FIFO Memory Aperture0
address_offset : 0x3ADA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[241] FIFO[241] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[25]

FIFO Memory Aperture0
address_offset : 0x3B14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[25] FIFO[25] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[242]

FIFO Memory Aperture0
address_offset : 0x3B36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[242] FIFO[242] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[243]

FIFO Memory Aperture0
address_offset : 0x3B938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[243] FIFO[243] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[244]

FIFO Memory Aperture0
address_offset : 0x3BF08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[244] FIFO[244] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[245]

FIFO Memory Aperture0
address_offset : 0x3C4DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[245] FIFO[245] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[246]

FIFO Memory Aperture0
address_offset : 0x3CAB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[246] FIFO[246] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[247]

FIFO Memory Aperture0
address_offset : 0x3D090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[247] FIFO[247] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[248]

FIFO Memory Aperture0
address_offset : 0x3D670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[248] FIFO[248] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[26]

FIFO Memory Aperture0
address_offset : 0x3D7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[26] FIFO[26] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[249]

FIFO Memory Aperture0
address_offset : 0x3DC54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[249] FIFO[249] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[250]

FIFO Memory Aperture0
address_offset : 0x3E23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[250] FIFO[250] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[251]

FIFO Memory Aperture0
address_offset : 0x3E828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[251] FIFO[251] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[252]

FIFO Memory Aperture0
address_offset : 0x3EE18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[252] FIFO[252] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[253]

FIFO Memory Aperture0
address_offset : 0x3F40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[253] FIFO[253] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[254]

FIFO Memory Aperture0
address_offset : 0x3FA04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[254] FIFO[254] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[27]

FIFO Memory Aperture0
address_offset : 0x3FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[27] FIFO[27] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


MR

Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKDIV PWSDIV RDPROOF WRPROOF FBYTE PADV CLKODD

CLKDIV : Clock Divider
bits : 0 - 7 (8 bit)
access : read-write

PWSDIV : Power Saving Divider
bits : 8 - 10 (3 bit)
access : read-write

RDPROOF : Read Proof Enable
bits : 11 - 11 (1 bit)
access : read-write

WRPROOF : Write Proof Enable
bits : 12 - 12 (1 bit)
access : read-write

FBYTE : Force Byte Transfer
bits : 13 - 13 (1 bit)
access : read-write

PADV : Padding Value
bits : 14 - 14 (1 bit)
access : read-write

CLKODD : Clock divider is odd
bits : 16 - 16 (1 bit)
access : read-write


RSPR[0]

Response Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RSPR[0] RSPR[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSP

RSP : Response
bits : 0 - 31 (32 bit)
access : read-only


SR

Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDRDY RXRDY TXRDY BLKE DTIP NOTBUSY SDIOIRQA SDIOWAIT CSRCV RINDE RDIRE RCRCE RENDE RTOE DCRCE DTOE CSTOE BLKOVRE DMADONE FIFOEMPTY XFRDONE ACKRCV ACKRCVE OVRE UNRE

CMDRDY : Command Ready
bits : 0 - 0 (1 bit)
access : read-only

RXRDY : Receiver Ready
bits : 1 - 1 (1 bit)
access : read-only

TXRDY : Transmit Ready
bits : 2 - 2 (1 bit)
access : read-only

BLKE : Data Block Ended
bits : 3 - 3 (1 bit)
access : read-only

DTIP : Data Transfer in Progress
bits : 4 - 4 (1 bit)
access : read-only

NOTBUSY : HSMCI Not Busy
bits : 5 - 5 (1 bit)
access : read-only

SDIOIRQA : SDIO Interrupt for Slot A
bits : 8 - 8 (1 bit)
access : read-only

SDIOWAIT : SDIO Read Wait Operation Status
bits : 12 - 12 (1 bit)
access : read-only

CSRCV : CE-ATA Completion Signal Received
bits : 13 - 13 (1 bit)
access : read-only

RINDE : Response Index Error
bits : 16 - 16 (1 bit)
access : read-only

RDIRE : Response Direction Error
bits : 17 - 17 (1 bit)
access : read-only

RCRCE : Response CRC Error
bits : 18 - 18 (1 bit)
access : read-only

RENDE : Response End Bit Error
bits : 19 - 19 (1 bit)
access : read-only

RTOE : Response Time-out Error
bits : 20 - 20 (1 bit)
access : read-only

DCRCE : Data CRC Error
bits : 21 - 21 (1 bit)
access : read-only

DTOE : Data Time-out Error
bits : 22 - 22 (1 bit)
access : read-only

CSTOE : Completion Signal Time-out Error
bits : 23 - 23 (1 bit)
access : read-only

BLKOVRE : DMA Block Overrun Error
bits : 24 - 24 (1 bit)
access : read-only

DMADONE : DMA Transfer done
bits : 25 - 25 (1 bit)
access : read-only

FIFOEMPTY : FIFO empty flag
bits : 26 - 26 (1 bit)
access : read-only

XFRDONE : Transfer Done flag
bits : 27 - 27 (1 bit)
access : read-only

ACKRCV : Boot Operation Acknowledge Received
bits : 28 - 28 (1 bit)
access : read-only

ACKRCVE : Boot Operation Acknowledge Error
bits : 29 - 29 (1 bit)
access : read-only

OVRE : Overrun
bits : 30 - 30 (1 bit)
access : read-only

UNRE : Underrun
bits : 31 - 31 (1 bit)
access : read-only


FIFO[0]

FIFO Memory Aperture0
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[0] FIFO[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[255]

FIFO Memory Aperture0
address_offset : 0x40000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[255] FIFO[255] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[28]

FIFO Memory Aperture0
address_offset : 0x4258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[28] FIFO[28] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


IER

Interrupt Enable Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDRDY RXRDY TXRDY BLKE DTIP NOTBUSY SDIOIRQA SDIOWAIT CSRCV RINDE RDIRE RCRCE RENDE RTOE DCRCE DTOE CSTOE BLKOVRE DMADONE FIFOEMPTY XFRDONE ACKRCV ACKRCVE OVRE UNRE

CMDRDY : Command Ready Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

RXRDY : Receiver Ready Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXRDY : Transmit Ready Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

BLKE : Data Block Ended Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

DTIP : Data Transfer in Progress Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

NOTBUSY : Data Not Busy Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

SDIOIRQA : SDIO Interrupt for Slot A Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

SDIOWAIT : SDIO Read Wait Operation Status Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

CSRCV : Completion Signal Received Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

RINDE : Response Index Error Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only

RDIRE : Response Direction Error Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only

RCRCE : Response CRC Error Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

RENDE : Response End Bit Error Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only

RTOE : Response Time-out Error Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only

DCRCE : Data CRC Error Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only

DTOE : Data Time-out Error Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only

CSTOE : Completion Signal Timeout Error Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only

BLKOVRE : DMA Block Overrun Error Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only

DMADONE : DMA Transfer completed Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only

FIFOEMPTY : FIFO empty Interrupt enable
bits : 26 - 26 (1 bit)
access : write-only

XFRDONE : Transfer Done Interrupt enable
bits : 27 - 27 (1 bit)
access : write-only

ACKRCV : Boot Acknowledge Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only

ACKRCVE : Boot Acknowledge Error Interrupt Enable
bits : 29 - 29 (1 bit)
access : write-only

OVRE : Overrun Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only

UNRE : Underrun Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


FIFO[29]

FIFO Memory Aperture0
address_offset : 0x44CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[29] FIFO[29] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[30]

FIFO Memory Aperture0
address_offset : 0x4744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[30] FIFO[30] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


IDR

Interrupt Disable Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDRDY RXRDY TXRDY BLKE DTIP NOTBUSY SDIOIRQA SDIOWAIT CSRCV RINDE RDIRE RCRCE RENDE RTOE DCRCE DTOE CSTOE BLKOVRE DMADONE FIFOEMPTY XFRDONE ACKRCV ACKRCVE OVRE UNRE

CMDRDY : Command Ready Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

RXRDY : Receiver Ready Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXRDY : Transmit Ready Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

BLKE : Data Block Ended Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

DTIP : Data Transfer in Progress Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

NOTBUSY : Data Not Busy Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

SDIOIRQA : SDIO Interrupt for Slot A Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

SDIOWAIT : SDIO Read Wait Operation Status Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

CSRCV : Completion Signal received interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

RINDE : Response Index Error Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only

RDIRE : Response Direction Error Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only

RCRCE : Response CRC Error Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

RENDE : Response End Bit Error Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only

RTOE : Response Time-out Error Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only

DCRCE : Data CRC Error Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only

DTOE : Data Time-out Error Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only

CSTOE : Completion Signal Time out Error Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only

BLKOVRE : DMA Block Overrun Error Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only

DMADONE : DMA Transfer completed Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only

FIFOEMPTY : FIFO empty Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only

XFRDONE : Transfer Done Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only

ACKRCV : Boot Acknowledge Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only

ACKRCVE : Boot Acknowledge Error Interrupt Disable
bits : 29 - 29 (1 bit)
access : write-only

OVRE : Overrun Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only

UNRE : Underrun Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


FIFO[31]

FIFO Memory Aperture0
address_offset : 0x49C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[31] FIFO[31] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


IMR

Interrupt Mask Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDRDY RXRDY TXRDY BLKE DTIP NOTBUSY SDIOIRQA SDIOWAIT CSRCV RINDE RDIRE RCRCE RENDE RTOE DCRCE DTOE CSTOE BLKOVRE DMADONE FIFOEMPTY XFRDONE ACKRCV ACKRCVE OVRE UNRE

CMDRDY : Command Ready Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

RXRDY : Receiver Ready Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

TXRDY : Transmit Ready Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

BLKE : Data Block Ended Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only

DTIP : Data Transfer in Progress Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only

NOTBUSY : Data Not Busy Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

SDIOIRQA : SDIO Interrupt for Slot A Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only

SDIOWAIT : SDIO Read Wait Operation Status Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only

CSRCV : Completion Signal Received Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only

RINDE : Response Index Error Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only

RDIRE : Response Direction Error Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only

RCRCE : Response CRC Error Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only

RENDE : Response End Bit Error Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only

RTOE : Response Time-out Error Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only

DCRCE : Data CRC Error Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only

DTOE : Data Time-out Error Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only

CSTOE : Completion Signal Time-out Error Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only

BLKOVRE : DMA Block Overrun Error Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only

DMADONE : DMA Transfer Completed Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only

FIFOEMPTY : FIFO Empty Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only

XFRDONE : Transfer Done Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only

ACKRCV : Boot Operation Acknowledge Received Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only

ACKRCVE : Boot Operation Acknowledge Error Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-only

OVRE : Overrun Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only

UNRE : Underrun Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-only


FIFO[32]

FIFO Memory Aperture0
address_offset : 0x4C40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[32] FIFO[32] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[33]

FIFO Memory Aperture0
address_offset : 0x4EC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[33] FIFO[33] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


DMA

DMA Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET CHKSIZE DMAEN ROPT

OFFSET : DMA Write Buffer Offset
bits : 0 - 1 (2 bit)
access : read-write

CHKSIZE : DMA Channel Read and Write Chunk Size
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : 1

1 data available

1 : 4

4 data available

End of enumeration elements list.

DMAEN : DMA Hardware Handshaking Enable
bits : 8 - 8 (1 bit)
access : read-write

ROPT : Read Optimization with padding
bits : 12 - 12 (1 bit)
access : read-write


FIFO[34]

FIFO Memory Aperture0
address_offset : 0x514C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[34] FIFO[34] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[35]

FIFO Memory Aperture0
address_offset : 0x53D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[35] FIFO[35] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


CFG

Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOMODE FERRCTRL HSMODE LSYNC

FIFOMODE : HSMCI Internal FIFO control mode
bits : 0 - 0 (1 bit)
access : read-write

FERRCTRL : Flow Error flag reset control mode
bits : 4 - 4 (1 bit)
access : read-write

HSMODE : High Speed Mode
bits : 8 - 8 (1 bit)
access : read-write

LSYNC : Synchronize on the last block
bits : 12 - 12 (1 bit)
access : read-write


FIFO[36]

FIFO Memory Aperture0
address_offset : 0x5668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[36] FIFO[36] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[37]

FIFO Memory Aperture0
address_offset : 0x58FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[37] FIFO[37] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[38]

FIFO Memory Aperture0
address_offset : 0x5B94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[38] FIFO[38] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[39]

FIFO Memory Aperture0
address_offset : 0x5E30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[39] FIFO[39] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[1]

FIFO Memory Aperture0
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[1] FIFO[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[40]

FIFO Memory Aperture0
address_offset : 0x60D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[40] FIFO[40] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[41]

FIFO Memory Aperture0
address_offset : 0x6374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[41] FIFO[41] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


RSPR[1]

Response Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RSPR[1] RSPR[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSP

RSP : Response
bits : 0 - 31 (32 bit)
access : read-only


FIFO[42]

FIFO Memory Aperture0
address_offset : 0x661C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[42] FIFO[42] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[43]

FIFO Memory Aperture0
address_offset : 0x68C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[43] FIFO[43] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[44]

FIFO Memory Aperture0
address_offset : 0x6B78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[44] FIFO[44] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[45]

FIFO Memory Aperture0
address_offset : 0x6E2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[45] FIFO[45] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[46]

FIFO Memory Aperture0
address_offset : 0x70E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[46] FIFO[46] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[47]

FIFO Memory Aperture0
address_offset : 0x73A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[47] FIFO[47] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[48]

FIFO Memory Aperture0
address_offset : 0x7660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[48] FIFO[48] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[49]

FIFO Memory Aperture0
address_offset : 0x7924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[49] FIFO[49] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[50]

FIFO Memory Aperture0
address_offset : 0x7BEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[50] FIFO[50] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[51]

FIFO Memory Aperture0
address_offset : 0x7EB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[51] FIFO[51] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


DTOR

Data Timeout Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTOR DTOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTOCYC DTOMUL

DTOCYC : Data Timeout Cycle Number
bits : 0 - 3 (4 bit)
access : read-write

DTOMUL : Data Timeout Multiplier
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 1

DTOCYC

0x1 : 16

DTOCYC x 16

0x2 : 128

DTOCYC x 128

0x3 : 256

DTOCYC x 256

0x4 : 1024

DTOCYC x 1024

0x5 : 4096

DTOCYC x 4096

0x6 : 65536

DTOCYC x 65536

0x7 : 1048576

DTOCYC x 1048576

End of enumeration elements list.


FIFO[2]

FIFO Memory Aperture0
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[2] FIFO[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[52]

FIFO Memory Aperture0
address_offset : 0x8188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[52] FIFO[52] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[53]

FIFO Memory Aperture0
address_offset : 0x845C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[53] FIFO[53] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[54]

FIFO Memory Aperture0
address_offset : 0x8734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[54] FIFO[54] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[55]

FIFO Memory Aperture0
address_offset : 0x8A10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[55] FIFO[55] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


RSPR[2]

Response Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RSPR[2] RSPR[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSP

RSP : Response
bits : 0 - 31 (32 bit)
access : read-only


FIFO[56]

FIFO Memory Aperture0
address_offset : 0x8CF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[56] FIFO[56] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[57]

FIFO Memory Aperture0
address_offset : 0x8FD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[57] FIFO[57] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[58]

FIFO Memory Aperture0
address_offset : 0x92BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[58] FIFO[58] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[59]

FIFO Memory Aperture0
address_offset : 0x95A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[59] FIFO[59] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[60]

FIFO Memory Aperture0
address_offset : 0x9898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[60] FIFO[60] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[61]

FIFO Memory Aperture0
address_offset : 0x9B8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[61] FIFO[61] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[62]

FIFO Memory Aperture0
address_offset : 0x9E84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[62] FIFO[62] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[3]

FIFO Memory Aperture0
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[3] FIFO[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[63]

FIFO Memory Aperture0
address_offset : 0xA180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[63] FIFO[63] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[64]

FIFO Memory Aperture0
address_offset : 0xA480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[64] FIFO[64] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[65]

FIFO Memory Aperture0
address_offset : 0xA784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[65] FIFO[65] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[66]

FIFO Memory Aperture0
address_offset : 0xAA8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[66] FIFO[66] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[67]

FIFO Memory Aperture0
address_offset : 0xAD98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[67] FIFO[67] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[68]

FIFO Memory Aperture0
address_offset : 0xB0A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[68] FIFO[68] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[69]

FIFO Memory Aperture0
address_offset : 0xB3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[69] FIFO[69] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[70]

FIFO Memory Aperture0
address_offset : 0xB6D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[70] FIFO[70] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


RSPR[3]

Response Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RSPR[3] RSPR[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSP

RSP : Response
bits : 0 - 31 (32 bit)
access : read-only


FIFO[71]

FIFO Memory Aperture0
address_offset : 0xB9F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[71] FIFO[71] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[72]

FIFO Memory Aperture0
address_offset : 0xBD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[72] FIFO[72] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


SDCR

SD/SDIO Card Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDCR SDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCSEL SDCBUS

SDCSEL : SDCard/SDIO Slot
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : SLOTA

Slot A is selected.

0x1 : SLOTB

-

0x2 : SLOTC

-

0x3 : SLOTD

-

End of enumeration elements list.

SDCBUS : SDCard/SDIO Bus Width
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0x0 : 1

1 bit

0x2 : 4

4 bit

0x3 : 8

8 bit

End of enumeration elements list.


FIFO[73]

FIFO Memory Aperture0
address_offset : 0xC034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[73] FIFO[73] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[4]

FIFO Memory Aperture0
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[4] FIFO[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[74]

FIFO Memory Aperture0
address_offset : 0xC35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[74] FIFO[74] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[75]

FIFO Memory Aperture0
address_offset : 0xC688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[75] FIFO[75] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[76]

FIFO Memory Aperture0
address_offset : 0xC9B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[76] FIFO[76] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[77]

FIFO Memory Aperture0
address_offset : 0xCCEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[77] FIFO[77] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[78]

FIFO Memory Aperture0
address_offset : 0xD024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[78] FIFO[78] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[79]

FIFO Memory Aperture0
address_offset : 0xD360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[79] FIFO[79] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[80]

FIFO Memory Aperture0
address_offset : 0xD6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[80] FIFO[80] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[81]

FIFO Memory Aperture0
address_offset : 0xD9E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[81] FIFO[81] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[82]

FIFO Memory Aperture0
address_offset : 0xDD2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[82] FIFO[82] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[83]

FIFO Memory Aperture0
address_offset : 0xE078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[83] FIFO[83] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[5]

FIFO Memory Aperture0
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[5] FIFO[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[84]

FIFO Memory Aperture0
address_offset : 0xE3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[84] FIFO[84] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WP_EN WP_KEY

WP_EN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write

WP_KEY : Write Protection Key password
bits : 8 - 31 (24 bit)
access : read-write


FIFO[85]

FIFO Memory Aperture0
address_offset : 0xE71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[85] FIFO[85] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


WPSR

Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WP_VS WP_VSRC

WP_VS : Write Protection Violation Status
bits : 0 - 3 (4 bit)
access : read-only

Enumeration:

0x0 : NONE

No Write Protection Violation occurred since the last read of this register (WP_SR)

0x1 : WRITE

Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.)

0x2 : RESET

Software reset had been performed while Write Protection was enabled (since the last read).

0x3 : BOTH

Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read.

End of enumeration elements list.

WP_VSRC : Write Protection Violation SouRCe
bits : 8 - 23 (16 bit)
access : read-only


FIFO[86]

FIFO Memory Aperture0
address_offset : 0xEA74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[86] FIFO[86] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[87]

FIFO Memory Aperture0
address_offset : 0xEDD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[87] FIFO[87] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[88]

FIFO Memory Aperture0
address_offset : 0xF130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[88] FIFO[88] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[89]

FIFO Memory Aperture0
address_offset : 0xF494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[89] FIFO[89] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[90]

FIFO Memory Aperture0
address_offset : 0xF7FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[90] FIFO[90] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[91]

FIFO Memory Aperture0
address_offset : 0xFB68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[91] FIFO[91] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write


FIFO[92]

FIFO Memory Aperture0
address_offset : 0xFED8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[92] FIFO[92] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to Read or Data to Write
bits : 0 - 31 (32 bit)
access : read-write



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