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UDPHS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

IEN

EPTCFG0

EPTCTLENB0

EPTCTLENB0_ISOENDPT

EPTCTLDIS0

EPTCTLDIS0_ISOENDPT

EPTCTL0

EPTCTL0_ISOENDPT

EPTSETSTA0

EPTSETSTA0_ISOENDPT

EPTCLRSTA0

EPTCLRSTA0_ISOENDPT

EPTSTA0

EPTSTA0_ISOENDPT

EPTCFG1

EPTCTLENB1

EPTCTLENB1_ISOENDPT

EPTCTLDIS1

EPTCTLDIS1_ISOENDPT

EPTCTL1

EPTCTL1_ISOENDPT

EPTSETSTA1

EPTSETSTA1_ISOENDPT

EPTCLRSTA1

EPTCLRSTA1_ISOENDPT

EPTSTA1

EPTSTA1_ISOENDPT

INTSTA

EPTCFG2

EPTCTLENB2

EPTCTLENB2_ISOENDPT

EPTCTLDIS2

EPTCTLDIS2_ISOENDPT

EPTCTL2

EPTCTL2_ISOENDPT

EPTSETSTA2

EPTSETSTA2_ISOENDPT

EPTCLRSTA2

EPTCLRSTA2_ISOENDPT

EPTSTA2

EPTSTA2_ISOENDPT

EPTCFG3

EPTCTLENB3

EPTCTLENB3_ISOENDPT

EPTCTLDIS3

EPTCTLDIS3_ISOENDPT

EPTCTL3

EPTCTL3_ISOENDPT

EPTSETSTA3

EPTSETSTA3_ISOENDPT

EPTCLRSTA3

EPTCLRSTA3_ISOENDPT

EPTSTA3

EPTSTA3_ISOENDPT

CLRINT

EPTCFG4

EPTCTLENB4

EPTCTLENB4_ISOENDPT

EPTCTLDIS4

EPTCTLDIS4_ISOENDPT

EPTCTL4

EPTCTL4_ISOENDPT

EPTSETSTA4

EPTSETSTA4_ISOENDPT

EPTCLRSTA4

EPTCLRSTA4_ISOENDPT

EPTSTA4

EPTSTA4_ISOENDPT

EPTCFG5

EPTCTLENB5

EPTCTLENB5_ISOENDPT

EPTCTLDIS5

EPTCTLDIS5_ISOENDPT

EPTCTL5

EPTCTL5_ISOENDPT

EPTSETSTA5

EPTSETSTA5_ISOENDPT

EPTCLRSTA5

EPTCLRSTA5_ISOENDPT

EPTSTA5

EPTSTA5_ISOENDPT

EPTRST

EPTCFG6

EPTCTLENB6

EPTCTLENB6_ISOENDPT

EPTCTLDIS6

EPTCTLDIS6_ISOENDPT

EPTCTL6

EPTCTL6_ISOENDPT

EPTSETSTA6

EPTSETSTA6_ISOENDPT

EPTCLRSTA6

EPTCLRSTA6_ISOENDPT

EPTSTA6

EPTSTA6_ISOENDPT

DMANXTDSC0

DMAADDRESS0

DMACONTROL0

DMASTATUS0

DMANXTDSC1

DMAADDRESS1

DMACONTROL1

DMASTATUS1

DMANXTDSC2

DMAADDRESS2

DMACONTROL2

DMASTATUS2

DMANXTDSC3

DMAADDRESS3

DMACONTROL3

DMASTATUS3

DMANXTDSC4

DMAADDRESS4

DMACONTROL4

DMASTATUS4

DMANXTDSC5

DMAADDRESS5

DMACONTROL5

DMASTATUS5

FNUM

TST


CTRL

UDPHS Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEV_ADDR FADDR_EN EN_UDPHS DETACH REWAKEUP PULLD_DIS

DEV_ADDR : UDPHS Address
bits : 0 - 6 (7 bit)
access : read-write

FADDR_EN : Function Address Enable
bits : 7 - 7 (1 bit)
access : read-write

EN_UDPHS : UDPHS Enable
bits : 8 - 8 (1 bit)
access : read-write

DETACH : Detach Command
bits : 9 - 9 (1 bit)
access : read-write

REWAKEUP : Send Remote Wake Up
bits : 10 - 10 (1 bit)
access : read-write

PULLD_DIS : Pull-Down Disable
bits : 11 - 11 (1 bit)
access : read-write


IEN

UDPHS Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DET_SUSPD MICRO_SOF INT_SOF ENDRESET WAKE_UP ENDOFRSM UPSTR_RES EPT_0 EPT_1 EPT_2 EPT_3 EPT_4 EPT_5 EPT_6 DMA_1 DMA_2 DMA_3 DMA_4 DMA_5 DMA_6

DET_SUSPD : Suspend Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

MICRO_SOF : Micro-SOF Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

INT_SOF : SOF Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

ENDRESET : End Of Reset Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

WAKE_UP : Wake Up CPU Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

ENDOFRSM : End Of Resume Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

UPSTR_RES : Upstream Resume Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

EPT_0 : Endpoint 0 Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

EPT_1 : Endpoint 1 Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

EPT_2 : Endpoint 2 Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

EPT_3 : Endpoint 3 Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

EPT_4 : Endpoint 4 Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

EPT_5 : Endpoint 5 Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write

EPT_6 : Endpoint 6 Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

DMA_1 : DMA Channel 1 Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-write

DMA_2 : DMA Channel 2 Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-write

DMA_3 : DMA Channel 3 Interrupt Enable
bits : 27 - 27 (1 bit)
access : read-write

DMA_4 : DMA Channel 4 Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-write

DMA_5 : DMA Channel 5 Interrupt Enable
bits : 29 - 29 (1 bit)
access : read-write

DMA_6 : DMA Channel 6 Interrupt Enable
bits : 30 - 30 (1 bit)
access : read-write


EPTCFG0

UDPHS Endpoint Configuration Register (endpoint = 0)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPTCFG0 EPTCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_SIZE EPT_DIR EPT_TYPE BK_NUMBER NB_TRANS EPT_MAPD

EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 8

8 bytes

0x1 : 16

16 bytes

0x2 : 32

32 bytes

0x3 : 64

64 bytes

0x4 : 128

128 bytes

0x5 : 256

256 bytes

0x6 : 512

512 bytes

0x7 : 1024

1024 bytes

End of enumeration elements list.

EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write

EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL8

Control endpoint

0x1 : ISO

Isochronous endpoint

0x2 : BULK

Bulk endpoint

0x3 : INT

Interrupt endpoint

End of enumeration elements list.

BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0x0 : 0

Zero bank, the endpoint is not mapped in memory

0x1 : 1

One bank (bank 0)

0x2 : 2

Double bank (Ping-Pong: bank0/bank1)

0x3 : 3

Triple bank (bank0/bank1/bank2)

End of enumeration elements list.

NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write

EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write


EPTCTLENB0

UDPHS Endpoint Control Enable Register (endpoint = 0)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTLENB0 EPTCTLENB0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLENB0_ISOENDPT

UDPHS Endpoint Control Enable Register (endpoint = 0)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTLENB0_ISOENDPT EPTCTLENB0_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only

MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLDIS0

UDPHS Endpoint Control Disable Register (endpoint = 0)
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTLDIS0 EPTCTLDIS0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_DISABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLDIS0_ISOENDPT

UDPHS Endpoint Control Disable Register (endpoint = 0)
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTLDIS0_ISOENDPT EPTCTLDIS0_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_DISABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only

MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTL0

UDPHS Endpoint Control Register (endpoint = 0)
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTL0 EPTCTL0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only

AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only

INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only

NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only

ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only

TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only

RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only

STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only

NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only

NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only

BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only

SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only


EPTCTL0_ISOENDPT

UDPHS Endpoint Control Register (endpoint = 0)
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTL0_ISOENDPT EPTCTL0_ISOENDPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only

AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only

INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only

DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only

MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only

ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only

ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only

ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only

BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only

SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only


EPTSETSTA0

UDPHS Endpoint Set Status Register (endpoint = 0)
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTSETSTA0 EPTSETSTA0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL RXRDY_TXKL TXRDY

FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only

RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only

TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only


EPTSETSTA0_ISOENDPT

UDPHS Endpoint Set Status Register (endpoint = 0)
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTSETSTA0_ISOENDPT EPTSETSTA0_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY_TXKL TXRDY_TRER

RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only


EPTCLRSTA0

UDPHS Endpoint Clear Status Register (endpoint = 0)
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCLRSTA0 EPTCLRSTA0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL TOGGLESQ RXRDY_TXKL TX_COMPLT RX_SETUP STALL_SNT NAK_IN NAK_OUT

FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only

TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only

RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only


EPTCLRSTA0_ISOENDPT

UDPHS Endpoint Clear Status Register (endpoint = 0)
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCLRSTA0_ISOENDPT EPTCLRSTA0_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOGGLESQ RXRDY_TXKL TX_COMPLT ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH

TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only


EPTSTA0

UDPHS Endpoint Status Register (endpoint = 0)
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPTSTA0 EPTSTA0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL TOGGLESQ_STA ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT CURBK_CTLDIR BUSY_BANK_STA BYTE_COUNT SHRT_PCKT

FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only

TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only

Enumeration:

0x0 : DATA0

DATA0

0x1 : DATA1

DATA1

0x2 : DATA2

Reserved for High Bandwidth Isochronous Endpoint

0x3 : MDATA

Reserved for High Bandwidth Isochronous Endpoint

End of enumeration elements list.

ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only

TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only

RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only

STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only

NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only

NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only

CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only

BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only

Enumeration:

0x0 : 1BUSYBANK

1 busy bank

0x1 : 2BUSYBANKS

2 busy banks

0x2 : 3BUSYBANKS

3 busy banks

End of enumeration elements list.

BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only

SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only


EPTSTA0_ISOENDPT

UDPHS Endpoint Status Register (endpoint = 0)
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTSTA0_ISOENDPT EPTSTA0_ISOENDPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOGGLESQ_STA ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH CURBK BUSY_BANK_STA BYTE_COUNT SHRT_PCKT

TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only

Enumeration:

0x0 : DATA0

DATA0

0x1 : DATA1

DATA1

0x2 : DATA2

Data2 (only for High Bandwidth Isochronous Endpoint)

0x3 : MDATA

MData (only for High Bandwidth Isochronous Endpoint)

End of enumeration elements list.

ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only

TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only

ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only

ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only

ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only

CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Bank 0 (or single bank)

0x1 : BANK1

Bank 1

0x2 : BANK2

Bank 2

End of enumeration elements list.

BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only

Enumeration:

0x0 : 1BUSYBANK

1 busy bank

0x1 : 2BUSYBANKS

2 busy banks

0x2 : 3BUSYBANKS

3 busy banks

End of enumeration elements list.

BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only

SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only


EPTCFG1

UDPHS Endpoint Configuration Register (endpoint = 1)
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPTCFG1 EPTCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_SIZE EPT_DIR EPT_TYPE BK_NUMBER NB_TRANS EPT_MAPD

EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 8

8 bytes

0x1 : 16

16 bytes

0x2 : 32

32 bytes

0x3 : 64

64 bytes

0x4 : 128

128 bytes

0x5 : 256

256 bytes

0x6 : 512

512 bytes

0x7 : 1024

1024 bytes

End of enumeration elements list.

EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write

EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL8

Control endpoint

0x1 : ISO

Isochronous endpoint

0x2 : BULK

Bulk endpoint

0x3 : INT

Interrupt endpoint

End of enumeration elements list.

BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0x0 : 0

Zero bank, the endpoint is not mapped in memory

0x1 : 1

One bank (bank 0)

0x2 : 2

Double bank (Ping-Pong: bank0/bank1)

0x3 : 3

Triple bank (bank0/bank1/bank2)

End of enumeration elements list.

NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write

EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write


EPTCTLENB1

UDPHS Endpoint Control Enable Register (endpoint = 1)
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTLENB1 EPTCTLENB1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLENB1_ISOENDPT

UDPHS Endpoint Control Enable Register (endpoint = 1)
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTLENB1_ISOENDPT EPTCTLENB1_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only

MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLDIS1

UDPHS Endpoint Control Disable Register (endpoint = 1)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTLDIS1 EPTCTLDIS1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_DISABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLDIS1_ISOENDPT

UDPHS Endpoint Control Disable Register (endpoint = 1)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTLDIS1_ISOENDPT EPTCTLDIS1_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_DISABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only

MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTL1

UDPHS Endpoint Control Register (endpoint = 1)
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTL1 EPTCTL1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only

AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only

INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only

NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only

ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only

TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only

RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only

STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only

NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only

NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only

BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only

SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only


EPTCTL1_ISOENDPT

UDPHS Endpoint Control Register (endpoint = 1)
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTL1_ISOENDPT EPTCTL1_ISOENDPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only

AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only

INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only

DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only

MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only

ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only

ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only

ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only

BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only

SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only


EPTSETSTA1

UDPHS Endpoint Set Status Register (endpoint = 1)
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTSETSTA1 EPTSETSTA1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL RXRDY_TXKL TXRDY

FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only

RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only

TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only


EPTSETSTA1_ISOENDPT

UDPHS Endpoint Set Status Register (endpoint = 1)
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTSETSTA1_ISOENDPT EPTSETSTA1_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY_TXKL TXRDY_TRER

RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only


EPTCLRSTA1

UDPHS Endpoint Clear Status Register (endpoint = 1)
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCLRSTA1 EPTCLRSTA1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL TOGGLESQ RXRDY_TXKL TX_COMPLT RX_SETUP STALL_SNT NAK_IN NAK_OUT

FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only

TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only

RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only


EPTCLRSTA1_ISOENDPT

UDPHS Endpoint Clear Status Register (endpoint = 1)
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCLRSTA1_ISOENDPT EPTCLRSTA1_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOGGLESQ RXRDY_TXKL TX_COMPLT ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH

TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only


EPTSTA1

UDPHS Endpoint Status Register (endpoint = 1)
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPTSTA1 EPTSTA1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL TOGGLESQ_STA ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT CURBK_CTLDIR BUSY_BANK_STA BYTE_COUNT SHRT_PCKT

FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only

TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only

Enumeration:

0x0 : DATA0

DATA0

0x1 : DATA1

DATA1

0x2 : DATA2

Reserved for High Bandwidth Isochronous Endpoint

0x3 : MDATA

Reserved for High Bandwidth Isochronous Endpoint

End of enumeration elements list.

ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only

TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only

RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only

STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only

NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only

NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only

CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only

BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only

Enumeration:

0x0 : 1BUSYBANK

1 busy bank

0x1 : 2BUSYBANKS

2 busy banks

0x2 : 3BUSYBANKS

3 busy banks

End of enumeration elements list.

BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only

SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only


EPTSTA1_ISOENDPT

UDPHS Endpoint Status Register (endpoint = 1)
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTSTA1_ISOENDPT EPTSTA1_ISOENDPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOGGLESQ_STA ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH CURBK BUSY_BANK_STA BYTE_COUNT SHRT_PCKT

TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only

Enumeration:

0x0 : DATA0

DATA0

0x1 : DATA1

DATA1

0x2 : DATA2

Data2 (only for High Bandwidth Isochronous Endpoint)

0x3 : MDATA

MData (only for High Bandwidth Isochronous Endpoint)

End of enumeration elements list.

ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only

TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only

ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only

ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only

ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only

CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Bank 0 (or single bank)

0x1 : BANK1

Bank 1

0x2 : BANK2

Bank 2

End of enumeration elements list.

BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only

Enumeration:

0x0 : 1BUSYBANK

1 busy bank

0x1 : 2BUSYBANKS

2 busy banks

0x2 : 3BUSYBANKS

3 busy banks

End of enumeration elements list.

BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only

SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only


INTSTA

UDPHS Interrupt Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTA INTSTA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPEED DET_SUSPD MICRO_SOF INT_SOF ENDRESET WAKE_UP ENDOFRSM UPSTR_RES EPT_0 EPT_1 EPT_2 EPT_3 EPT_4 EPT_5 EPT_6 DMA_1 DMA_2 DMA_3 DMA_4 DMA_5 DMA_6

SPEED : Speed Status
bits : 0 - 0 (1 bit)
access : read-only

DET_SUSPD : Suspend Interrupt
bits : 1 - 1 (1 bit)
access : read-only

MICRO_SOF : Micro Start Of Frame Interrupt
bits : 2 - 2 (1 bit)
access : read-only

INT_SOF : Start Of Frame Interrupt
bits : 3 - 3 (1 bit)
access : read-only

ENDRESET : End Of Reset Interrupt
bits : 4 - 4 (1 bit)
access : read-only

WAKE_UP : Wake Up CPU Interrupt
bits : 5 - 5 (1 bit)
access : read-only

ENDOFRSM : End Of Resume Interrupt
bits : 6 - 6 (1 bit)
access : read-only

UPSTR_RES : Upstream Resume Interrupt
bits : 7 - 7 (1 bit)
access : read-only

EPT_0 : Endpoint 0 Interrupt
bits : 8 - 8 (1 bit)
access : read-only

EPT_1 : Endpoint 1 Interrupt
bits : 9 - 9 (1 bit)
access : read-only

EPT_2 : Endpoint 2 Interrupt
bits : 10 - 10 (1 bit)
access : read-only

EPT_3 : Endpoint 3 Interrupt
bits : 11 - 11 (1 bit)
access : read-only

EPT_4 : Endpoint 4 Interrupt
bits : 12 - 12 (1 bit)
access : read-only

EPT_5 : Endpoint 5 Interrupt
bits : 13 - 13 (1 bit)
access : read-only

EPT_6 : Endpoint 6 Interrupt
bits : 14 - 14 (1 bit)
access : read-only

DMA_1 : DMA Channel 1 Interrupt
bits : 25 - 25 (1 bit)
access : read-only

DMA_2 : DMA Channel 2 Interrupt
bits : 26 - 26 (1 bit)
access : read-only

DMA_3 : DMA Channel 3 Interrupt
bits : 27 - 27 (1 bit)
access : read-only

DMA_4 : DMA Channel 4 Interrupt
bits : 28 - 28 (1 bit)
access : read-only

DMA_5 : DMA Channel 5 Interrupt
bits : 29 - 29 (1 bit)
access : read-only

DMA_6 : DMA Channel 6 Interrupt
bits : 30 - 30 (1 bit)
access : read-only


EPTCFG2

UDPHS Endpoint Configuration Register (endpoint = 2)
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPTCFG2 EPTCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_SIZE EPT_DIR EPT_TYPE BK_NUMBER NB_TRANS EPT_MAPD

EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 8

8 bytes

0x1 : 16

16 bytes

0x2 : 32

32 bytes

0x3 : 64

64 bytes

0x4 : 128

128 bytes

0x5 : 256

256 bytes

0x6 : 512

512 bytes

0x7 : 1024

1024 bytes

End of enumeration elements list.

EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write

EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL8

Control endpoint

0x1 : ISO

Isochronous endpoint

0x2 : BULK

Bulk endpoint

0x3 : INT

Interrupt endpoint

End of enumeration elements list.

BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0x0 : 0

Zero bank, the endpoint is not mapped in memory

0x1 : 1

One bank (bank 0)

0x2 : 2

Double bank (Ping-Pong: bank0/bank1)

0x3 : 3

Triple bank (bank0/bank1/bank2)

End of enumeration elements list.

NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write

EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write


EPTCTLENB2

UDPHS Endpoint Control Enable Register (endpoint = 2)
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTLENB2 EPTCTLENB2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLENB2_ISOENDPT

UDPHS Endpoint Control Enable Register (endpoint = 2)
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTLENB2_ISOENDPT EPTCTLENB2_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only

MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLDIS2

UDPHS Endpoint Control Disable Register (endpoint = 2)
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTLDIS2 EPTCTLDIS2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_DISABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLDIS2_ISOENDPT

UDPHS Endpoint Control Disable Register (endpoint = 2)
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTLDIS2_ISOENDPT EPTCTLDIS2_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_DISABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only

MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTL2

UDPHS Endpoint Control Register (endpoint = 2)
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTL2 EPTCTL2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only

AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only

INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only

NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only

ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only

TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only

RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only

STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only

NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only

NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only

BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only

SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only


EPTCTL2_ISOENDPT

UDPHS Endpoint Control Register (endpoint = 2)
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTL2_ISOENDPT EPTCTL2_ISOENDPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only

AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only

INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only

DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only

MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only

ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only

ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only

ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only

BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only

SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only


EPTSETSTA2

UDPHS Endpoint Set Status Register (endpoint = 2)
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTSETSTA2 EPTSETSTA2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL RXRDY_TXKL TXRDY

FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only

RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only

TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only


EPTSETSTA2_ISOENDPT

UDPHS Endpoint Set Status Register (endpoint = 2)
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTSETSTA2_ISOENDPT EPTSETSTA2_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY_TXKL TXRDY_TRER

RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only


EPTCLRSTA2

UDPHS Endpoint Clear Status Register (endpoint = 2)
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCLRSTA2 EPTCLRSTA2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL TOGGLESQ RXRDY_TXKL TX_COMPLT RX_SETUP STALL_SNT NAK_IN NAK_OUT

FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only

TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only

RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only


EPTCLRSTA2_ISOENDPT

UDPHS Endpoint Clear Status Register (endpoint = 2)
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCLRSTA2_ISOENDPT EPTCLRSTA2_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOGGLESQ RXRDY_TXKL TX_COMPLT ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH

TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only


EPTSTA2

UDPHS Endpoint Status Register (endpoint = 2)
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPTSTA2 EPTSTA2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL TOGGLESQ_STA ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT CURBK_CTLDIR BUSY_BANK_STA BYTE_COUNT SHRT_PCKT

FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only

TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only

Enumeration:

0x0 : DATA0

DATA0

0x1 : DATA1

DATA1

0x2 : DATA2

Reserved for High Bandwidth Isochronous Endpoint

0x3 : MDATA

Reserved for High Bandwidth Isochronous Endpoint

End of enumeration elements list.

ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only

TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only

RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only

STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only

NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only

NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only

CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only

BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only

Enumeration:

0x0 : 1BUSYBANK

1 busy bank

0x1 : 2BUSYBANKS

2 busy banks

0x2 : 3BUSYBANKS

3 busy banks

End of enumeration elements list.

BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only

SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only


EPTSTA2_ISOENDPT

UDPHS Endpoint Status Register (endpoint = 2)
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTSTA2_ISOENDPT EPTSTA2_ISOENDPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOGGLESQ_STA ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH CURBK BUSY_BANK_STA BYTE_COUNT SHRT_PCKT

TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only

Enumeration:

0x0 : DATA0

DATA0

0x1 : DATA1

DATA1

0x2 : DATA2

Data2 (only for High Bandwidth Isochronous Endpoint)

0x3 : MDATA

MData (only for High Bandwidth Isochronous Endpoint)

End of enumeration elements list.

ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only

TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only

ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only

ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only

ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only

CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Bank 0 (or single bank)

0x1 : BANK1

Bank 1

0x2 : BANK2

Bank 2

End of enumeration elements list.

BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only

Enumeration:

0x0 : 1BUSYBANK

1 busy bank

0x1 : 2BUSYBANKS

2 busy banks

0x2 : 3BUSYBANKS

3 busy banks

End of enumeration elements list.

BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only

SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only


EPTCFG3

UDPHS Endpoint Configuration Register (endpoint = 3)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPTCFG3 EPTCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_SIZE EPT_DIR EPT_TYPE BK_NUMBER NB_TRANS EPT_MAPD

EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 8

8 bytes

0x1 : 16

16 bytes

0x2 : 32

32 bytes

0x3 : 64

64 bytes

0x4 : 128

128 bytes

0x5 : 256

256 bytes

0x6 : 512

512 bytes

0x7 : 1024

1024 bytes

End of enumeration elements list.

EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write

EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL8

Control endpoint

0x1 : ISO

Isochronous endpoint

0x2 : BULK

Bulk endpoint

0x3 : INT

Interrupt endpoint

End of enumeration elements list.

BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0x0 : 0

Zero bank, the endpoint is not mapped in memory

0x1 : 1

One bank (bank 0)

0x2 : 2

Double bank (Ping-Pong: bank0/bank1)

0x3 : 3

Triple bank (bank0/bank1/bank2)

End of enumeration elements list.

NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write

EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write


EPTCTLENB3

UDPHS Endpoint Control Enable Register (endpoint = 3)
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTLENB3 EPTCTLENB3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLENB3_ISOENDPT

UDPHS Endpoint Control Enable Register (endpoint = 3)
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTLENB3_ISOENDPT EPTCTLENB3_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only

MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLDIS3

UDPHS Endpoint Control Disable Register (endpoint = 3)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTLDIS3 EPTCTLDIS3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_DISABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLDIS3_ISOENDPT

UDPHS Endpoint Control Disable Register (endpoint = 3)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTLDIS3_ISOENDPT EPTCTLDIS3_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_DISABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only

MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTL3

UDPHS Endpoint Control Register (endpoint = 3)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTL3 EPTCTL3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only

AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only

INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only

NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only

ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only

TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only

RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only

STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only

NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only

NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only

BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only

SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only


EPTCTL3_ISOENDPT

UDPHS Endpoint Control Register (endpoint = 3)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTL3_ISOENDPT EPTCTL3_ISOENDPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only

AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only

INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only

DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only

MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only

ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only

ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only

ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only

BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only

SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only


EPTSETSTA3

UDPHS Endpoint Set Status Register (endpoint = 3)
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTSETSTA3 EPTSETSTA3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL RXRDY_TXKL TXRDY

FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only

RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only

TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only


EPTSETSTA3_ISOENDPT

UDPHS Endpoint Set Status Register (endpoint = 3)
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTSETSTA3_ISOENDPT EPTSETSTA3_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY_TXKL TXRDY_TRER

RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only


EPTCLRSTA3

UDPHS Endpoint Clear Status Register (endpoint = 3)
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCLRSTA3 EPTCLRSTA3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL TOGGLESQ RXRDY_TXKL TX_COMPLT RX_SETUP STALL_SNT NAK_IN NAK_OUT

FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only

TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only

RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only


EPTCLRSTA3_ISOENDPT

UDPHS Endpoint Clear Status Register (endpoint = 3)
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCLRSTA3_ISOENDPT EPTCLRSTA3_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOGGLESQ RXRDY_TXKL TX_COMPLT ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH

TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only


EPTSTA3

UDPHS Endpoint Status Register (endpoint = 3)
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPTSTA3 EPTSTA3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL TOGGLESQ_STA ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT CURBK_CTLDIR BUSY_BANK_STA BYTE_COUNT SHRT_PCKT

FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only

TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only

Enumeration:

0x0 : DATA0

DATA0

0x1 : DATA1

DATA1

0x2 : DATA2

Reserved for High Bandwidth Isochronous Endpoint

0x3 : MDATA

Reserved for High Bandwidth Isochronous Endpoint

End of enumeration elements list.

ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only

TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only

RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only

STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only

NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only

NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only

CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only

BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only

Enumeration:

0x0 : 1BUSYBANK

1 busy bank

0x1 : 2BUSYBANKS

2 busy banks

0x2 : 3BUSYBANKS

3 busy banks

End of enumeration elements list.

BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only

SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only


EPTSTA3_ISOENDPT

UDPHS Endpoint Status Register (endpoint = 3)
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTSTA3_ISOENDPT EPTSTA3_ISOENDPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOGGLESQ_STA ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH CURBK BUSY_BANK_STA BYTE_COUNT SHRT_PCKT

TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only

Enumeration:

0x0 : DATA0

DATA0

0x1 : DATA1

DATA1

0x2 : DATA2

Data2 (only for High Bandwidth Isochronous Endpoint)

0x3 : MDATA

MData (only for High Bandwidth Isochronous Endpoint)

End of enumeration elements list.

ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only

TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only

ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only

ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only

ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only

CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Bank 0 (or single bank)

0x1 : BANK1

Bank 1

0x2 : BANK2

Bank 2

End of enumeration elements list.

BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only

Enumeration:

0x0 : 1BUSYBANK

1 busy bank

0x1 : 2BUSYBANKS

2 busy banks

0x2 : 3BUSYBANKS

3 busy banks

End of enumeration elements list.

BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only

SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only


CLRINT

UDPHS Clear Interrupt Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CLRINT CLRINT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DET_SUSPD MICRO_SOF INT_SOF ENDRESET WAKE_UP ENDOFRSM UPSTR_RES

DET_SUSPD : Suspend Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

MICRO_SOF : Micro Start Of Frame Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

INT_SOF : Start Of Frame Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

ENDRESET : End Of Reset Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

WAKE_UP : Wake Up CPU Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

ENDOFRSM : End Of Resume Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

UPSTR_RES : Upstream Resume Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


EPTCFG4

UDPHS Endpoint Configuration Register (endpoint = 4)
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPTCFG4 EPTCFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_SIZE EPT_DIR EPT_TYPE BK_NUMBER NB_TRANS EPT_MAPD

EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 8

8 bytes

0x1 : 16

16 bytes

0x2 : 32

32 bytes

0x3 : 64

64 bytes

0x4 : 128

128 bytes

0x5 : 256

256 bytes

0x6 : 512

512 bytes

0x7 : 1024

1024 bytes

End of enumeration elements list.

EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write

EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL8

Control endpoint

0x1 : ISO

Isochronous endpoint

0x2 : BULK

Bulk endpoint

0x3 : INT

Interrupt endpoint

End of enumeration elements list.

BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0x0 : 0

Zero bank, the endpoint is not mapped in memory

0x1 : 1

One bank (bank 0)

0x2 : 2

Double bank (Ping-Pong: bank0/bank1)

0x3 : 3

Triple bank (bank0/bank1/bank2)

End of enumeration elements list.

NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write

EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write


EPTCTLENB4

UDPHS Endpoint Control Enable Register (endpoint = 4)
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTLENB4 EPTCTLENB4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLENB4_ISOENDPT

UDPHS Endpoint Control Enable Register (endpoint = 4)
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTLENB4_ISOENDPT EPTCTLENB4_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only

MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLDIS4

UDPHS Endpoint Control Disable Register (endpoint = 4)
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTLDIS4 EPTCTLDIS4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_DISABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLDIS4_ISOENDPT

UDPHS Endpoint Control Disable Register (endpoint = 4)
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTLDIS4_ISOENDPT EPTCTLDIS4_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_DISABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only

MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTL4

UDPHS Endpoint Control Register (endpoint = 4)
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTL4 EPTCTL4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only

AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only

INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only

NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only

ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only

TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only

RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only

STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only

NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only

NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only

BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only

SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only


EPTCTL4_ISOENDPT

UDPHS Endpoint Control Register (endpoint = 4)
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTL4_ISOENDPT EPTCTL4_ISOENDPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only

AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only

INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only

DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only

MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only

ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only

ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only

ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only

BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only

SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only


EPTSETSTA4

UDPHS Endpoint Set Status Register (endpoint = 4)
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTSETSTA4 EPTSETSTA4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL RXRDY_TXKL TXRDY

FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only

RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only

TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only


EPTSETSTA4_ISOENDPT

UDPHS Endpoint Set Status Register (endpoint = 4)
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTSETSTA4_ISOENDPT EPTSETSTA4_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY_TXKL TXRDY_TRER

RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only


EPTCLRSTA4

UDPHS Endpoint Clear Status Register (endpoint = 4)
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCLRSTA4 EPTCLRSTA4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL TOGGLESQ RXRDY_TXKL TX_COMPLT RX_SETUP STALL_SNT NAK_IN NAK_OUT

FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only

TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only

RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only


EPTCLRSTA4_ISOENDPT

UDPHS Endpoint Clear Status Register (endpoint = 4)
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCLRSTA4_ISOENDPT EPTCLRSTA4_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOGGLESQ RXRDY_TXKL TX_COMPLT ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH

TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only


EPTSTA4

UDPHS Endpoint Status Register (endpoint = 4)
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPTSTA4 EPTSTA4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL TOGGLESQ_STA ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT CURBK_CTLDIR BUSY_BANK_STA BYTE_COUNT SHRT_PCKT

FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only

TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only

Enumeration:

0x0 : DATA0

DATA0

0x1 : DATA1

DATA1

0x2 : DATA2

Reserved for High Bandwidth Isochronous Endpoint

0x3 : MDATA

Reserved for High Bandwidth Isochronous Endpoint

End of enumeration elements list.

ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only

TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only

RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only

STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only

NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only

NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only

CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only

BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only

Enumeration:

0x0 : 1BUSYBANK

1 busy bank

0x1 : 2BUSYBANKS

2 busy banks

0x2 : 3BUSYBANKS

3 busy banks

End of enumeration elements list.

BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only

SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only


EPTSTA4_ISOENDPT

UDPHS Endpoint Status Register (endpoint = 4)
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTSTA4_ISOENDPT EPTSTA4_ISOENDPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOGGLESQ_STA ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH CURBK BUSY_BANK_STA BYTE_COUNT SHRT_PCKT

TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only

Enumeration:

0x0 : DATA0

DATA0

0x1 : DATA1

DATA1

0x2 : DATA2

Data2 (only for High Bandwidth Isochronous Endpoint)

0x3 : MDATA

MData (only for High Bandwidth Isochronous Endpoint)

End of enumeration elements list.

ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only

TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only

ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only

ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only

ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only

CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Bank 0 (or single bank)

0x1 : BANK1

Bank 1

0x2 : BANK2

Bank 2

End of enumeration elements list.

BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only

Enumeration:

0x0 : 1BUSYBANK

1 busy bank

0x1 : 2BUSYBANKS

2 busy banks

0x2 : 3BUSYBANKS

3 busy banks

End of enumeration elements list.

BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only

SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only


EPTCFG5

UDPHS Endpoint Configuration Register (endpoint = 5)
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPTCFG5 EPTCFG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_SIZE EPT_DIR EPT_TYPE BK_NUMBER NB_TRANS EPT_MAPD

EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 8

8 bytes

0x1 : 16

16 bytes

0x2 : 32

32 bytes

0x3 : 64

64 bytes

0x4 : 128

128 bytes

0x5 : 256

256 bytes

0x6 : 512

512 bytes

0x7 : 1024

1024 bytes

End of enumeration elements list.

EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write

EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL8

Control endpoint

0x1 : ISO

Isochronous endpoint

0x2 : BULK

Bulk endpoint

0x3 : INT

Interrupt endpoint

End of enumeration elements list.

BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0x0 : 0

Zero bank, the endpoint is not mapped in memory

0x1 : 1

One bank (bank 0)

0x2 : 2

Double bank (Ping-Pong: bank0/bank1)

0x3 : 3

Triple bank (bank0/bank1/bank2)

End of enumeration elements list.

NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write

EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write


EPTCTLENB5

UDPHS Endpoint Control Enable Register (endpoint = 5)
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTLENB5 EPTCTLENB5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLENB5_ISOENDPT

UDPHS Endpoint Control Enable Register (endpoint = 5)
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTLENB5_ISOENDPT EPTCTLENB5_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only

MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLDIS5

UDPHS Endpoint Control Disable Register (endpoint = 5)
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTLDIS5 EPTCTLDIS5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_DISABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLDIS5_ISOENDPT

UDPHS Endpoint Control Disable Register (endpoint = 5)
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTLDIS5_ISOENDPT EPTCTLDIS5_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_DISABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only

MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTL5

UDPHS Endpoint Control Register (endpoint = 5)
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTL5 EPTCTL5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only

AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only

INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only

NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only

ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only

TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only

RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only

STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only

NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only

NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only

BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only

SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only


EPTCTL5_ISOENDPT

UDPHS Endpoint Control Register (endpoint = 5)
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTL5_ISOENDPT EPTCTL5_ISOENDPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only

AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only

INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only

DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only

MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only

ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only

ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only

ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only

BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only

SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only


EPTSETSTA5

UDPHS Endpoint Set Status Register (endpoint = 5)
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTSETSTA5 EPTSETSTA5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL RXRDY_TXKL TXRDY

FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only

RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only

TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only


EPTSETSTA5_ISOENDPT

UDPHS Endpoint Set Status Register (endpoint = 5)
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTSETSTA5_ISOENDPT EPTSETSTA5_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY_TXKL TXRDY_TRER

RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only


EPTCLRSTA5

UDPHS Endpoint Clear Status Register (endpoint = 5)
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCLRSTA5 EPTCLRSTA5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL TOGGLESQ RXRDY_TXKL TX_COMPLT RX_SETUP STALL_SNT NAK_IN NAK_OUT

FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only

TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only

RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only


EPTCLRSTA5_ISOENDPT

UDPHS Endpoint Clear Status Register (endpoint = 5)
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCLRSTA5_ISOENDPT EPTCLRSTA5_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOGGLESQ RXRDY_TXKL TX_COMPLT ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH

TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only


EPTSTA5

UDPHS Endpoint Status Register (endpoint = 5)
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPTSTA5 EPTSTA5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL TOGGLESQ_STA ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT CURBK_CTLDIR BUSY_BANK_STA BYTE_COUNT SHRT_PCKT

FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only

TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only

Enumeration:

0x0 : DATA0

DATA0

0x1 : DATA1

DATA1

0x2 : DATA2

Reserved for High Bandwidth Isochronous Endpoint

0x3 : MDATA

Reserved for High Bandwidth Isochronous Endpoint

End of enumeration elements list.

ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only

TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only

RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only

STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only

NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only

NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only

CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only

BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only

Enumeration:

0x0 : 1BUSYBANK

1 busy bank

0x1 : 2BUSYBANKS

2 busy banks

0x2 : 3BUSYBANKS

3 busy banks

End of enumeration elements list.

BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only

SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only


EPTSTA5_ISOENDPT

UDPHS Endpoint Status Register (endpoint = 5)
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTSTA5_ISOENDPT EPTSTA5_ISOENDPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOGGLESQ_STA ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH CURBK BUSY_BANK_STA BYTE_COUNT SHRT_PCKT

TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only

Enumeration:

0x0 : DATA0

DATA0

0x1 : DATA1

DATA1

0x2 : DATA2

Data2 (only for High Bandwidth Isochronous Endpoint)

0x3 : MDATA

MData (only for High Bandwidth Isochronous Endpoint)

End of enumeration elements list.

ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only

TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only

ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only

ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only

ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only

CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Bank 0 (or single bank)

0x1 : BANK1

Bank 1

0x2 : BANK2

Bank 2

End of enumeration elements list.

BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only

Enumeration:

0x0 : 1BUSYBANK

1 busy bank

0x1 : 2BUSYBANKS

2 busy banks

0x2 : 3BUSYBANKS

3 busy banks

End of enumeration elements list.

BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only

SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only


EPTRST

UDPHS Endpoints Reset Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTRST EPTRST write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_0 EPT_1 EPT_2 EPT_3 EPT_4 EPT_5 EPT_6

EPT_0 : Endpoint 0 Reset
bits : 0 - 0 (1 bit)
access : write-only

EPT_1 : Endpoint 1 Reset
bits : 1 - 1 (1 bit)
access : write-only

EPT_2 : Endpoint 2 Reset
bits : 2 - 2 (1 bit)
access : write-only

EPT_3 : Endpoint 3 Reset
bits : 3 - 3 (1 bit)
access : write-only

EPT_4 : Endpoint 4 Reset
bits : 4 - 4 (1 bit)
access : write-only

EPT_5 : Endpoint 5 Reset
bits : 5 - 5 (1 bit)
access : write-only

EPT_6 : Endpoint 6 Reset
bits : 6 - 6 (1 bit)
access : write-only


EPTCFG6

UDPHS Endpoint Configuration Register (endpoint = 6)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPTCFG6 EPTCFG6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_SIZE EPT_DIR EPT_TYPE BK_NUMBER NB_TRANS EPT_MAPD

EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 8

8 bytes

0x1 : 16

16 bytes

0x2 : 32

32 bytes

0x3 : 64

64 bytes

0x4 : 128

128 bytes

0x5 : 256

256 bytes

0x6 : 512

512 bytes

0x7 : 1024

1024 bytes

End of enumeration elements list.

EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write

EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL8

Control endpoint

0x1 : ISO

Isochronous endpoint

0x2 : BULK

Bulk endpoint

0x3 : INT

Interrupt endpoint

End of enumeration elements list.

BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0x0 : 0

Zero bank, the endpoint is not mapped in memory

0x1 : 1

One bank (bank 0)

0x2 : 2

Double bank (Ping-Pong: bank0/bank1)

0x3 : 3

Triple bank (bank0/bank1/bank2)

End of enumeration elements list.

NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write

EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write


EPTCTLENB6

UDPHS Endpoint Control Enable Register (endpoint = 6)
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTLENB6 EPTCTLENB6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLENB6_ISOENDPT

UDPHS Endpoint Control Enable Register (endpoint = 6)
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTLENB6_ISOENDPT EPTCTLENB6_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only

MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLDIS6

UDPHS Endpoint Control Disable Register (endpoint = 6)
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTLDIS6 EPTCTLDIS6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_DISABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTLDIS6_ISOENDPT

UDPHS Endpoint Control Disable Register (endpoint = 6)
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTLDIS6_ISOENDPT EPTCTLDIS6_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_DISABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only

AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only

INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only

DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only

MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only

ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


EPTCTL6

UDPHS Endpoint Control Register (endpoint = 6)
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPTCTL6 EPTCTL6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA NYET_DIS ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only

AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only

INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only

NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only

ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only

TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only

RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only

STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only

NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only

NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only

BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only

SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only


EPTCTL6_ISOENDPT

UDPHS Endpoint Control Register (endpoint = 6)
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCTL6_ISOENDPT EPTCTL6_ISOENDPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPT_ENABL AUTO_VALID INTDIS_DMA DATAX_RX MDATA_RX ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH BUSY_BANK SHRT_PCKT

EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only

AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only

INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only

DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only

MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only

ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only

TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only

ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only

ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only

ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only

BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only

SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only


EPTSETSTA6

UDPHS Endpoint Set Status Register (endpoint = 6)
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTSETSTA6 EPTSETSTA6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL RXRDY_TXKL TXRDY

FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only

RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only

TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only


EPTSETSTA6_ISOENDPT

UDPHS Endpoint Set Status Register (endpoint = 6)
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTSETSTA6_ISOENDPT EPTSETSTA6_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY_TXKL TXRDY_TRER

RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only

TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only


EPTCLRSTA6

UDPHS Endpoint Clear Status Register (endpoint = 6)
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPTCLRSTA6 EPTCLRSTA6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL TOGGLESQ RXRDY_TXKL TX_COMPLT RX_SETUP STALL_SNT NAK_IN NAK_OUT

FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only

TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only

RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only

STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only

NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only

NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only


EPTCLRSTA6_ISOENDPT

UDPHS Endpoint Clear Status Register (endpoint = 6)
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTCLRSTA6_ISOENDPT EPTCLRSTA6_ISOENDPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOGGLESQ RXRDY_TXKL TX_COMPLT ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH

TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only

RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only

TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only

ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only

ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only

ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only


EPTSTA6

UDPHS Endpoint Status Register (endpoint = 6)
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPTSTA6 EPTSTA6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRCESTALL TOGGLESQ_STA ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY RX_SETUP STALL_SNT NAK_IN NAK_OUT CURBK_CTLDIR BUSY_BANK_STA BYTE_COUNT SHRT_PCKT

FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only

TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only

Enumeration:

0x0 : DATA0

DATA0

0x1 : DATA1

DATA1

0x2 : DATA2

Reserved for High Bandwidth Isochronous Endpoint

0x3 : MDATA

Reserved for High Bandwidth Isochronous Endpoint

End of enumeration elements list.

ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only

TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only

RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only

STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only

NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only

NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only

CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only

BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only

Enumeration:

0x0 : 1BUSYBANK

1 busy bank

0x1 : 2BUSYBANKS

2 busy banks

0x2 : 3BUSYBANKS

3 busy banks

End of enumeration elements list.

BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only

SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only


EPTSTA6_ISOENDPT

UDPHS Endpoint Status Register (endpoint = 6)
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0

EPTSTA6_ISOENDPT EPTSTA6_ISOENDPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOGGLESQ_STA ERR_OVFLW RXRDY_TXKL TX_COMPLT TXRDY_TRER ERR_FL_ISO ERR_CRC_NTR ERR_FLUSH CURBK BUSY_BANK_STA BYTE_COUNT SHRT_PCKT

TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only

Enumeration:

0x0 : DATA0

DATA0

0x1 : DATA1

DATA1

0x2 : DATA2

Data2 (only for High Bandwidth Isochronous Endpoint)

0x3 : MDATA

MData (only for High Bandwidth Isochronous Endpoint)

End of enumeration elements list.

ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only

RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only

TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only

TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only

ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only

ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only

ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only

CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Bank 0 (or single bank)

0x1 : BANK1

Bank 1

0x2 : BANK2

Bank 2

End of enumeration elements list.

BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only

Enumeration:

0x0 : 1BUSYBANK

1 busy bank

0x1 : 2BUSYBANKS

2 busy banks

0x2 : 3BUSYBANKS

3 busy banks

End of enumeration elements list.

BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only

SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only


DMANXTDSC0

UDPHS DMA Next Descriptor Address Register (channel = 0)
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMANXTDSC0 DMANXTDSC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NXT_DSC_ADD

NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write


DMAADDRESS0

UDPHS DMA Channel Address Register (channel = 0)
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAADDRESS0 DMAADDRESS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFF_ADD

BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write


DMACONTROL0

UDPHS DMA Channel Control Register (channel = 0)
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACONTROL0 DMACONTROL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB LDNXT_DSC END_TR_EN END_B_EN END_TR_IT END_BUFFIT DESC_LD_IT BURST_LCK BUFF_LENGTH

CHANN_ENB : (Channel Enable Command)
bits : 0 - 0 (1 bit)
access : read-write

LDNXT_DSC : Load Next Channel Transfer Descriptor Enable (Command)
bits : 1 - 1 (1 bit)
access : read-write

END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write

END_B_EN : End of Buffer Enable (Control)
bits : 3 - 3 (1 bit)
access : read-write

END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write

BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write


DMASTATUS0

UDPHS DMA Channel Status Register (channel = 0)
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMASTATUS0 DMASTATUS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB CHANN_ACT END_TR_ST END_BF_ST DESC_LDST BUFF_COUNT

CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write

CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write

END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write

END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write

DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write

BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write


DMANXTDSC1

UDPHS DMA Next Descriptor Address Register (channel = 1)
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMANXTDSC1 DMANXTDSC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NXT_DSC_ADD

NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write


DMAADDRESS1

UDPHS DMA Channel Address Register (channel = 1)
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAADDRESS1 DMAADDRESS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFF_ADD

BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write


DMACONTROL1

UDPHS DMA Channel Control Register (channel = 1)
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACONTROL1 DMACONTROL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB LDNXT_DSC END_TR_EN END_B_EN END_TR_IT END_BUFFIT DESC_LD_IT BURST_LCK BUFF_LENGTH

CHANN_ENB : (Channel Enable Command)
bits : 0 - 0 (1 bit)
access : read-write

LDNXT_DSC : Load Next Channel Transfer Descriptor Enable (Command)
bits : 1 - 1 (1 bit)
access : read-write

END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write

END_B_EN : End of Buffer Enable (Control)
bits : 3 - 3 (1 bit)
access : read-write

END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write

BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write


DMASTATUS1

UDPHS DMA Channel Status Register (channel = 1)
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMASTATUS1 DMASTATUS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB CHANN_ACT END_TR_ST END_BF_ST DESC_LDST BUFF_COUNT

CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write

CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write

END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write

END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write

DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write

BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write


DMANXTDSC2

UDPHS DMA Next Descriptor Address Register (channel = 2)
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMANXTDSC2 DMANXTDSC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NXT_DSC_ADD

NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write


DMAADDRESS2

UDPHS DMA Channel Address Register (channel = 2)
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAADDRESS2 DMAADDRESS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFF_ADD

BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write


DMACONTROL2

UDPHS DMA Channel Control Register (channel = 2)
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACONTROL2 DMACONTROL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB LDNXT_DSC END_TR_EN END_B_EN END_TR_IT END_BUFFIT DESC_LD_IT BURST_LCK BUFF_LENGTH

CHANN_ENB : (Channel Enable Command)
bits : 0 - 0 (1 bit)
access : read-write

LDNXT_DSC : Load Next Channel Transfer Descriptor Enable (Command)
bits : 1 - 1 (1 bit)
access : read-write

END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write

END_B_EN : End of Buffer Enable (Control)
bits : 3 - 3 (1 bit)
access : read-write

END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write

BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write


DMASTATUS2

UDPHS DMA Channel Status Register (channel = 2)
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMASTATUS2 DMASTATUS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB CHANN_ACT END_TR_ST END_BF_ST DESC_LDST BUFF_COUNT

CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write

CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write

END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write

END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write

DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write

BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write


DMANXTDSC3

UDPHS DMA Next Descriptor Address Register (channel = 3)
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMANXTDSC3 DMANXTDSC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NXT_DSC_ADD

NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write


DMAADDRESS3

UDPHS DMA Channel Address Register (channel = 3)
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAADDRESS3 DMAADDRESS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFF_ADD

BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write


DMACONTROL3

UDPHS DMA Channel Control Register (channel = 3)
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACONTROL3 DMACONTROL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB LDNXT_DSC END_TR_EN END_B_EN END_TR_IT END_BUFFIT DESC_LD_IT BURST_LCK BUFF_LENGTH

CHANN_ENB : (Channel Enable Command)
bits : 0 - 0 (1 bit)
access : read-write

LDNXT_DSC : Load Next Channel Transfer Descriptor Enable (Command)
bits : 1 - 1 (1 bit)
access : read-write

END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write

END_B_EN : End of Buffer Enable (Control)
bits : 3 - 3 (1 bit)
access : read-write

END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write

BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write


DMASTATUS3

UDPHS DMA Channel Status Register (channel = 3)
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMASTATUS3 DMASTATUS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB CHANN_ACT END_TR_ST END_BF_ST DESC_LDST BUFF_COUNT

CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write

CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write

END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write

END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write

DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write

BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write


DMANXTDSC4

UDPHS DMA Next Descriptor Address Register (channel = 4)
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMANXTDSC4 DMANXTDSC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NXT_DSC_ADD

NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write


DMAADDRESS4

UDPHS DMA Channel Address Register (channel = 4)
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAADDRESS4 DMAADDRESS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFF_ADD

BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write


DMACONTROL4

UDPHS DMA Channel Control Register (channel = 4)
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACONTROL4 DMACONTROL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB LDNXT_DSC END_TR_EN END_B_EN END_TR_IT END_BUFFIT DESC_LD_IT BURST_LCK BUFF_LENGTH

CHANN_ENB : (Channel Enable Command)
bits : 0 - 0 (1 bit)
access : read-write

LDNXT_DSC : Load Next Channel Transfer Descriptor Enable (Command)
bits : 1 - 1 (1 bit)
access : read-write

END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write

END_B_EN : End of Buffer Enable (Control)
bits : 3 - 3 (1 bit)
access : read-write

END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write

BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write


DMASTATUS4

UDPHS DMA Channel Status Register (channel = 4)
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMASTATUS4 DMASTATUS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB CHANN_ACT END_TR_ST END_BF_ST DESC_LDST BUFF_COUNT

CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write

CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write

END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write

END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write

DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write

BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write


DMANXTDSC5

UDPHS DMA Next Descriptor Address Register (channel = 5)
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMANXTDSC5 DMANXTDSC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NXT_DSC_ADD

NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write


DMAADDRESS5

UDPHS DMA Channel Address Register (channel = 5)
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAADDRESS5 DMAADDRESS5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFF_ADD

BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write


DMACONTROL5

UDPHS DMA Channel Control Register (channel = 5)
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACONTROL5 DMACONTROL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB LDNXT_DSC END_TR_EN END_B_EN END_TR_IT END_BUFFIT DESC_LD_IT BURST_LCK BUFF_LENGTH

CHANN_ENB : (Channel Enable Command)
bits : 0 - 0 (1 bit)
access : read-write

LDNXT_DSC : Load Next Channel Transfer Descriptor Enable (Command)
bits : 1 - 1 (1 bit)
access : read-write

END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write

END_B_EN : End of Buffer Enable (Control)
bits : 3 - 3 (1 bit)
access : read-write

END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write

BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write


DMASTATUS5

UDPHS DMA Channel Status Register (channel = 5)
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMASTATUS5 DMASTATUS5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB CHANN_ACT END_TR_ST END_BF_ST DESC_LDST BUFF_COUNT

CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write

CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write

END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write

END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write

DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write

BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write


FNUM

UDPHS Frame Number Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FNUM FNUM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MICRO_FRAME_NUM FRAME_NUMBER FNUM_ERR

MICRO_FRAME_NUM : Microframe Number
bits : 0 - 2 (3 bit)
access : read-only

FRAME_NUMBER : Frame Number as defined in the Packet Field Formats
bits : 3 - 13 (11 bit)
access : read-only

FNUM_ERR : Frame Number CRC Error
bits : 31 - 31 (1 bit)
access : read-only


TST

UDPHS Test Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TST TST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPEED_CFG TST_J TST_K TST_PKT OPMODE2

SPEED_CFG : Speed Configuration
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : NORMAL

Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode

0x2 : HIGH_SPEED

Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose.

0x3 : FULL_SPEED

Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake.

End of enumeration elements list.

TST_J : Test J Mode
bits : 2 - 2 (1 bit)
access : read-write

TST_K : Test K Mode
bits : 3 - 3 (1 bit)
access : read-write

TST_PKT : Test Packet Mode
bits : 4 - 4 (1 bit)
access : read-write

OPMODE2 : OpMode2
bits : 5 - 5 (1 bit)
access : read-write



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