\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Network Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LB : LoopBack
bits : 0 - 0 (1 bit)
access : read-write
LLB : Loopback local
bits : 1 - 1 (1 bit)
access : read-write
RE : Receive enable
bits : 2 - 2 (1 bit)
access : read-write
TE : Transmit enable
bits : 3 - 3 (1 bit)
access : read-write
MPE : Management port enable
bits : 4 - 4 (1 bit)
access : read-write
CLRSTAT : Clear statistics registers
bits : 5 - 5 (1 bit)
access : read-write
INCSTAT : Increment statistics registers
bits : 6 - 6 (1 bit)
access : read-write
WESTAT : Write enable for statistics registers
bits : 7 - 7 (1 bit)
access : read-write
BP : Back pressure
bits : 8 - 8 (1 bit)
access : read-write
TSTART : Start transmission
bits : 9 - 9 (1 bit)
access : read-write
THALT : Transmit halt
bits : 10 - 10 (1 bit)
access : read-write
Transmit Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBR : Used Bit Read
bits : 0 - 0 (1 bit)
access : read-write
COL : Collision Occurred
bits : 1 - 1 (1 bit)
access : read-write
RLE : Retry Limit exceeded
bits : 2 - 2 (1 bit)
access : read-write
TGO : Transmit Go
bits : 3 - 3 (1 bit)
access : read-write
BEX : Buffers exhausted mid frame
bits : 4 - 4 (1 bit)
access : read-write
COMP : Transmit Complete
bits : 5 - 5 (1 bit)
access : read-write
UND : Transmit Underrun
bits : 6 - 6 (1 bit)
access : read-write
Receive Buffer Queue Pointer Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Receive buffer queue pointer address
bits : 2 - 31 (30 bit)
access : read-write
Transmit Buffer Queue Pointer Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Transmit buffer queue pointer address
bits : 2 - 31 (30 bit)
access : read-write
Receive Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNA : Buffer Not Available
bits : 0 - 0 (1 bit)
access : read-write
REC : Frame Received
bits : 1 - 1 (1 bit)
access : read-write
OVR : Receive Overrun
bits : 2 - 2 (1 bit)
access : read-write
Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFD : Management Frame Done
bits : 0 - 0 (1 bit)
access : read-write
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : read-write
RXUBR : Receive Used Bit Read
bits : 2 - 2 (1 bit)
access : read-write
TXUBR : Transmit Used Bit Read
bits : 3 - 3 (1 bit)
access : read-write
TUND : Ethernet Transmit Buffer Underrun
bits : 4 - 4 (1 bit)
access : read-write
RLE : Retry Limit Exceeded
bits : 5 - 5 (1 bit)
access : read-write
TXERR : Transmit Error
bits : 6 - 6 (1 bit)
access : read-write
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : read-write
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : read-write
HRESP : Hresp not OK
bits : 11 - 11 (1 bit)
access : read-write
PFR : Pause Frame Received
bits : 12 - 12 (1 bit)
access : read-write
PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
access : read-write
Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MFD : Management Frame sent
bits : 0 - 0 (1 bit)
access : write-only
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : write-only
RXUBR : Receive Used Bit Read
bits : 2 - 2 (1 bit)
access : write-only
TXUBR : Transmit Used Bit Read
bits : 3 - 3 (1 bit)
access : write-only
TUND : Ethernet Transmit Buffer Underrun
bits : 4 - 4 (1 bit)
access : write-only
RLE : Retry Limit Exceeded
bits : 5 - 5 (1 bit)
access : write-only
TXERR :
bits : 6 - 6 (1 bit)
access : write-only
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : write-only
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : write-only
HRESP : Hresp not OK
bits : 11 - 11 (1 bit)
access : write-only
PFR : Pause Frame Received
bits : 12 - 12 (1 bit)
access : write-only
PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
access : write-only
Interrupt Disable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MFD : Management Frame sent
bits : 0 - 0 (1 bit)
access : write-only
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : write-only
RXUBR : Receive Used Bit Read
bits : 2 - 2 (1 bit)
access : write-only
TXUBR : Transmit Used Bit Read
bits : 3 - 3 (1 bit)
access : write-only
TUND : Ethernet Transmit Buffer Underrun
bits : 4 - 4 (1 bit)
access : write-only
RLE : Retry Limit Exceeded
bits : 5 - 5 (1 bit)
access : write-only
TXERR :
bits : 6 - 6 (1 bit)
access : write-only
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : write-only
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : write-only
HRESP : Hresp not OK
bits : 11 - 11 (1 bit)
access : write-only
PFR : Pause Frame Received
bits : 12 - 12 (1 bit)
access : write-only
PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
access : write-only
Interrupt Mask Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFD : Management Frame sent
bits : 0 - 0 (1 bit)
access : read-only
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : read-only
RXUBR : Receive Used Bit Read
bits : 2 - 2 (1 bit)
access : read-only
TXUBR : Transmit Used Bit Read
bits : 3 - 3 (1 bit)
access : read-only
TUND : Ethernet Transmit Buffer Underrun
bits : 4 - 4 (1 bit)
access : read-only
RLE : Retry Limit Exceeded
bits : 5 - 5 (1 bit)
access : read-only
TXERR :
bits : 6 - 6 (1 bit)
access : read-only
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : read-only
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : read-only
HRESP : Hresp not OK
bits : 11 - 11 (1 bit)
access : read-only
PFR : Pause Frame Received
bits : 12 - 12 (1 bit)
access : read-only
PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
access : read-only
Phy Maintenance Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA :
bits : 0 - 15 (16 bit)
access : read-write
CODE :
bits : 16 - 17 (2 bit)
access : read-write
REGA : Register Address
bits : 18 - 22 (5 bit)
access : read-write
PHYA : PHY Address
bits : 23 - 27 (5 bit)
access : read-write
RW : Read-write
bits : 28 - 29 (2 bit)
access : read-write
SOF : Start of frame
bits : 30 - 31 (2 bit)
access : read-write
Pause Time Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTIME : Pause Time
bits : 0 - 15 (16 bit)
access : read-write
Pause Frames Received Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FROK : Pause Frames received OK
bits : 0 - 15 (16 bit)
access : read-write
Network Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPD : Speed
bits : 0 - 0 (1 bit)
access : read-write
FD : Full Duplex
bits : 1 - 1 (1 bit)
access : read-write
JFRAME : Jumbo Frames
bits : 3 - 3 (1 bit)
access : read-write
CAF : Copy All Frames
bits : 4 - 4 (1 bit)
access : read-write
NBC : No Broadcast
bits : 5 - 5 (1 bit)
access : read-write
MTI : Multicast Hash Enable
bits : 6 - 6 (1 bit)
access : read-write
UNI : Unicast Hash Enable
bits : 7 - 7 (1 bit)
access : read-write
BIG : Receive 1536 bytes frames
bits : 8 - 8 (1 bit)
access : read-write
CLK : MDC clock divider
bits : 10 - 11 (2 bit)
access : read-write
RTY : Retry test
bits : 12 - 12 (1 bit)
access : read-write
PAE : Pause Enable
bits : 13 - 13 (1 bit)
access : read-write
RBOF : Receive Buffer Offset
bits : 14 - 15 (2 bit)
access : read-write
RLCE : Receive Length field Checking Enable
bits : 16 - 16 (1 bit)
access : read-write
DRFCS : Discard Receive FCS
bits : 17 - 17 (1 bit)
access : read-write
EFRHD :
bits : 18 - 18 (1 bit)
access : read-write
IRXFCS : Ignore RX FCS
bits : 19 - 19 (1 bit)
access : read-write
Frames Transmitted Ok Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTOK : Frames Transmitted OK
bits : 0 - 23 (24 bit)
access : read-write
Single Collision Frames Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCF : Single Collision Frames
bits : 0 - 15 (16 bit)
access : read-write
Multiple Collision Frames Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCF : Multicollision Frames
bits : 0 - 15 (16 bit)
access : read-write
Frames Received Ok Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FROK : Frames Received OK
bits : 0 - 23 (24 bit)
access : read-write
Frame Check Sequence Errors Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCSE : Frame Check Sequence Errors
bits : 0 - 7 (8 bit)
access : read-write
Alignment Errors Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALE : Alignment Errors
bits : 0 - 7 (8 bit)
access : read-write
Deferred Transmission Frames Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTF : Deferred Transmission Frames
bits : 0 - 15 (16 bit)
access : read-write
Late Collisions Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCOL : Late Collisions
bits : 0 - 7 (8 bit)
access : read-write
Excessive Collisions Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXCOL : Excessive Collisions
bits : 0 - 7 (8 bit)
access : read-write
Transmit Underrun Errors Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUND : Transmit Underruns
bits : 0 - 7 (8 bit)
access : read-write
Carrier Sense Errors Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSE : Carrier Sense Errors
bits : 0 - 7 (8 bit)
access : read-write
Receive Resource Errors Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRE : Receive Resource Errors
bits : 0 - 15 (16 bit)
access : read-write
Receive Overrun Errors Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROVR : Receive Overrun
bits : 0 - 7 (8 bit)
access : read-write
Receive Symbol Errors Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSE : Receive Symbol Errors
bits : 0 - 7 (8 bit)
access : read-write
Excessive Length Errors Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXL : Excessive Length Errors
bits : 0 - 7 (8 bit)
access : read-write
Receive Jabbers Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RJB : Receive Jabbers
bits : 0 - 7 (8 bit)
access : read-write
Network Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MDIO :
bits : 1 - 1 (1 bit)
access : read-only
IDLE :
bits : 2 - 2 (1 bit)
access : read-only
Undersize Frames Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USF : Undersize frames
bits : 0 - 7 (8 bit)
access : read-write
SQE Test Errors Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQER : SQE test errors
bits : 0 - 7 (8 bit)
access : read-write
Received Length Field Mismatch Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RLFM : Receive Length Field Mismatch
bits : 0 - 7 (8 bit)
access : read-write
Hash Register Bottom [31:0] Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Hash Register Top [63:32] Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 1 Bottom Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 1 Top Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 15 (16 bit)
access : read-write
Specific Address 2 Bottom Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 2 Top Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 15 (16 bit)
access : read-write
Specific Address 3 Bottom Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 3 Top Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 15 (16 bit)
access : read-write
Specific Address 4 Bottom Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 4 Top Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 15 (16 bit)
access : read-write
Type ID Checking Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TID : Type ID checking
bits : 0 - 15 (16 bit)
access : read-write
User Input/Output Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RMII :
bits : 0 - 0 (1 bit)
access : read-write
CLKEN :
bits : 1 - 1 (1 bit)
access : read-write
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