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SSC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

RCMR

RPR

RCR

TPR

TCR

RNPR

RNCR

TNPR

TNCR

PTCR

PTSR

RFMR

TCMR

TFMR

RHR

THR

RSHR

TSHR

RC0R

RC1R

CMR

SR

IER

IDR

IMR


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXEN RXDIS TXEN TXDIS SWRST

RXEN : Receive Enable
bits : 0 - 0 (1 bit)
access : write-only

RXDIS : Receive Disable
bits : 1 - 1 (1 bit)
access : write-only

TXEN : Transmit Enable
bits : 8 - 8 (1 bit)
access : write-only

TXDIS : Transmit Disable
bits : 9 - 9 (1 bit)
access : write-only

SWRST : Software Reset
bits : 15 - 15 (1 bit)
access : write-only


RCMR

Receive Clock Mode Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCMR RCMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKS CKO CKI CKG START STOP STTDLY PERIOD

CKS : Receive Clock Selection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : MCK

Divided Clock

0x1 : TK

TK Clock signal

0x2 : RK

RK pin

End of enumeration elements list.

CKO : Receive Clock Output Mode Selection
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : CONTINUOUS

Continuous Receive Clock

0x2 : TRANSFER

Receive Clock only during data transfers

End of enumeration elements list.

CKI : Receive Clock Inversion
bits : 5 - 5 (1 bit)
access : read-write

CKG : Receive Clock Gating Selection
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : CONTINUOUS

Continuous Receive Clock

0x2 : TRANSFER

Receive Clock only during data transfers

End of enumeration elements list.

START : Receive Start Selection
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

0x0 : CONTINUOUS

Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.

0x1 : TRANSMIT

Transmit start

0x2 : RF_LOW

Detection of a low level on RF signal

0x3 : RF_HIGH

Detection of a high level on RF signal

0x4 : RF_FALLING

Detection of a falling edge on RF signal

0x5 : RF_RISING

Detection of a rising edge on RF signal

0x6 : RF_LEVEL

Detection of any level change on RF signal

0x7 : RF_EDGE

Detection of any edge on RF signal

0x8 : CMP_0

Compare 0

End of enumeration elements list.

STOP : Receive Stop Selection
bits : 12 - 12 (1 bit)
access : read-write

STTDLY : Receive Start Delay
bits : 16 - 23 (8 bit)
access : read-write

PERIOD : Receive Period Divider Selection
bits : 24 - 31 (8 bit)
access : read-write


RPR

Receive Pointer Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPR RPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPTR

RXPTR : Receive Pointer Register
bits : 0 - 31 (32 bit)
access : read-write


RCR

Receive Counter Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCTR

RXCTR : Receive Counter Register
bits : 0 - 15 (16 bit)
access : read-write


TPR

Transmit Pointer Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPR TPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXPTR

TXPTR : Transmit Counter Register
bits : 0 - 31 (32 bit)
access : read-write


TCR

Transmit Counter Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCTR

TXCTR : Transmit Counter Register
bits : 0 - 15 (16 bit)
access : read-write


RNPR

Receive Next Pointer Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNPR RNPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNPTR

RXNPTR : Receive Next Pointer
bits : 0 - 31 (32 bit)
access : read-write


RNCR

Receive Next Counter Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNCR RNCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNCTR

RXNCTR : Receive Next Counter
bits : 0 - 15 (16 bit)
access : read-write


TNPR

Transmit Next Pointer Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TNPR TNPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXNPTR

TXNPTR : Transmit Next Pointer
bits : 0 - 31 (32 bit)
access : read-write


TNCR

Transmit Next Counter Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TNCR TNCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXNCTR

TXNCTR : Transmit Counter Next
bits : 0 - 15 (16 bit)
access : read-write


PTCR

Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PTCR PTCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN RXTDIS TXTEN TXTDIS

RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only

RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only

TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only

TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only


PTSR

Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PTSR PTSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN TXTEN

RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only

TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only


RFMR

Receive Frame Mode Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFMR RFMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATLEN LOOP MSBF DATNB FSLEN FSOS FSEDGE FSLEN_EXT

DATLEN : Data Length
bits : 0 - 4 (5 bit)
access : read-write

LOOP : Loop Mode
bits : 5 - 5 (1 bit)
access : read-write

MSBF : Most Significant Bit First
bits : 7 - 7 (1 bit)
access : read-write

DATNB : Data Number per Frame
bits : 8 - 11 (4 bit)
access : read-write

FSLEN : Receive Frame Sync Length
bits : 16 - 19 (4 bit)
access : read-write

FSOS : Receive Frame Sync Output Selection
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : NEGATIVE

Negative Pulse

0x2 : POSITIVE

Positive Pulse

0x3 : LOW

Driven Low during data transfer

0x4 : HIGH

Driven High during data transfer

0x5 : TOGGLING

Toggling at each start of data transfer

End of enumeration elements list.

FSEDGE : Frame Sync Edge Detection
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Positive Edge Detection

1 : NEGATIVE

Negative Edge Detection

End of enumeration elements list.

FSLEN_EXT : FSLEN Field Extension
bits : 28 - 31 (4 bit)
access : read-write


TCMR

Transmit Clock Mode Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCMR TCMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKS CKO CKI CKG START STTDLY PERIOD

CKS : Transmit Clock Selection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : MCK

Divided Clock

0x1 : TK

TK Clock signal

0x2 : RK

RK pin

End of enumeration elements list.

CKO : Transmit Clock Output Mode Selection
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : CONTINUOUS

Continuous Receive Clock

0x2 : TRANSFER

Transmit Clock only during data transfers

End of enumeration elements list.

CKI : Transmit Clock Inversion
bits : 5 - 5 (1 bit)
access : read-write

CKG : Transmit Clock Gating Selection
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : CONTINUOUS

Transmit Clock enabled only if TF Low

0x2 : TRANSFER

Transmit Clock enabled only if TF High

End of enumeration elements list.

START : Transmit Start Selection
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

0x0 : CONTINUOUS

Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.

0x1 : RECEIVE

Receive start

0x2 : RF_LOW

Detection of a low level on TF signal

0x3 : RF_HIGH

Detection of a high level on TF signal

0x4 : RF_FALLING

Detection of a falling edge on TF signal

0x5 : RF_RISING

Detection of a rising edge on TF signal

0x6 : RF_LEVEL

Detection of any level change on TF signal

0x7 : RF_EDGE

Detection of any edge on TF signal

0x8 : CMP_0

Compare 0

End of enumeration elements list.

STTDLY : Transmit Start Delay
bits : 16 - 23 (8 bit)
access : read-write

PERIOD : Transmit Period Divider Selection
bits : 24 - 31 (8 bit)
access : read-write


TFMR

Transmit Frame Mode Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFMR TFMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATLEN DATDEF MSBF DATNB FSLEN FSOS FSDEN FSEDGE FSLEN_EXT

DATLEN : Data Length
bits : 0 - 4 (5 bit)
access : read-write

DATDEF : Data Default Value
bits : 5 - 5 (1 bit)
access : read-write

MSBF : Most Significant Bit First
bits : 7 - 7 (1 bit)
access : read-write

DATNB : Data Number per frame
bits : 8 - 11 (4 bit)
access : read-write

FSLEN : Transmit Frame Syn Length
bits : 16 - 19 (4 bit)
access : read-write

FSOS : Transmit Frame Sync Output Selection
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : NEGATIVE

Negative Pulse

0x2 : POSITIVE

Positive Pulse

0x3 : LOW

Driven Low during data transfer

0x4 : HIGH

Driven High during data transfer

0x5 : TOGGLING

Toggling at each start of data transfer

End of enumeration elements list.

FSDEN : Frame Sync Data Enable
bits : 23 - 23 (1 bit)
access : read-write

FSEDGE : Frame Sync Edge Detection
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Positive Edge Detection

1 : NEGATIVE

Negative Edge Detection

End of enumeration elements list.

FSLEN_EXT : FSLEN Field Extension
bits : 28 - 31 (4 bit)
access : read-write


RHR

Receive Holding Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RHR RHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDAT

RDAT : Receive Data
bits : 0 - 31 (32 bit)
access : read-only


THR

Transmit Holding Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

THR THR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDAT

TDAT : Transmit Data
bits : 0 - 31 (32 bit)
access : write-only


RSHR

Receive Sync. Holding Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RSHR RSHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSDAT

RSDAT : Receive Synchronization Data
bits : 0 - 15 (16 bit)
access : read-only


TSHR

Transmit Sync. Holding Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSHR TSHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSDAT

TSDAT : Transmit Synchronization Data
bits : 0 - 15 (16 bit)
access : read-write


RC0R

Receive Compare 0 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RC0R RC0R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP0

CP0 : Receive Compare Data 0
bits : 0 - 15 (16 bit)
access : read-write


RC1R

Receive Compare 1 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RC1R RC1R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP1

CP1 : Receive Compare Data 1
bits : 0 - 15 (16 bit)
access : read-write


CMR

Clock Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR CMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Clock Divider
bits : 0 - 11 (12 bit)
access : read-write


SR

Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXRDY TXEMPTY ENDTX TXBUFE RXRDY OVRUN ENDRX RXBUFF CP0 CP1 TXSYN RXSYN TXEN RXEN

TXRDY : Transmit Ready
bits : 0 - 0 (1 bit)
access : read-only

TXEMPTY : Transmit Empty
bits : 1 - 1 (1 bit)
access : read-only

ENDTX : End of Transmission
bits : 2 - 2 (1 bit)
access : read-only

TXBUFE : Transmit Buffer Empty
bits : 3 - 3 (1 bit)
access : read-only

RXRDY : Receive Ready
bits : 4 - 4 (1 bit)
access : read-only

OVRUN : Receive Overrun
bits : 5 - 5 (1 bit)
access : read-only

ENDRX : End of Reception
bits : 6 - 6 (1 bit)
access : read-only

RXBUFF : Receive Buffer Full
bits : 7 - 7 (1 bit)
access : read-only

CP0 : Compare 0
bits : 8 - 8 (1 bit)
access : read-only

CP1 : Compare 1
bits : 9 - 9 (1 bit)
access : read-only

TXSYN : Transmit Sync
bits : 10 - 10 (1 bit)
access : read-only

RXSYN : Receive Sync
bits : 11 - 11 (1 bit)
access : read-only

TXEN : Transmit Enable
bits : 16 - 16 (1 bit)
access : read-only

RXEN : Receive Enable
bits : 17 - 17 (1 bit)
access : read-only


IER

Interrupt Enable Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXRDY TXEMPTY ENDTX TXBUFE RXRDY OVRUN ENDRX RXBUFF CP0 CP1 TXSYN RXSYN

TXRDY : Transmit Ready Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXEMPTY : Transmit Empty Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

ENDTX : End of Transmission Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

TXBUFE : Transmit Buffer Empty Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

RXRDY : Receive Ready Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVRUN : Receive Overrun Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

ENDRX : End of Reception Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

RXBUFF : Receive Buffer Full Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

CP0 : Compare 0 Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

CP1 : Compare 1 Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TXSYN : Tx Sync Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

RXSYN : Rx Sync Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only


IDR

Interrupt Disable Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXRDY TXEMPTY ENDTX TXBUFE RXRDY OVRUN ENDRX RXBUFF CP0 CP1 TXSYN RXSYN

TXRDY : Transmit Ready Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXEMPTY : Transmit Empty Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

ENDTX : End of Transmission Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

TXBUFE : Transmit Buffer Empty Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

RXRDY : Receive Ready Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

OVRUN : Receive Overrun Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

ENDRX : End of Reception Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

RXBUFF : Receive Buffer Full Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

CP0 : Compare 0 Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

CP1 : Compare 1 Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TXSYN : Tx Sync Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

RXSYN : Rx Sync Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only


IMR

Interrupt Mask Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXRDY TXEMPTY ENDTX TXBUFE RXRDY OVRUN ENDRX RXBUFF CP0 CP1 TXSYN RXSYN

TXRDY : Transmit Ready Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

TXEMPTY : Transmit Empty Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

ENDTX : End of Transmission Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

TXBUFE : Transmit Buffer Empty Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only

RXRDY : Receive Ready Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only

OVRUN : Receive Overrun Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

ENDRX : End of Reception Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only

RXBUFF : Receive Buffer Full Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only

CP0 : Compare 0 Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only

CP1 : Compare 1 Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only

TXSYN : Tx Sync Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only

RXSYN : Rx Sync Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only



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