\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
START : Start Processing
bits : 0 - 0 (1 bit)
access : write-only
SWRST : Software Reset
bits : 8 - 8 (1 bit)
access : write-only
LOADSEED : Load Seed
bits : 16 - 16 (1 bit)
access : write-only
Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATRDY : Data Ready Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
ENDRX : End of Receive Buffer Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
ENDTX : End of Transmit Buffer Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
RXBUFF : Receive Buffer Full Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
TXBUFE : Transmit Buffer Empty Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
URAD : Unspecified Register Access Detection Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
Receive Pointer Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXPTR : Receive Pointer Register
bits : 0 - 31 (32 bit)
access : read-write
Receive Counter Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXCTR : Receive Counter Register
bits : 0 - 15 (16 bit)
access : read-write
Transmit Pointer Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPTR : Transmit Counter Register
bits : 0 - 31 (32 bit)
access : read-write
Transmit Counter Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCTR : Transmit Counter Register
bits : 0 - 15 (16 bit)
access : read-write
Receive Next Pointer Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXNPTR : Receive Next Pointer
bits : 0 - 31 (32 bit)
access : read-write
Receive Next Counter Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXNCTR : Receive Next Counter
bits : 0 - 15 (16 bit)
access : read-write
Transmit Next Pointer Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNPTR : Transmit Next Pointer
bits : 0 - 31 (32 bit)
access : read-write
Transmit Next Counter Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNCTR : Transmit Counter Next
bits : 0 - 15 (16 bit)
access : read-write
Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only
RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only
TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only
Initialization Vector Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IVx : Initialization Vector x
bits : 0 - 31 (32 bit)
access : write-only
Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only
Interrupt Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATRDY : Data Ready Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
ENDRX : End of Receive Buffer Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
ENDTX : End of Transmit Buffer Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
RXBUFF : Receive Buffer Full Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
TXBUFE : Transmit Buffer Empty Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
URAD : Unspecified Register Access Detection Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
Interrupt Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATRDY : Data Ready Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
ENDRX : End of Receive Buffer Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
ENDTX : End of Transmit Buffer Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
RXBUFF : Receive Buffer Full Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
TXBUFE : Transmit Buffer Empty Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
URAD : Unspecified Register Access Detection Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATRDY : Data Ready
bits : 0 - 0 (1 bit)
access : read-only
ENDRX : End of RX Buffer
bits : 1 - 1 (1 bit)
access : read-only
ENDTX : End of TX Buffer
bits : 2 - 2 (1 bit)
access : read-only
RXBUFF : RX Buffer Full
bits : 3 - 3 (1 bit)
access : read-only
TXBUFE : TX Buffer Empty
bits : 4 - 4 (1 bit)
access : read-only
URAD : Unspecified Register Access Detection Status
bits : 8 - 8 (1 bit)
access : read-only
URAT : Unspecified Register Access Type:
bits : 12 - 13 (2 bit)
access : read-only
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIPHER : Processing Mode
bits : 0 - 0 (1 bit)
access : read-write
TDESMOD : ALGORITHM mode
bits : 1 - 1 (1 bit)
access : read-write
KEYMOD : Key Mode
bits : 4 - 4 (1 bit)
access : read-write
SMOD : Start Mode
bits : 8 - 9 (2 bit)
access : read-write
OPMOD : Operation Mode
bits : 12 - 13 (2 bit)
access : read-write
LOD : Last Output Data Mode
bits : 15 - 15 (1 bit)
access : read-write
CFBS : Cipher Feedback Data Size
bits : 16 - 17 (2 bit)
access : read-write
CKEY : Countermeasure Key
bits : 20 - 23 (4 bit)
access : read-write
CTYPE : Countermeasure Type
bits : 24 - 29 (6 bit)
access : read-write
Key 1 Word Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY1Wx : Key 1 Word x
bits : 0 - 31 (32 bit)
access : write-only
Key 2 Word Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY2Wx : Key 2 Word x
bits : 0 - 31 (32 bit)
access : write-only
Key 3 Word Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY3Wx : Key 3 Word x
bits : 0 - 31 (32 bit)
access : write-only
Key 1 Word Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY1Wx : Key 1 Word x
bits : 0 - 31 (32 bit)
access : write-only
Key 2 Word Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY2Wx : Key 2 Word x
bits : 0 - 31 (32 bit)
access : write-only
Input Data Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDATAx : Input Data x
bits : 0 - 31 (32 bit)
access : write-only
Key 3 Word Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY3Wx : Key 3 Word x
bits : 0 - 31 (32 bit)
access : write-only
Output Data Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ODATAx : Output Data x
bits : 0 - 31 (32 bit)
access : read-only
Initialization Vector Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IVx : Initialization Vector x
bits : 0 - 31 (32 bit)
access : write-only
Input Data Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDATAx : Input Data x
bits : 0 - 31 (32 bit)
access : write-only
Output Data Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ODATAx : Output Data x
bits : 0 - 31 (32 bit)
access : read-only
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