\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REPMODE : Repeat Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x00000000 : FREE
When started, the LETIMER counts down until it is stopped by software.
0x00000001 : ONESHOT
The counter counts REP0 times. When REP0 reaches zero, the counter stops.
0x00000002 : BUFFERED
The counter counts REP0 times. If REP1 has been written, it is loaded into REP0 when REP0 reaches zero. Else the counter stops
0x00000003 : DOUBLE
Both REP0 and REP1 are decremented when the LETIMER wraps around. The LETIMER counts until both REP0 and REP1 are zero
End of enumeration elements list.
UFOA0 : Underflow Output Action 0
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x00000000 : NONE
LETn_O0 is held at its idle value as defined by OPOL0.
0x00000001 : TOGGLE
LETn_O0 is toggled on CNT underflow.
0x00000002 : PULSE
LETn_O0 is held active for one LFACLKLETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL0.
0x00000003 : PWM
LETn_O0 is set idle on CNT underflow, and active on compare match with COMP1
End of enumeration elements list.
UFOA1 : Underflow Output Action 1
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x00000000 : NONE
LETn_O1 is held at its idle value as defined by OPOL1.
0x00000001 : TOGGLE
LETn_O1 is toggled on CNT underflow.
0x00000002 : PULSE
LETn_O1 is held active for one LFACLKLETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL1.
0x00000003 : PWM
LETn_O1 is set idle on CNT underflow, and active on compare match with COMP1
End of enumeration elements list.
OPOL0 : Output 0 Polarity
bits : 6 - 6 (1 bit)
access : read-write
OPOL1 : Output 1 Polarity
bits : 7 - 7 (1 bit)
access : read-write
BUFTOP : Buffered Top
bits : 8 - 8 (1 bit)
access : read-write
COMP0TOP : Compare Value 0 Is Top Value
bits : 9 - 9 (1 bit)
access : read-write
RTCC0TEN : RTC Compare 0 Trigger Enable
bits : 10 - 10 (1 bit)
access : read-write
RTCC1TEN : RTC Compare 1 Trigger Enable
bits : 11 - 11 (1 bit)
access : read-write
DEBUGRUN : Debug Mode Run Enable
bits : 12 - 12 (1 bit)
access : read-write
Compare Value Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP0 : Compare Value 0
bits : 0 - 15 (16 bit)
access : read-write
Compare Value Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP1 : Compare Value 1
bits : 0 - 15 (16 bit)
access : read-write
Repeat Counter Register 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REP0 : Repeat Counter 0
bits : 0 - 7 (8 bit)
access : read-write
Repeat Counter Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REP1 : Repeat Counter 1
bits : 0 - 7 (8 bit)
access : read-write
Interrupt Flag Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMP0 : Compare Match 0 Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only
COMP1 : Compare Match 1 Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only
UF : Underflow Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only
REP0 : Repeat Counter 0 Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only
REP1 : Repeat Counter 1 Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-only
Interrupt Flag Set Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COMP0 : Set Compare Match 0 Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only
COMP1 : Set Compare Match 1 Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only
UF : Set Underflow Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only
REP0 : Set Repeat Counter 0 Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only
REP1 : Set Repeat Counter 1 Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only
Interrupt Flag Clear Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COMP0 : Clear Compare Match 0 Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only
COMP1 : Clear Compare Match 1 Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only
UF : Clear Underflow Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only
REP0 : Clear Repeat Counter 0 Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only
REP1 : Clear Repeat Counter 1 Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only
Interrupt Enable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP0 : Compare Match 0 Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
COMP1 : Compare Match 1 Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
UF : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
REP0 : Repeat Counter 0 Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
REP1 : Repeat Counter 1 Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Freeze Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGFREEZE : Register Update Freeze
bits : 0 - 0 (1 bit)
access : read-write
Synchronization Busy Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTRL : CTRL Register Busy
bits : 0 - 0 (1 bit)
access : read-only
CMD : CMD Register Busy
bits : 1 - 1 (1 bit)
access : read-only
COMP0 : COMP0 Register Busy
bits : 2 - 2 (1 bit)
access : read-only
COMP1 : COMP1 Register Busy
bits : 3 - 3 (1 bit)
access : read-only
REP0 : REP0 Register Busy
bits : 4 - 4 (1 bit)
access : read-only
REP1 : REP1 Register Busy
bits : 5 - 5 (1 bit)
access : read-only
Command Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
START : Start LETIMER
bits : 0 - 0 (1 bit)
access : write-only
STOP : Stop LETIMER
bits : 1 - 1 (1 bit)
access : write-only
CLEAR : Clear LETIMER
bits : 2 - 2 (1 bit)
access : write-only
CTO0 : Clear Toggle Output 0
bits : 3 - 3 (1 bit)
access : write-only
CTO1 : Clear Toggle Output 1
bits : 4 - 4 (1 bit)
access : write-only
I/O Routing Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0PEN : Output 0 Pin Enable
bits : 0 - 0 (1 bit)
access : read-write
OUT1PEN : Output 1 Pin Enable
bits : 1 - 1 (1 bit)
access : read-write
LOCATION : I/O Location
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
End of enumeration elements list.
Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUNNING : LETIMER Running
bits : 0 - 0 (1 bit)
access : read-only
Counter Value Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Counter Value
bits : 0 - 15 (16 bit)
access : read-write
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