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EMAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

NCR

TSR

RBQP

TBQP

RSR

ISR

IER

IDR

IMR

MAN

PTR

PFR

NCFGR

FTO

SCF

MCF

FRO

FCSE

ALE

DTF

LCOL

ECOL

TUND

CSE

RRE

ROV

RSE

ELE

RJA

NSR

USF

STE

RLE

HRB

HRT

SA1B

SA1T

SA2B

SA2T

SA3B

SA3T

SA4B

SA4T

TID

USRIO


NCR

Network Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NCR NCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LB LLB RE TE MPE CLRSTAT INCSTAT WESTAT BP TSTART THALT

LB : LoopBack
bits : 0 - 0 (1 bit)
access : read-write

LLB : Loopback local
bits : 1 - 1 (1 bit)
access : read-write

RE : Receive enable
bits : 2 - 2 (1 bit)
access : read-write

TE : Transmit enable
bits : 3 - 3 (1 bit)
access : read-write

MPE : Management port enable
bits : 4 - 4 (1 bit)
access : read-write

CLRSTAT : Clear statistics registers
bits : 5 - 5 (1 bit)
access : read-write

INCSTAT : Increment statistics registers
bits : 6 - 6 (1 bit)
access : read-write

WESTAT : Write enable for statistics registers
bits : 7 - 7 (1 bit)
access : read-write

BP : Back pressure
bits : 8 - 8 (1 bit)
access : read-write

TSTART : Start transmission
bits : 9 - 9 (1 bit)
access : read-write

THALT : Transmit halt
bits : 10 - 10 (1 bit)
access : read-write


TSR

Transmit Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSR TSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBR COL RLES TGO BEX COMP UND

UBR : Used Bit Read
bits : 0 - 0 (1 bit)
access : read-write

COL : Collision Occurred
bits : 1 - 1 (1 bit)
access : read-write

RLES : Retry Limit exceeded
bits : 2 - 2 (1 bit)
access : read-write

TGO : Transmit Go
bits : 3 - 3 (1 bit)
access : read-write

BEX : Buffers exhausted mid frame
bits : 4 - 4 (1 bit)
access : read-write

COMP : Transmit Complete
bits : 5 - 5 (1 bit)
access : read-write

UND : Transmit Underrun
bits : 6 - 6 (1 bit)
access : read-write


RBQP

Receive Buffer Queue Pointer Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RBQP RBQP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Receive buffer queue pointer address
bits : 2 - 31 (30 bit)
access : read-write


TBQP

Transmit Buffer Queue Pointer Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBQP TBQP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Transmit buffer queue pointer address
bits : 2 - 31 (30 bit)
access : read-write


RSR

Receive Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSR RSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BNA REC OVR

BNA : Buffer Not Available
bits : 0 - 0 (1 bit)
access : read-write

REC : Frame Received
bits : 1 - 1 (1 bit)
access : read-write

OVR : Receive Overrun
bits : 2 - 2 (1 bit)
access : read-write


ISR

Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFD RCOMP RXUBR TXUBR TUND RLEX TXERR TCOMP ROVR HRESP PFRE PTZ

MFD : Management Frame Done
bits : 0 - 0 (1 bit)
access : read-write

RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : read-write

RXUBR : Receive Used Bit Read
bits : 2 - 2 (1 bit)
access : read-write

TXUBR : Transmit Used Bit Read
bits : 3 - 3 (1 bit)
access : read-write

TUND : Ethernet Transmit Buffer Underrun
bits : 4 - 4 (1 bit)
access : read-write

RLEX : Retry Limit Exceeded
bits : 5 - 5 (1 bit)
access : read-write

TXERR : Transmit Error
bits : 6 - 6 (1 bit)
access : read-write

TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : read-write

ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : read-write

HRESP : Hresp not OK
bits : 11 - 11 (1 bit)
access : read-write

PFRE : Pause Frame Received
bits : 12 - 12 (1 bit)
access : read-write

PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
access : read-write


IER

Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFD RCOMP RXUBR TXUBR TUND RLE TXERR TCOMP ROVR HRESP PFR PTZ

MFD : Management Frame sent
bits : 0 - 0 (1 bit)
access : write-only

RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : write-only

RXUBR : Receive Used Bit Read
bits : 2 - 2 (1 bit)
access : write-only

TXUBR : Transmit Used Bit Read
bits : 3 - 3 (1 bit)
access : write-only

TUND : Ethernet Transmit Buffer Underrun
bits : 4 - 4 (1 bit)
access : write-only

RLE : Retry Limit Exceeded
bits : 5 - 5 (1 bit)
access : write-only

TXERR :
bits : 6 - 6 (1 bit)
access : write-only

TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : write-only

ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : write-only

HRESP : Hresp not OK
bits : 11 - 11 (1 bit)
access : write-only

PFR : Pause Frame Received
bits : 12 - 12 (1 bit)
access : write-only

PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
access : write-only


IDR

Interrupt Disable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFD RCOMP RXUBR TXUBR TUND RLE TXERR TCOMP ROVR HRESP PFR PTZ

MFD : Management Frame sent
bits : 0 - 0 (1 bit)
access : write-only

RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : write-only

RXUBR : Receive Used Bit Read
bits : 2 - 2 (1 bit)
access : write-only

TXUBR : Transmit Used Bit Read
bits : 3 - 3 (1 bit)
access : write-only

TUND : Ethernet Transmit Buffer Underrun
bits : 4 - 4 (1 bit)
access : write-only

RLE : Retry Limit Exceeded
bits : 5 - 5 (1 bit)
access : write-only

TXERR :
bits : 6 - 6 (1 bit)
access : write-only

TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : write-only

ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : write-only

HRESP : Hresp not OK
bits : 11 - 11 (1 bit)
access : write-only

PFR : Pause Frame Received
bits : 12 - 12 (1 bit)
access : write-only

PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
access : write-only


IMR

Interrupt Mask Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFD RCOMP RXUBR TXUBR TUND RLE TXERR TCOMP ROVR HRESP PFR PTZ

MFD : Management Frame sent
bits : 0 - 0 (1 bit)
access : read-only

RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : read-only

RXUBR : Receive Used Bit Read
bits : 2 - 2 (1 bit)
access : read-only

TXUBR : Transmit Used Bit Read
bits : 3 - 3 (1 bit)
access : read-only

TUND : Ethernet Transmit Buffer Underrun
bits : 4 - 4 (1 bit)
access : read-only

RLE : Retry Limit Exceeded
bits : 5 - 5 (1 bit)
access : read-only

TXERR :
bits : 6 - 6 (1 bit)
access : read-only

TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : read-only

ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : read-only

HRESP : Hresp not OK
bits : 11 - 11 (1 bit)
access : read-only

PFR : Pause Frame Received
bits : 12 - 12 (1 bit)
access : read-only

PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
access : read-only


MAN

Phy Maintenance Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAN MAN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA CODE REGA PHYA RW SOF

DATA :
bits : 0 - 15 (16 bit)
access : read-write

CODE :
bits : 16 - 17 (2 bit)
access : read-write

REGA : Register Address
bits : 18 - 22 (5 bit)
access : read-write

PHYA : PHY Address
bits : 23 - 27 (5 bit)
access : read-write

RW : Read-write
bits : 28 - 29 (2 bit)
access : read-write

SOF : Start of frame
bits : 30 - 31 (2 bit)
access : read-write


PTR

Pause Time Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PTR PTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTIME

PTIME : Pause Time
bits : 0 - 15 (16 bit)
access : read-write


PFR

Pause Frames Received Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFR PFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FROK

FROK : Pause Frames received OK
bits : 0 - 15 (16 bit)
access : read-write


NCFGR

Network Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NCFGR NCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPD FD JFRAME CAF NBC MTI UNI BIG CLK RTY PAE RBOF RLCE DRFCS EFRHD IRXFCS

SPD : Speed
bits : 0 - 0 (1 bit)
access : read-write

FD : Full Duplex
bits : 1 - 1 (1 bit)
access : read-write

JFRAME : Jumbo Frames
bits : 3 - 3 (1 bit)
access : read-write

CAF : Copy All Frames
bits : 4 - 4 (1 bit)
access : read-write

NBC : No Broadcast
bits : 5 - 5 (1 bit)
access : read-write

MTI : Multicast Hash Enable
bits : 6 - 6 (1 bit)
access : read-write

UNI : Unicast Hash Enable
bits : 7 - 7 (1 bit)
access : read-write

BIG : Receive 1536 bytes frames
bits : 8 - 8 (1 bit)
access : read-write

CLK : MDC clock divider
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

0x0 : MCK_8

MCK divided by 8 (MCK up to 20 MHz).

0x1 : MCK_16

MCK divided by 16 (MCK up to 40 MHz).

0x2 : MCK_32

MCK divided by 32 (MCK up to 80 MHz).

0x3 : MCK_64

MCK divided by 64 (MCK up to 160 MHz).

End of enumeration elements list.

RTY : Retry test
bits : 12 - 12 (1 bit)
access : read-write

PAE : Pause Enable
bits : 13 - 13 (1 bit)
access : read-write

RBOF : Receive Buffer Offset
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0x0 : OFFSET_0

No offset from start of receive buffer.

0x1 : OFFSET_1

One-byte offset from start of receive buffer.

0x2 : OFFSET_2

Two-byte offset from start of receive buffer.

0x3 : OFFSET_3

Three-byte offset from start of receive buffer.

End of enumeration elements list.

RLCE : Receive Length field Checking Enable
bits : 16 - 16 (1 bit)
access : read-write

DRFCS : Discard Receive FCS
bits : 17 - 17 (1 bit)
access : read-write

EFRHD :
bits : 18 - 18 (1 bit)
access : read-write

IRXFCS : Ignore RX FCS
bits : 19 - 19 (1 bit)
access : read-write


FTO

Frames Transmitted Ok Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FTO FTO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTOK

FTOK : Frames Transmitted OK
bits : 0 - 23 (24 bit)
access : read-write


SCF

Single Collision Frames Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCF SCF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCF

SCF : Single Collision Frames
bits : 0 - 15 (16 bit)
access : read-write


MCF

Multiple Collision Frames Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCF MCF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCF

MCF : Multicollision Frames
bits : 0 - 15 (16 bit)
access : read-write


FRO

Frames Received Ok Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRO FRO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FROK

FROK : Frames Received OK
bits : 0 - 23 (24 bit)
access : read-write


FCSE

Frame Check Sequence Errors Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCSE FCSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCSE

FCSE : Frame Check Sequence Errors
bits : 0 - 7 (8 bit)
access : read-write


ALE

Alignment Errors Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALE ALE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALE

ALE : Alignment Errors
bits : 0 - 7 (8 bit)
access : read-write


DTF

Deferred Transmission Frames Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTF DTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTF

DTF : Deferred Transmission Frames
bits : 0 - 15 (16 bit)
access : read-write


LCOL

Late Collisions Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCOL LCOL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCOL

LCOL : Late Collisions
bits : 0 - 7 (8 bit)
access : read-write


ECOL

Excessive Collisions Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECOL ECOL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCOL

EXCOL : Excessive Collisions
bits : 0 - 7 (8 bit)
access : read-write


TUND

Transmit Underrun Errors Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TUND TUND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TUND

TUND : Transmit Underruns
bits : 0 - 7 (8 bit)
access : read-write


CSE

Carrier Sense Errors Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSE CSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSE

CSE : Carrier Sense Errors
bits : 0 - 7 (8 bit)
access : read-write


RRE

Receive Resource Errors Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RRE RRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRE

RRE : Receive Resource Errors
bits : 0 - 15 (16 bit)
access : read-write


ROV

Receive Overrun Errors Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROV ROV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROVR

ROVR : Receive Overrun
bits : 0 - 7 (8 bit)
access : read-write


RSE

Receive Symbol Errors Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSE RSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSE

RSE : Receive Symbol Errors
bits : 0 - 7 (8 bit)
access : read-write


ELE

Excessive Length Errors Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ELE ELE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXL

EXL : Excessive Length Errors
bits : 0 - 7 (8 bit)
access : read-write


RJA

Receive Jabbers Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RJA RJA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RJB

RJB : Receive Jabbers
bits : 0 - 7 (8 bit)
access : read-write


NSR

Network Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NSR NSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDIO IDLE

MDIO :
bits : 1 - 1 (1 bit)
access : read-only

IDLE :
bits : 2 - 2 (1 bit)
access : read-only


USF

Undersize Frames Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USF USF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USF

USF : Undersize frames
bits : 0 - 7 (8 bit)
access : read-write


STE

SQE Test Errors Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STE STE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQER

SQER : SQE test errors
bits : 0 - 7 (8 bit)
access : read-write


RLE

Received Length Field Mismatch Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RLE RLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLFM

RLFM : Receive Length Field Mismatch
bits : 0 - 7 (8 bit)
access : read-write


HRB

Hash Register Bottom [31:0] Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HRB HRB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR :
bits : 0 - 31 (32 bit)
access : read-write


HRT

Hash Register Top [63:32] Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HRT HRT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR :
bits : 0 - 31 (32 bit)
access : read-write


SA1B

Specific Address 1 Bottom Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SA1B SA1B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR :
bits : 0 - 31 (32 bit)
access : read-write


SA1T

Specific Address 1 Top Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SA1T SA1T read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR :
bits : 0 - 15 (16 bit)
access : read-write


SA2B

Specific Address 2 Bottom Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SA2B SA2B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR :
bits : 0 - 31 (32 bit)
access : read-write


SA2T

Specific Address 2 Top Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SA2T SA2T read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR :
bits : 0 - 15 (16 bit)
access : read-write


SA3B

Specific Address 3 Bottom Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SA3B SA3B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR :
bits : 0 - 31 (32 bit)
access : read-write


SA3T

Specific Address 3 Top Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SA3T SA3T read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR :
bits : 0 - 15 (16 bit)
access : read-write


SA4B

Specific Address 4 Bottom Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SA4B SA4B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR :
bits : 0 - 31 (32 bit)
access : read-write


SA4T

Specific Address 4 Top Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SA4T SA4T read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR :
bits : 0 - 15 (16 bit)
access : read-write


TID

Type ID Checking Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TID TID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TID

TID : Type ID checking
bits : 0 - 15 (16 bit)
access : read-write


USRIO

User Input/Output Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USRIO USRIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMII CLKEN

RMII : Reduce MII
bits : 0 - 0 (1 bit)
access : read-write

CLKEN : Clock Enable
bits : 1 - 1 (1 bit)
access : read-write



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