\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOCALIE : End of calibration interrupt enable
bits : 0 - 0 (1 bit)
JEOCIE : Injected end of conversion interrupt enable
bits : 1 - 1 (1 bit)
JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)
REOCIE : Regular end of conversion interrupt enable
bits : 3 - 3 (1 bit)
ROVRIE : Regular data overrun interrupt enable
bits : 4 - 4 (1 bit)
REFV : Reference voltage selection
bits : 8 - 9 (2 bit)
SLOWCK : Slow clock mode enable
bits : 10 - 10 (1 bit)
SBI : Enter Standby mode when idle
bits : 11 - 11 (1 bit)
PDI : Enter power down mode when idle
bits : 12 - 12 (1 bit)
JSYNC : Launch a injected conversion synchronously with SDADC1
bits : 14 - 14 (1 bit)
RSYNC : Launch regular conversion synchronously with SDADC1
bits : 15 - 15 (1 bit)
JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 16 - 16 (1 bit)
RDMAEN : DMA channel enabled to read data for the regular channel
bits : 17 - 17 (1 bit)
INIT : Initialization mode request
bits : 31 - 31 (1 bit)
injected channel group selection register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection
bits : 0 - 8 (9 bit)
configuration 0 register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET0 : Twelve-bit calibration offset for configuration 0
bits : 0 - 11 (12 bit)
GAIN0 : Gain setting for configuration 0
bits : 20 - 22 (3 bit)
SE0 : Single-ended mode for configuration 0
bits : 26 - 27 (2 bit)
COMMON0 : Common mode for configuration 0
bits : 30 - 31 (2 bit)
configuration 1 register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET1 : Twelve-bit calibration offset for configuration 1
bits : 0 - 11 (12 bit)
GAIN1 : Gain setting for configuration 1
bits : 20 - 22 (3 bit)
SE1 : Single-ended mode for configuration 1
bits : 26 - 27 (2 bit)
COMMON1 : Common mode for configuration 1
bits : 30 - 31 (2 bit)
configuration 2 register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET2 : Twelve-bit calibration offset for configuration 2
bits : 0 - 11 (12 bit)
GAIN2 : Gain setting for configuration 2
bits : 20 - 22 (3 bit)
SE2 : Single-ended mode for configuration 2
bits : 26 - 27 (2 bit)
COMMON2 : Common mode for configuration 2
bits : 30 - 31 (2 bit)
control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADON : SDADC enable
bits : 0 - 0 (1 bit)
CALIBCNT : Number of calibration sequences to be performed (number of valid configurations)
bits : 1 - 2 (2 bit)
STARTCALIB : Start calibration
bits : 4 - 4 (1 bit)
JCONT : Continuous mode selection for injected conversions
bits : 5 - 5 (1 bit)
JDS : Delay start of injected conversions.
bits : 6 - 6 (1 bit)
JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 11 (4 bit)
JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)
JSWSTART : Start a conversion of the injected group of channels
bits : 15 - 15 (1 bit)
RCH : Regular channel selection
bits : 16 - 19 (4 bit)
RCONT : Continuous mode selection for regular conversions
bits : 22 - 22 (1 bit)
RSWSTART : Software start of a conversion on the regular channel
bits : 23 - 23 (1 bit)
FAST : Fast conversion mode selection
bits : 24 - 24 (1 bit)
channel configuration register 1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CONFCH0 : CONFCH0
bits : 0 - 1 (2 bit)
CONFCH1 : CONFCH1
bits : 4 - 5 (2 bit)
CONFCH2 : CONFCH2
bits : 8 - 9 (2 bit)
CONFCH3 : CONFCH3
bits : 12 - 13 (2 bit)
CONFCH4 : CONFCH4
bits : 16 - 17 (2 bit)
CONFCH5 : CONFCH5
bits : 20 - 21 (2 bit)
CONFCH6 : CONFCH6
bits : 24 - 25 (2 bit)
CONFCH7 : CONFCH7
bits : 28 - 29 (2 bit)
channel configuration register 2
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CONFCH8 : Channel 8 configuration
bits : 0 - 1 (2 bit)
data register for injected group
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected group conversion data
bits : 0 - 15 (16 bit)
JDATACH : Injected channel most recently converted
bits : 25 - 28 (4 bit)
data register for the regular channel
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATA : Regular channel conversion data
bits : 0 - 15 (16 bit)
SDADC1 and SDADC2 injected data register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATA1 : Injected group conversion data for SDADC1
bits : 0 - 15 (16 bit)
JDATA2 : Injected group conversion data for SDADC2
bits : 16 - 31 (16 bit)
SDADC1 and SDADC2 regular data register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATA1 : Regular conversion data for SDADC1
bits : 0 - 15 (16 bit)
RDATA2 : Regular conversion data for SDADC2
bits : 16 - 31 (16 bit)
SDADC1 and SDADC3 injected data register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATA1 : Injected group conversion data for SDADC1
bits : 0 - 15 (16 bit)
JDATA3 : Injected group conversion data for SDADC3
bits : 16 - 31 (16 bit)
SDADC1 and SDADC3 regular data register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATA1 : Regular conversion data for SDADC1
bits : 0 - 15 (16 bit)
RDATA3 : Regular conversion data for SDADC3
bits : 16 - 31 (16 bit)
interrupt and status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EOCALF : End of calibration flag
bits : 0 - 0 (1 bit)
JEOCF : End of injected conversion flag
bits : 1 - 1 (1 bit)
JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)
REOCF : End of regular conversion flag
bits : 3 - 3 (1 bit)
ROVRF : Regular conversion overrun flag
bits : 4 - 4 (1 bit)
CALIBIP : Calibration in progress status
bits : 12 - 12 (1 bit)
JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)
RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)
STABIP : Stabilization in progress status
bits : 15 - 15 (1 bit)
INITRDY : Initialization mode is ready
bits : 31 - 31 (1 bit)
interrupt and status clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLREOCALF : Clear the end of calibration flag
bits : 0 - 0 (1 bit)
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
CLRROVRF : Clear the regular conversion overrun flag
bits : 4 - 4 (1 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.