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SDADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR1

JCHGR

CONF0R

CONF1R

CONF2R

CR2

CONFCHR1

CONFCHR2

JDATAR

RDATAR

JDATA12R

RDATA12R

JDATA13R

RDATA13R

ISR

CLRISR


CR1

control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOCALIE JEOCIE JOVRIE REOCIE ROVRIE REFV SLOWCK SBI PDI JSYNC RSYNC JDMAEN RDMAEN INIT

EOCALIE : End of calibration interrupt enable
bits : 0 - 0 (1 bit)

JEOCIE : Injected end of conversion interrupt enable
bits : 1 - 1 (1 bit)

JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)

REOCIE : Regular end of conversion interrupt enable
bits : 3 - 3 (1 bit)

ROVRIE : Regular data overrun interrupt enable
bits : 4 - 4 (1 bit)

REFV : Reference voltage selection
bits : 8 - 9 (2 bit)

SLOWCK : Slow clock mode enable
bits : 10 - 10 (1 bit)

SBI : Enter Standby mode when idle
bits : 11 - 11 (1 bit)

PDI : Enter power down mode when idle
bits : 12 - 12 (1 bit)

JSYNC : Launch a injected conversion synchronously with SDADC1
bits : 14 - 14 (1 bit)

RSYNC : Launch regular conversion synchronously with SDADC1
bits : 15 - 15 (1 bit)

JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 16 - 16 (1 bit)

RDMAEN : DMA channel enabled to read data for the regular channel
bits : 17 - 17 (1 bit)

INIT : Initialization mode request
bits : 31 - 31 (1 bit)


JCHGR

injected channel group selection register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JCHGR JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : Injected channel group selection
bits : 0 - 8 (9 bit)


CONF0R

configuration 0 register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONF0R CONF0R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET0 GAIN0 SE0 COMMON0

OFFSET0 : Twelve-bit calibration offset for configuration 0
bits : 0 - 11 (12 bit)

GAIN0 : Gain setting for configuration 0
bits : 20 - 22 (3 bit)

SE0 : Single-ended mode for configuration 0
bits : 26 - 27 (2 bit)

COMMON0 : Common mode for configuration 0
bits : 30 - 31 (2 bit)


CONF1R

configuration 1 register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONF1R CONF1R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET1 GAIN1 SE1 COMMON1

OFFSET1 : Twelve-bit calibration offset for configuration 1
bits : 0 - 11 (12 bit)

GAIN1 : Gain setting for configuration 1
bits : 20 - 22 (3 bit)

SE1 : Single-ended mode for configuration 1
bits : 26 - 27 (2 bit)

COMMON1 : Common mode for configuration 1
bits : 30 - 31 (2 bit)


CONF2R

configuration 2 register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONF2R CONF2R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET2 GAIN2 SE2 COMMON2

OFFSET2 : Twelve-bit calibration offset for configuration 2
bits : 0 - 11 (12 bit)

GAIN2 : Gain setting for configuration 2
bits : 20 - 22 (3 bit)

SE2 : Single-ended mode for configuration 2
bits : 26 - 27 (2 bit)

COMMON2 : Common mode for configuration 2
bits : 30 - 31 (2 bit)


CR2

control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADON CALIBCNT STARTCALIB JCONT JDS JEXTSEL JEXTEN JSWSTART RCH RCONT RSWSTART FAST

ADON : SDADC enable
bits : 0 - 0 (1 bit)

CALIBCNT : Number of calibration sequences to be performed (number of valid configurations)
bits : 1 - 2 (2 bit)

STARTCALIB : Start calibration
bits : 4 - 4 (1 bit)

JCONT : Continuous mode selection for injected conversions
bits : 5 - 5 (1 bit)

JDS : Delay start of injected conversions.
bits : 6 - 6 (1 bit)

JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 11 (4 bit)

JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)

JSWSTART : Start a conversion of the injected group of channels
bits : 15 - 15 (1 bit)

RCH : Regular channel selection
bits : 16 - 19 (4 bit)

RCONT : Continuous mode selection for regular conversions
bits : 22 - 22 (1 bit)

RSWSTART : Software start of a conversion on the regular channel
bits : 23 - 23 (1 bit)

FAST : Fast conversion mode selection
bits : 24 - 24 (1 bit)


CONFCHR1

channel configuration register 1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFCHR1 CONFCHR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONFCH0 CONFCH1 CONFCH2 CONFCH3 CONFCH4 CONFCH5 CONFCH6 CONFCH7

CONFCH0 : CONFCH0
bits : 0 - 1 (2 bit)

CONFCH1 : CONFCH1
bits : 4 - 5 (2 bit)

CONFCH2 : CONFCH2
bits : 8 - 9 (2 bit)

CONFCH3 : CONFCH3
bits : 12 - 13 (2 bit)

CONFCH4 : CONFCH4
bits : 16 - 17 (2 bit)

CONFCH5 : CONFCH5
bits : 20 - 21 (2 bit)

CONFCH6 : CONFCH6
bits : 24 - 25 (2 bit)

CONFCH7 : CONFCH7
bits : 28 - 29 (2 bit)


CONFCHR2

channel configuration register 2
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFCHR2 CONFCHR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONFCH8

CONFCH8 : Channel 8 configuration
bits : 0 - 1 (2 bit)


JDATAR

data register for injected group
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDATAR JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA JDATACH

JDATA : Injected group conversion data
bits : 0 - 15 (16 bit)

JDATACH : Injected channel most recently converted
bits : 25 - 28 (4 bit)


RDATAR

data register for the regular channel
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDATAR RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA

RDATA : Regular channel conversion data
bits : 0 - 15 (16 bit)


JDATA12R

SDADC1 and SDADC2 injected data register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDATA12R JDATA12R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA1 JDATA2

JDATA1 : Injected group conversion data for SDADC1
bits : 0 - 15 (16 bit)

JDATA2 : Injected group conversion data for SDADC2
bits : 16 - 31 (16 bit)


RDATA12R

SDADC1 and SDADC2 regular data register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDATA12R RDATA12R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA1 RDATA2

RDATA1 : Regular conversion data for SDADC1
bits : 0 - 15 (16 bit)

RDATA2 : Regular conversion data for SDADC2
bits : 16 - 31 (16 bit)


JDATA13R

SDADC1 and SDADC3 injected data register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDATA13R JDATA13R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA1 JDATA3

JDATA1 : Injected group conversion data for SDADC1
bits : 0 - 15 (16 bit)

JDATA3 : Injected group conversion data for SDADC3
bits : 16 - 31 (16 bit)


RDATA13R

SDADC1 and SDADC3 regular data register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDATA13R RDATA13R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA1 RDATA3

RDATA1 : Regular conversion data for SDADC1
bits : 0 - 15 (16 bit)

RDATA3 : Regular conversion data for SDADC3
bits : 16 - 31 (16 bit)


ISR

interrupt and status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOCALF JEOCF JOVRF REOCF ROVRF CALIBIP JCIP RCIP STABIP INITRDY

EOCALF : End of calibration flag
bits : 0 - 0 (1 bit)

JEOCF : End of injected conversion flag
bits : 1 - 1 (1 bit)

JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)

REOCF : End of regular conversion flag
bits : 3 - 3 (1 bit)

ROVRF : Regular conversion overrun flag
bits : 4 - 4 (1 bit)

CALIBIP : Calibration in progress status
bits : 12 - 12 (1 bit)

JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)

RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)

STABIP : Stabilization in progress status
bits : 15 - 15 (1 bit)

INITRDY : Initialization mode is ready
bits : 31 - 31 (1 bit)


CLRISR

interrupt and status clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLRISR CLRISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLREOCALF CLRJOVRF CLRROVRF

CLREOCALF : Clear the end of calibration flag
bits : 0 - 0 (1 bit)

CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)

CLRROVRF : Clear the regular conversion overrun flag
bits : 4 - 4 (1 bit)



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