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EBI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SETUP0

SETUP1

PULSE1

CYCLE1

MODE1

SETUP2

PULSE2

CYCLE2

MODE2

SETUP3

PULSE3

CYCLE3

MODE3

PULSE0

SETUP4

PULSE4

CYCLE4

MODE4

SETUP5

PULSE5

CYCLE5

MODE5

CYCLE0

MODE0

DELAY1

DELAY2

DELAY3

DELAY4

DELAY5

DELAY6

DELAY7

DELAY8

WPMR

WPSR


SETUP0

SMC Setup Register (CS_number = 0)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETUP0 SETUP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_SETUP NCS_WR_SETUP NRD_SETUP NCS_RD_SETUP

NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write

NCS_WR_SETUP : NCS Setup Length in WRITE Access
bits : 8 - 13 (6 bit)
access : read-write

NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write

NCS_RD_SETUP : NCS Setup Length in READ Access
bits : 24 - 29 (6 bit)
access : read-write


SETUP1

SMC Setup Register (CS_number = 1)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETUP1 SETUP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_SETUP NCS_WR_SETUP NRD_SETUP NCS_RD_SETUP

NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write

NCS_WR_SETUP : NCS Setup Length in WRITE Access
bits : 8 - 13 (6 bit)
access : read-write

NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write

NCS_RD_SETUP : NCS Setup Length in READ Access
bits : 24 - 29 (6 bit)
access : read-write


PULSE1

SMC Pulse Register (CS_number = 1)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PULSE1 PULSE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_PULSE NCS_WR_PULSE NRD_PULSE NCS_RD_PULSE

NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write

NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write

NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write

NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write


CYCLE1

SMC Cycle Register (CS_number = 1)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CYCLE1 CYCLE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_CYCLE NRD_CYCLE

NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write

NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write


MODE1

SMC Mode Register (CS_number = 1)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 MODE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_MODE WRITE_MODE EXNW_MODE BAT DBW TDF_CYCLES TDF_MODE PMEN PS

READ_MODE :
bits : 0 - 0 (1 bit)
access : read-write

WRITE_MODE :
bits : 1 - 1 (1 bit)
access : read-write

EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write

BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write

DBW : Data Bus Width
bits : 12 - 13 (2 bit)
access : read-write

TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write

TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write

PMEN : Page Mode Enabled
bits : 24 - 24 (1 bit)
access : read-write

PS : Page Size
bits : 28 - 29 (2 bit)
access : read-write


SETUP2

SMC Setup Register (CS_number = 2)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETUP2 SETUP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_SETUP NCS_WR_SETUP NRD_SETUP NCS_RD_SETUP

NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write

NCS_WR_SETUP : NCS Setup Length in WRITE Access
bits : 8 - 13 (6 bit)
access : read-write

NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write

NCS_RD_SETUP : NCS Setup Length in READ Access
bits : 24 - 29 (6 bit)
access : read-write


PULSE2

SMC Pulse Register (CS_number = 2)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PULSE2 PULSE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_PULSE NCS_WR_PULSE NRD_PULSE NCS_RD_PULSE

NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write

NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write

NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write

NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write


CYCLE2

SMC Cycle Register (CS_number = 2)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CYCLE2 CYCLE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_CYCLE NRD_CYCLE

NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write

NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write


MODE2

SMC Mode Register (CS_number = 2)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 MODE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_MODE WRITE_MODE EXNW_MODE BAT DBW TDF_CYCLES TDF_MODE PMEN PS

READ_MODE :
bits : 0 - 0 (1 bit)
access : read-write

WRITE_MODE :
bits : 1 - 1 (1 bit)
access : read-write

EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write

BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write

DBW : Data Bus Width
bits : 12 - 13 (2 bit)
access : read-write

TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write

TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write

PMEN : Page Mode Enabled
bits : 24 - 24 (1 bit)
access : read-write

PS : Page Size
bits : 28 - 29 (2 bit)
access : read-write


SETUP3

SMC Setup Register (CS_number = 3)
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETUP3 SETUP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_SETUP NCS_WR_SETUP NRD_SETUP NCS_RD_SETUP

NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write

NCS_WR_SETUP : NCS Setup Length in WRITE Access
bits : 8 - 13 (6 bit)
access : read-write

NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write

NCS_RD_SETUP : NCS Setup Length in READ Access
bits : 24 - 29 (6 bit)
access : read-write


PULSE3

SMC Pulse Register (CS_number = 3)
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PULSE3 PULSE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_PULSE NCS_WR_PULSE NRD_PULSE NCS_RD_PULSE

NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write

NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write

NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write

NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write


CYCLE3

SMC Cycle Register (CS_number = 3)
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CYCLE3 CYCLE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_CYCLE NRD_CYCLE

NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write

NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write


MODE3

SMC Mode Register (CS_number = 3)
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE3 MODE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_MODE WRITE_MODE EXNW_MODE BAT DBW TDF_CYCLES TDF_MODE PMEN PS

READ_MODE :
bits : 0 - 0 (1 bit)
access : read-write

WRITE_MODE :
bits : 1 - 1 (1 bit)
access : read-write

EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write

BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write

DBW : Data Bus Width
bits : 12 - 13 (2 bit)
access : read-write

TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write

TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write

PMEN : Page Mode Enabled
bits : 24 - 24 (1 bit)
access : read-write

PS : Page Size
bits : 28 - 29 (2 bit)
access : read-write


PULSE0

SMC Pulse Register (CS_number = 0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PULSE0 PULSE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_PULSE NCS_WR_PULSE NRD_PULSE NCS_RD_PULSE

NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write

NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write

NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write

NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write


SETUP4

SMC Setup Register (CS_number = 4)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETUP4 SETUP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_SETUP NCS_WR_SETUP NRD_SETUP NCS_RD_SETUP

NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write

NCS_WR_SETUP : NCS Setup Length in WRITE Access
bits : 8 - 13 (6 bit)
access : read-write

NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write

NCS_RD_SETUP : NCS Setup Length in READ Access
bits : 24 - 29 (6 bit)
access : read-write


PULSE4

SMC Pulse Register (CS_number = 4)
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PULSE4 PULSE4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_PULSE NCS_WR_PULSE NRD_PULSE NCS_RD_PULSE

NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write

NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write

NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write

NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write


CYCLE4

SMC Cycle Register (CS_number = 4)
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CYCLE4 CYCLE4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_CYCLE NRD_CYCLE

NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write

NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write


MODE4

SMC Mode Register (CS_number = 4)
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE4 MODE4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_MODE WRITE_MODE EXNW_MODE BAT DBW TDF_CYCLES TDF_MODE PMEN PS

READ_MODE :
bits : 0 - 0 (1 bit)
access : read-write

WRITE_MODE :
bits : 1 - 1 (1 bit)
access : read-write

EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write

BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write

DBW : Data Bus Width
bits : 12 - 13 (2 bit)
access : read-write

TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write

TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write

PMEN : Page Mode Enabled
bits : 24 - 24 (1 bit)
access : read-write

PS : Page Size
bits : 28 - 29 (2 bit)
access : read-write


SETUP5

SMC Setup Register (CS_number = 5)
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETUP5 SETUP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_SETUP NCS_WR_SETUP NRD_SETUP NCS_RD_SETUP

NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write

NCS_WR_SETUP : NCS Setup Length in WRITE Access
bits : 8 - 13 (6 bit)
access : read-write

NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write

NCS_RD_SETUP : NCS Setup Length in READ Access
bits : 24 - 29 (6 bit)
access : read-write


PULSE5

SMC Pulse Register (CS_number = 5)
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PULSE5 PULSE5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_PULSE NCS_WR_PULSE NRD_PULSE NCS_RD_PULSE

NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write

NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write

NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write

NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write


CYCLE5

SMC Cycle Register (CS_number = 5)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CYCLE5 CYCLE5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_CYCLE NRD_CYCLE

NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write

NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write


MODE5

SMC Mode Register (CS_number = 5)
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE5 MODE5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_MODE WRITE_MODE EXNW_MODE BAT DBW TDF_CYCLES TDF_MODE PMEN PS

READ_MODE :
bits : 0 - 0 (1 bit)
access : read-write

WRITE_MODE :
bits : 1 - 1 (1 bit)
access : read-write

EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write

BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write

DBW : Data Bus Width
bits : 12 - 13 (2 bit)
access : read-write

TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write

TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write

PMEN : Page Mode Enabled
bits : 24 - 24 (1 bit)
access : read-write

PS : Page Size
bits : 28 - 29 (2 bit)
access : read-write


CYCLE0

SMC Cycle Register (CS_number = 0)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CYCLE0 CYCLE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_CYCLE NRD_CYCLE

NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write

NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write


MODE0

SMC Mode Register (CS_number = 0)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 MODE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_MODE WRITE_MODE EXNW_MODE BAT DBW TDF_CYCLES TDF_MODE PMEN PS

READ_MODE :
bits : 0 - 0 (1 bit)
access : read-write

WRITE_MODE :
bits : 1 - 1 (1 bit)
access : read-write

EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write

BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write

DBW : Data Bus Width
bits : 12 - 13 (2 bit)
access : read-write

TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write

TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write

PMEN : Page Mode Enabled
bits : 24 - 24 (1 bit)
access : read-write

PS : Page Size
bits : 28 - 29 (2 bit)
access : read-write


DELAY1

SMC Delay on I/O
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELAY1 DELAY1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Delay1 Delay2 Delay3 Delay4 Delay5 Delay6 Delay7 Delay8

Delay1 :
bits : 0 - 3 (4 bit)
access : read-write

Delay2 :
bits : 4 - 7 (4 bit)
access : read-write

Delay3 :
bits : 8 - 11 (4 bit)
access : read-write

Delay4 :
bits : 12 - 15 (4 bit)
access : read-write

Delay5 :
bits : 16 - 19 (4 bit)
access : read-write

Delay6 :
bits : 20 - 23 (4 bit)
access : read-write

Delay7 :
bits : 24 - 27 (4 bit)
access : read-write

Delay8 :
bits : 28 - 31 (4 bit)
access : read-write


DELAY2

SMC Delay on I/O
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELAY2 DELAY2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DELAY3

SMC Delay on I/O
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELAY3 DELAY3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DELAY4

SMC Delay on I/O
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELAY4 DELAY4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DELAY5

SMC Delay on I/O
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELAY5 DELAY5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DELAY6

SMC Delay on I/O
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELAY6 DELAY6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DELAY7

SMC Delay on I/O
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELAY7 DELAY7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DELAY8

SMC Delay on I/O
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELAY8 DELAY8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WPMR

SMC Write Protect Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protect KEY
bits : 8 - 31 (24 bit)
access : read-write


WPSR

SMC Write Protect Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protect Violation Source
bits : 8 - 23 (16 bit)
access : read-only



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