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TC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CCR0

CV0

RA0

RB0

RC0

SR0

IER0

IDR0

IMR0

CMR0

CMR0_WAVE_EQ_1

CCR1

CMR1

CMR1_WAVE_EQ_1

SMMR1

RAB1

CV1

RA1

RB1

RC1

SR1

IER1

IDR1

IMR1

SMMR0

CCR2

CMR2

CMR2_WAVE_EQ_1

SMMR2

RAB2

CV2

RA2

RB2

RC2

SR2

IER2

IDR2

IMR2

RAB0

BCR

BMR

QIER

QIDR

QIMR

QISR

WPMR


CCR0

Channel Control Register (channel = 0)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CCR0 CCR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKEN CLKDIS SWTRG

CLKEN : Counter Clock Enable Command
bits : 0 - 0 (1 bit)
access : write-only

CLKDIS : Counter Clock Disable Command
bits : 1 - 1 (1 bit)
access : write-only

SWTRG : Software Trigger Command
bits : 2 - 2 (1 bit)
access : write-only


CV0

Counter Value (channel = 0)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CV0 CV0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CV

CV : Counter Value
bits : 0 - 31 (32 bit)
access : read-only


RA0

Register A (channel = 0)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RA0 RA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RA

RA : Register A
bits : 0 - 31 (32 bit)
access : read-write


RB0

Register B (channel = 0)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RB0 RB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB

RB : Register B
bits : 0 - 31 (32 bit)
access : read-write


RC0

Register C (channel = 0)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RC0 RC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RC

RC : Register C
bits : 0 - 31 (32 bit)
access : read-write


SR0

Status Register (channel = 0)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR0 SR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COVFS LOVRS CPAS CPBS CPCS LDRAS LDRBS ETRGS CLKSTA MTIOA MTIOB

COVFS : Counter Overflow Status
bits : 0 - 0 (1 bit)
access : read-only

LOVRS : Load Overrun Status
bits : 1 - 1 (1 bit)
access : read-only

CPAS : RA Compare Status
bits : 2 - 2 (1 bit)
access : read-only

CPBS : RB Compare Status
bits : 3 - 3 (1 bit)
access : read-only

CPCS : RC Compare Status
bits : 4 - 4 (1 bit)
access : read-only

LDRAS : RA Loading Status
bits : 5 - 5 (1 bit)
access : read-only

LDRBS : RB Loading Status
bits : 6 - 6 (1 bit)
access : read-only

ETRGS : External Trigger Status
bits : 7 - 7 (1 bit)
access : read-only

CLKSTA : Clock Enabling Status
bits : 16 - 16 (1 bit)
access : read-only

MTIOA : TIOA Mirror
bits : 17 - 17 (1 bit)
access : read-only

MTIOB : TIOB Mirror
bits : 18 - 18 (1 bit)
access : read-only


IER0

Interrupt Enable Register (channel = 0)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER0 IER0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COVFS LOVRS CPAS CPBS CPCS LDRAS LDRBS ETRGS

COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : write-only

LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : write-only

CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : write-only

CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : write-only

CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : write-only

LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : write-only

LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : write-only

ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : write-only


IDR0

Interrupt Disable Register (channel = 0)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR0 IDR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COVFS LOVRS CPAS CPBS CPCS LDRAS LDRBS ETRGS

COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : write-only

LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : write-only

CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : write-only

CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : write-only

CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : write-only

LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : write-only

LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : write-only

ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : write-only


IMR0

Interrupt Mask Register (channel = 0)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR0 IMR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COVFS LOVRS CPAS CPBS CPCS LDRAS LDRBS ETRGS

COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : read-only

LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : read-only

CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : read-only

CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : read-only

CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : read-only

LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : read-only

LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : read-only

ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : read-only


CMR0

Channel Mode Register (channel = 0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR0 CMR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCCLKS CLKI BURST LDBSTOP LDBDIS ETRGEDG ABETRG CPCTRG WAVE LDRA LDRB

TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : TIMER_CLOCK1

Clock selected: TCLK1

0x1 : TIMER_CLOCK2

Clock selected: TCLK2

0x2 : TIMER_CLOCK3

Clock selected: TCLK3

0x3 : TIMER_CLOCK4

Clock selected: TCLK4

0x4 : TIMER_CLOCK5

Clock selected: TCLK5

0x5 : XC0

Clock selected: XC0

0x6 : XC1

Clock selected: XC1

0x7 : XC2

Clock selected: XC2

End of enumeration elements list.

CLKI : Clock Invert
bits : 3 - 3 (1 bit)
access : read-write

BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

The clock is not gated by an external signal.

0x1 : XC0

XC0 is ANDed with the selected clock.

0x2 : XC1

XC1 is ANDed with the selected clock.

0x3 : XC2

XC2 is ANDed with the selected clock.

End of enumeration elements list.

LDBSTOP : Counter Clock Stopped with RB Loading
bits : 6 - 6 (1 bit)
access : read-write

LDBDIS : Counter Clock Disable with RB Loading
bits : 7 - 7 (1 bit)
access : read-write

ETRGEDG : External Trigger Edge Selection
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

The clock is not gated by an external signal.

0x1 : RISING

Rising edge

0x2 : FALLING

Falling edge

0x3 : EDGE

Each edge

End of enumeration elements list.

ABETRG : TIOA or TIOB External Trigger Selection
bits : 10 - 10 (1 bit)
access : read-write

CPCTRG : RC Compare Trigger Enable
bits : 14 - 14 (1 bit)
access : read-write

WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
access : read-write

LDRA : RA Loading Edge Selection
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : RISING

Rising edge of TIOA

0x2 : FALLING

Falling edge of TIOA

0x3 : EDGE

Each edge of TIOA

End of enumeration elements list.

LDRB : RB Loading Edge Selection
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : RISING

Rising edge of TIOA

0x2 : FALLING

Falling edge of TIOA

0x3 : EDGE

Each edge of TIOA

End of enumeration elements list.


CMR0_WAVE_EQ_1

Channel Mode Register (channel = 0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : WAVE_EQ_1
reset_Mask : 0x0

CMR0_WAVE_EQ_1 CMR0_WAVE_EQ_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCCLKS CLKI BURST CPCSTOP CPCDIS EEVTEDG EEVT ENETRG WAVSEL WAVE ACPA ACPC AEEVT ASWTRG BCPB BCPC BEEVT BSWTRG

TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : TIMER_CLOCK1

Clock selected: TCLK1

0x1 : TIMER_CLOCK2

Clock selected: TCLK2

0x2 : TIMER_CLOCK3

Clock selected: TCLK3

0x3 : TIMER_CLOCK4

Clock selected: TCLK4

0x4 : TIMER_CLOCK5

Clock selected: TCLK5

0x5 : XC0

Clock selected: XC0

0x6 : XC1

Clock selected: XC1

0x7 : XC2

Clock selected: XC2

End of enumeration elements list.

CLKI : Clock Invert
bits : 3 - 3 (1 bit)
access : read-write

BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

The clock is not gated by an external signal.

0x1 : XC0

XC0 is ANDed with the selected clock.

0x2 : XC1

XC1 is ANDed with the selected clock.

0x3 : XC2

XC2 is ANDed with the selected clock.

End of enumeration elements list.

CPCSTOP : Counter Clock Stopped with RC Compare
bits : 6 - 6 (1 bit)
access : read-write

CPCDIS : Counter Clock Disable with RC Compare
bits : 7 - 7 (1 bit)
access : read-write

EEVTEDG : External Event Edge Selection
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : RISING

Rising edge

0x2 : FALLING

Falling edge

0x3 : EDGE

Each edge

End of enumeration elements list.

EEVT : External Event Selection
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

0x0 : TIOB

TIOB

0x1 : XC0

XC0

0x2 : XC1

XC1

0x3 : XC2

XC2

End of enumeration elements list.

ENETRG : External Event Trigger Enable
bits : 12 - 12 (1 bit)
access : read-write

WAVSEL : Waveform Selection
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

0x0 : UP

UP mode without automatic trigger on RC Compare

0x1 : UPDOWN

UPDOWN mode without automatic trigger on RC Compare

0x2 : UP_RC

UP mode with automatic trigger on RC Compare

0x3 : UPDOWN_RC

UPDOWN mode with automatic trigger on RC Compare

End of enumeration elements list.

WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
access : read-write

ACPA : RA Compare Effect on TIOA
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

ACPC : RC Compare Effect on TIOA
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

AEEVT : External Event Effect on TIOA
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

ASWTRG : Software Trigger Effect on TIOA
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

BCPB : RB Compare Effect on TIOB
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

BCPC : RC Compare Effect on TIOB
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

BEEVT : External Event Effect on TIOB
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

BSWTRG : Software Trigger Effect on TIOB
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.


CCR1

Channel Control Register (channel = 1)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CCR1 CCR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKEN CLKDIS SWTRG

CLKEN : Counter Clock Enable Command
bits : 0 - 0 (1 bit)
access : write-only

CLKDIS : Counter Clock Disable Command
bits : 1 - 1 (1 bit)
access : write-only

SWTRG : Software Trigger Command
bits : 2 - 2 (1 bit)
access : write-only


CMR1

Channel Mode Register (channel = 1)
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR1 CMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCCLKS CLKI BURST LDBSTOP LDBDIS ETRGEDG ABETRG CPCTRG WAVE LDRA LDRB

TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : TIMER_CLOCK1

Clock selected: TCLK1

0x1 : TIMER_CLOCK2

Clock selected: TCLK2

0x2 : TIMER_CLOCK3

Clock selected: TCLK3

0x3 : TIMER_CLOCK4

Clock selected: TCLK4

0x4 : TIMER_CLOCK5

Clock selected: TCLK5

0x5 : XC0

Clock selected: XC0

0x6 : XC1

Clock selected: XC1

0x7 : XC2

Clock selected: XC2

End of enumeration elements list.

CLKI : Clock Invert
bits : 3 - 3 (1 bit)
access : read-write

BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

The clock is not gated by an external signal.

0x1 : XC0

XC0 is ANDed with the selected clock.

0x2 : XC1

XC1 is ANDed with the selected clock.

0x3 : XC2

XC2 is ANDed with the selected clock.

End of enumeration elements list.

LDBSTOP : Counter Clock Stopped with RB Loading
bits : 6 - 6 (1 bit)
access : read-write

LDBDIS : Counter Clock Disable with RB Loading
bits : 7 - 7 (1 bit)
access : read-write

ETRGEDG : External Trigger Edge Selection
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

The clock is not gated by an external signal.

0x1 : RISING

Rising edge

0x2 : FALLING

Falling edge

0x3 : EDGE

Each edge

End of enumeration elements list.

ABETRG : TIOA or TIOB External Trigger Selection
bits : 10 - 10 (1 bit)
access : read-write

CPCTRG : RC Compare Trigger Enable
bits : 14 - 14 (1 bit)
access : read-write

WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
access : read-write

LDRA : RA Loading Edge Selection
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : RISING

Rising edge of TIOA

0x2 : FALLING

Falling edge of TIOA

0x3 : EDGE

Each edge of TIOA

End of enumeration elements list.

LDRB : RB Loading Edge Selection
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : RISING

Rising edge of TIOA

0x2 : FALLING

Falling edge of TIOA

0x3 : EDGE

Each edge of TIOA

End of enumeration elements list.


CMR1_WAVE_EQ_1

Channel Mode Register (channel = 1)
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : WAVE_EQ_1
reset_Mask : 0x0

CMR1_WAVE_EQ_1 CMR1_WAVE_EQ_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCCLKS CLKI BURST CPCSTOP CPCDIS EEVTEDG EEVT ENETRG WAVSEL WAVE ACPA ACPC AEEVT ASWTRG BCPB BCPC BEEVT BSWTRG

TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : TIMER_CLOCK1

Clock selected: TCLK1

0x1 : TIMER_CLOCK2

Clock selected: TCLK2

0x2 : TIMER_CLOCK3

Clock selected: TCLK3

0x3 : TIMER_CLOCK4

Clock selected: TCLK4

0x4 : TIMER_CLOCK5

Clock selected: TCLK5

0x5 : XC0

Clock selected: XC0

0x6 : XC1

Clock selected: XC1

0x7 : XC2

Clock selected: XC2

End of enumeration elements list.

CLKI : Clock Invert
bits : 3 - 3 (1 bit)
access : read-write

BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

The clock is not gated by an external signal.

0x1 : XC0

XC0 is ANDed with the selected clock.

0x2 : XC1

XC1 is ANDed with the selected clock.

0x3 : XC2

XC2 is ANDed with the selected clock.

End of enumeration elements list.

CPCSTOP : Counter Clock Stopped with RC Compare
bits : 6 - 6 (1 bit)
access : read-write

CPCDIS : Counter Clock Disable with RC Compare
bits : 7 - 7 (1 bit)
access : read-write

EEVTEDG : External Event Edge Selection
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : RISING

Rising edge

0x2 : FALLING

Falling edge

0x3 : EDGE

Each edge

End of enumeration elements list.

EEVT : External Event Selection
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

0x0 : TIOB

TIOB

0x1 : XC0

XC0

0x2 : XC1

XC1

0x3 : XC2

XC2

End of enumeration elements list.

ENETRG : External Event Trigger Enable
bits : 12 - 12 (1 bit)
access : read-write

WAVSEL : Waveform Selection
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

0x0 : UP

UP mode without automatic trigger on RC Compare

0x1 : UPDOWN

UPDOWN mode without automatic trigger on RC Compare

0x2 : UP_RC

UP mode with automatic trigger on RC Compare

0x3 : UPDOWN_RC

UPDOWN mode with automatic trigger on RC Compare

End of enumeration elements list.

WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
access : read-write

ACPA : RA Compare Effect on TIOA
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

ACPC : RC Compare Effect on TIOA
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

AEEVT : External Event Effect on TIOA
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

ASWTRG : Software Trigger Effect on TIOA
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

BCPB : RB Compare Effect on TIOB
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

BCPC : RC Compare Effect on TIOB
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

BEEVT : External Event Effect on TIOB
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

BSWTRG : Software Trigger Effect on TIOB
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.


SMMR1

Stepper Motor Mode Register (channel = 1)
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMMR1 SMMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GCEN DOWN

GCEN : Gray Count Enable
bits : 0 - 0 (1 bit)
access : read-write

DOWN : DOWN Count
bits : 1 - 1 (1 bit)
access : read-write


RAB1

Register AB (channel = 1)
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAB1 RAB1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAB

RAB : Register A or Register B
bits : 0 - 31 (32 bit)
access : read-only


CV1

Counter Value (channel = 1)
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CV1 CV1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CV

CV : Counter Value
bits : 0 - 31 (32 bit)
access : read-only


RA1

Register A (channel = 1)
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RA1 RA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RA

RA : Register A
bits : 0 - 31 (32 bit)
access : read-write


RB1

Register B (channel = 1)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RB1 RB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB

RB : Register B
bits : 0 - 31 (32 bit)
access : read-write


RC1

Register C (channel = 1)
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RC1 RC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RC

RC : Register C
bits : 0 - 31 (32 bit)
access : read-write


SR1

Status Register (channel = 1)
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR1 SR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COVFS LOVRS CPAS CPBS CPCS LDRAS LDRBS ETRGS CLKSTA MTIOA MTIOB

COVFS : Counter Overflow Status
bits : 0 - 0 (1 bit)
access : read-only

LOVRS : Load Overrun Status
bits : 1 - 1 (1 bit)
access : read-only

CPAS : RA Compare Status
bits : 2 - 2 (1 bit)
access : read-only

CPBS : RB Compare Status
bits : 3 - 3 (1 bit)
access : read-only

CPCS : RC Compare Status
bits : 4 - 4 (1 bit)
access : read-only

LDRAS : RA Loading Status
bits : 5 - 5 (1 bit)
access : read-only

LDRBS : RB Loading Status
bits : 6 - 6 (1 bit)
access : read-only

ETRGS : External Trigger Status
bits : 7 - 7 (1 bit)
access : read-only

CLKSTA : Clock Enabling Status
bits : 16 - 16 (1 bit)
access : read-only

MTIOA : TIOA Mirror
bits : 17 - 17 (1 bit)
access : read-only

MTIOB : TIOB Mirror
bits : 18 - 18 (1 bit)
access : read-only


IER1

Interrupt Enable Register (channel = 1)
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER1 IER1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COVFS LOVRS CPAS CPBS CPCS LDRAS LDRBS ETRGS

COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : write-only

LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : write-only

CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : write-only

CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : write-only

CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : write-only

LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : write-only

LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : write-only

ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : write-only


IDR1

Interrupt Disable Register (channel = 1)
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR1 IDR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COVFS LOVRS CPAS CPBS CPCS LDRAS LDRBS ETRGS

COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : write-only

LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : write-only

CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : write-only

CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : write-only

CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : write-only

LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : write-only

LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : write-only

ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : write-only


IMR1

Interrupt Mask Register (channel = 1)
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR1 IMR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COVFS LOVRS CPAS CPBS CPCS LDRAS LDRBS ETRGS

COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : read-only

LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : read-only

CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : read-only

CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : read-only

CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : read-only

LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : read-only

LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : read-only

ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : read-only


SMMR0

Stepper Motor Mode Register (channel = 0)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMMR0 SMMR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GCEN DOWN

GCEN : Gray Count Enable
bits : 0 - 0 (1 bit)
access : read-write

DOWN : DOWN Count
bits : 1 - 1 (1 bit)
access : read-write


CCR2

Channel Control Register (channel = 2)
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CCR2 CCR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKEN CLKDIS SWTRG

CLKEN : Counter Clock Enable Command
bits : 0 - 0 (1 bit)
access : write-only

CLKDIS : Counter Clock Disable Command
bits : 1 - 1 (1 bit)
access : write-only

SWTRG : Software Trigger Command
bits : 2 - 2 (1 bit)
access : write-only


CMR2

Channel Mode Register (channel = 2)
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR2 CMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCCLKS CLKI BURST LDBSTOP LDBDIS ETRGEDG ABETRG CPCTRG WAVE LDRA LDRB

TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : TIMER_CLOCK1

Clock selected: TCLK1

0x1 : TIMER_CLOCK2

Clock selected: TCLK2

0x2 : TIMER_CLOCK3

Clock selected: TCLK3

0x3 : TIMER_CLOCK4

Clock selected: TCLK4

0x4 : TIMER_CLOCK5

Clock selected: TCLK5

0x5 : XC0

Clock selected: XC0

0x6 : XC1

Clock selected: XC1

0x7 : XC2

Clock selected: XC2

End of enumeration elements list.

CLKI : Clock Invert
bits : 3 - 3 (1 bit)
access : read-write

BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

The clock is not gated by an external signal.

0x1 : XC0

XC0 is ANDed with the selected clock.

0x2 : XC1

XC1 is ANDed with the selected clock.

0x3 : XC2

XC2 is ANDed with the selected clock.

End of enumeration elements list.

LDBSTOP : Counter Clock Stopped with RB Loading
bits : 6 - 6 (1 bit)
access : read-write

LDBDIS : Counter Clock Disable with RB Loading
bits : 7 - 7 (1 bit)
access : read-write

ETRGEDG : External Trigger Edge Selection
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

The clock is not gated by an external signal.

0x1 : RISING

Rising edge

0x2 : FALLING

Falling edge

0x3 : EDGE

Each edge

End of enumeration elements list.

ABETRG : TIOA or TIOB External Trigger Selection
bits : 10 - 10 (1 bit)
access : read-write

CPCTRG : RC Compare Trigger Enable
bits : 14 - 14 (1 bit)
access : read-write

WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
access : read-write

LDRA : RA Loading Edge Selection
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : RISING

Rising edge of TIOA

0x2 : FALLING

Falling edge of TIOA

0x3 : EDGE

Each edge of TIOA

End of enumeration elements list.

LDRB : RB Loading Edge Selection
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : RISING

Rising edge of TIOA

0x2 : FALLING

Falling edge of TIOA

0x3 : EDGE

Each edge of TIOA

End of enumeration elements list.


CMR2_WAVE_EQ_1

Channel Mode Register (channel = 2)
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : WAVE_EQ_1
reset_Mask : 0x0

CMR2_WAVE_EQ_1 CMR2_WAVE_EQ_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCCLKS CLKI BURST CPCSTOP CPCDIS EEVTEDG EEVT ENETRG WAVSEL WAVE ACPA ACPC AEEVT ASWTRG BCPB BCPC BEEVT BSWTRG

TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : TIMER_CLOCK1

Clock selected: TCLK1

0x1 : TIMER_CLOCK2

Clock selected: TCLK2

0x2 : TIMER_CLOCK3

Clock selected: TCLK3

0x3 : TIMER_CLOCK4

Clock selected: TCLK4

0x4 : TIMER_CLOCK5

Clock selected: TCLK5

0x5 : XC0

Clock selected: XC0

0x6 : XC1

Clock selected: XC1

0x7 : XC2

Clock selected: XC2

End of enumeration elements list.

CLKI : Clock Invert
bits : 3 - 3 (1 bit)
access : read-write

BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

The clock is not gated by an external signal.

0x1 : XC0

XC0 is ANDed with the selected clock.

0x2 : XC1

XC1 is ANDed with the selected clock.

0x3 : XC2

XC2 is ANDed with the selected clock.

End of enumeration elements list.

CPCSTOP : Counter Clock Stopped with RC Compare
bits : 6 - 6 (1 bit)
access : read-write

CPCDIS : Counter Clock Disable with RC Compare
bits : 7 - 7 (1 bit)
access : read-write

EEVTEDG : External Event Edge Selection
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : RISING

Rising edge

0x2 : FALLING

Falling edge

0x3 : EDGE

Each edge

End of enumeration elements list.

EEVT : External Event Selection
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

0x0 : TIOB

TIOB

0x1 : XC0

XC0

0x2 : XC1

XC1

0x3 : XC2

XC2

End of enumeration elements list.

ENETRG : External Event Trigger Enable
bits : 12 - 12 (1 bit)
access : read-write

WAVSEL : Waveform Selection
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

0x0 : UP

UP mode without automatic trigger on RC Compare

0x1 : UPDOWN

UPDOWN mode without automatic trigger on RC Compare

0x2 : UP_RC

UP mode with automatic trigger on RC Compare

0x3 : UPDOWN_RC

UPDOWN mode with automatic trigger on RC Compare

End of enumeration elements list.

WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
access : read-write

ACPA : RA Compare Effect on TIOA
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

ACPC : RC Compare Effect on TIOA
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

AEEVT : External Event Effect on TIOA
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

ASWTRG : Software Trigger Effect on TIOA
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

BCPB : RB Compare Effect on TIOB
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

BCPC : RC Compare Effect on TIOB
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

BEEVT : External Event Effect on TIOB
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.

BSWTRG : Software Trigger Effect on TIOB
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

None

0x1 : SET

Set

0x2 : CLEAR

Clear

0x3 : TOGGLE

Toggle

End of enumeration elements list.


SMMR2

Stepper Motor Mode Register (channel = 2)
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMMR2 SMMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GCEN DOWN

GCEN : Gray Count Enable
bits : 0 - 0 (1 bit)
access : read-write

DOWN : DOWN Count
bits : 1 - 1 (1 bit)
access : read-write


RAB2

Register AB (channel = 2)
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAB2 RAB2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAB

RAB : Register A or Register B
bits : 0 - 31 (32 bit)
access : read-only


CV2

Counter Value (channel = 2)
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CV2 CV2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CV

CV : Counter Value
bits : 0 - 31 (32 bit)
access : read-only


RA2

Register A (channel = 2)
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RA2 RA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RA

RA : Register A
bits : 0 - 31 (32 bit)
access : read-write


RB2

Register B (channel = 2)
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RB2 RB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB

RB : Register B
bits : 0 - 31 (32 bit)
access : read-write


RC2

Register C (channel = 2)
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RC2 RC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RC

RC : Register C
bits : 0 - 31 (32 bit)
access : read-write


SR2

Status Register (channel = 2)
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR2 SR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COVFS LOVRS CPAS CPBS CPCS LDRAS LDRBS ETRGS CLKSTA MTIOA MTIOB

COVFS : Counter Overflow Status
bits : 0 - 0 (1 bit)
access : read-only

LOVRS : Load Overrun Status
bits : 1 - 1 (1 bit)
access : read-only

CPAS : RA Compare Status
bits : 2 - 2 (1 bit)
access : read-only

CPBS : RB Compare Status
bits : 3 - 3 (1 bit)
access : read-only

CPCS : RC Compare Status
bits : 4 - 4 (1 bit)
access : read-only

LDRAS : RA Loading Status
bits : 5 - 5 (1 bit)
access : read-only

LDRBS : RB Loading Status
bits : 6 - 6 (1 bit)
access : read-only

ETRGS : External Trigger Status
bits : 7 - 7 (1 bit)
access : read-only

CLKSTA : Clock Enabling Status
bits : 16 - 16 (1 bit)
access : read-only

MTIOA : TIOA Mirror
bits : 17 - 17 (1 bit)
access : read-only

MTIOB : TIOB Mirror
bits : 18 - 18 (1 bit)
access : read-only


IER2

Interrupt Enable Register (channel = 2)
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER2 IER2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COVFS LOVRS CPAS CPBS CPCS LDRAS LDRBS ETRGS

COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : write-only

LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : write-only

CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : write-only

CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : write-only

CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : write-only

LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : write-only

LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : write-only

ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : write-only


IDR2

Interrupt Disable Register (channel = 2)
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR2 IDR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COVFS LOVRS CPAS CPBS CPCS LDRAS LDRBS ETRGS

COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : write-only

LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : write-only

CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : write-only

CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : write-only

CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : write-only

LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : write-only

LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : write-only

ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : write-only


IMR2

Interrupt Mask Register (channel = 2)
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR2 IMR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COVFS LOVRS CPAS CPBS CPCS LDRAS LDRBS ETRGS

COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : read-only

LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : read-only

CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : read-only

CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : read-only

CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : read-only

LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : read-only

LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : read-only

ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : read-only


RAB0

Register AB (channel = 0)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAB0 RAB0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAB

RAB : Register A or Register B
bits : 0 - 31 (32 bit)
access : read-only


BCR

Block Control Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

BCR BCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNC

SYNC : Synchro Command
bits : 0 - 0 (1 bit)
access : write-only


BMR

Block Mode Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BMR BMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC0XC0S TC1XC1S TC2XC2S QDEN POSEN SPEEDEN QDTRANS EDGPHA INVA INVB INVIDX SWAP IDXPHB FILTER MAXFILT

TC0XC0S : External Clock Signal 0 Selection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : TCLK0

Signal connected to XC0: TCLK0

0x2 : TIOA1

Signal connected to XC0: TIOA1

0x3 : TIOA2

Signal connected to XC0: TIOA2

End of enumeration elements list.

TC1XC1S : External Clock Signal 1 Selection
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : TCLK1

Signal connected to XC1: TCLK1

0x2 : TIOA0

Signal connected to XC1: TIOA0

0x3 : TIOA2

Signal connected to XC1: TIOA2

End of enumeration elements list.

TC2XC2S : External Clock Signal 2 Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : TCLK2

Signal connected to XC2: TCLK2

0x2 : TIOA1

Signal connected to XC2: TIOA1

0x3 : TIOA2

Signal connected to XC2: TIOA2

End of enumeration elements list.

QDEN : Quadrature Decoder ENabled
bits : 8 - 8 (1 bit)
access : read-write

POSEN : POSition ENabled
bits : 9 - 9 (1 bit)
access : read-write

SPEEDEN : SPEED ENabled
bits : 10 - 10 (1 bit)
access : read-write

QDTRANS : Quadrature Decoding TRANSparent
bits : 11 - 11 (1 bit)
access : read-write

EDGPHA : EDGe on PHA count mode
bits : 12 - 12 (1 bit)
access : read-write

INVA : INVerted phA
bits : 13 - 13 (1 bit)
access : read-write

INVB : INVerted phB
bits : 14 - 14 (1 bit)
access : read-write

INVIDX : INVerted InDeX
bits : 15 - 15 (1 bit)
access : read-write

SWAP : SWAP PHA and PHB
bits : 16 - 16 (1 bit)
access : read-write

IDXPHB : InDeX pin is PHB pin
bits : 17 - 17 (1 bit)
access : read-write

FILTER :
bits : 19 - 19 (1 bit)
access : read-write

MAXFILT : MAXimum FILTer
bits : 20 - 25 (6 bit)
access : read-write


QIER

QDEC Interrupt Enable Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

QIER QIER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDX DIRCHG QERR

IDX : InDeX
bits : 0 - 0 (1 bit)
access : write-only

DIRCHG : DIRection CHanGe
bits : 1 - 1 (1 bit)
access : write-only

QERR : Quadrature ERRor
bits : 2 - 2 (1 bit)
access : write-only


QIDR

QDEC Interrupt Disable Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

QIDR QIDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDX DIRCHG QERR

IDX : InDeX
bits : 0 - 0 (1 bit)
access : write-only

DIRCHG : DIRection CHanGe
bits : 1 - 1 (1 bit)
access : write-only

QERR : Quadrature ERRor
bits : 2 - 2 (1 bit)
access : write-only


QIMR

QDEC Interrupt Mask Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

QIMR QIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDX DIRCHG QERR

IDX : InDeX
bits : 0 - 0 (1 bit)
access : read-only

DIRCHG : DIRection CHanGe
bits : 1 - 1 (1 bit)
access : read-only

QERR : Quadrature ERRor
bits : 2 - 2 (1 bit)
access : read-only


QISR

QDEC Interrupt Status Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

QISR QISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDX DIRCHG QERR DIR

IDX : InDeX
bits : 0 - 0 (1 bit)
access : read-only

DIRCHG : DIRection CHanGe
bits : 1 - 1 (1 bit)
access : read-only

QERR : Quadrature ERRor
bits : 2 - 2 (1 bit)
access : read-only

DIR : DIRection
bits : 8 - 8 (1 bit)
access : read-only


WPMR

Write Protect Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protect KEY
bits : 8 - 31 (24 bit)
access : read-write



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