Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
DMAC Global Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARB_CFG : Arbiter Configuration
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : FIXED
Fixed priority arbiter.
1 : ROUND_ROBIN
Modified round robin arbiter.
End of enumeration elements list.
DICEN : Descriptor Integrity Check
bits : 8 - 8 (1 bit)
access : read-write
DMAC Software Last Transfer Flag Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST0 : Source Last
bits : 0 - 0 (1 bit)
access : read-write
DLAST0 : Destination Last
bits : 1 - 1 (1 bit)
access : read-write
SLAST1 : Source Last
bits : 2 - 2 (1 bit)
access : read-write
DLAST1 : Destination Last
bits : 3 - 3 (1 bit)
access : read-write
SLAST2 : Source Last
bits : 4 - 4 (1 bit)
access : read-write
DLAST2 : Destination Last
bits : 5 - 5 (1 bit)
access : read-write
SLAST3 : Source Last
bits : 6 - 6 (1 bit)
access : read-write
DLAST3 : Destination Last
bits : 7 - 7 (1 bit)
access : read-write
SLAST4 : Source Last
bits : 8 - 8 (1 bit)
access : read-write
DLAST4 : Destination Last
bits : 9 - 9 (1 bit)
access : read-write
SLAST5 : Source Last
bits : 10 - 10 (1 bit)
access : read-write
DLAST5 : Destination Last
bits : 11 - 11 (1 bit)
access : read-write
SLAST6 : Source Last
bits : 12 - 12 (1 bit)
access : read-write
DLAST6 : Destination Last
bits : 13 - 13 (1 bit)
access : read-write
SLAST7 : Source Last
bits : 14 - 14 (1 bit)
access : read-write
DLAST7 : Destination Last
bits : 15 - 15 (1 bit)
access : read-write
DMAC Channel Source Address Register (ch_num = 5)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel Destination Address Register (ch_num = 5)
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel Descriptor Address Register (ch_num = 5)
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSCR_IF : Descriptor Interface Selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The buffer transfer descriptor is fetched via AHB-Lite Interface 0
0x1 : AHB_IF1
The buffer transfer descriptor is fetched via AHB-Lite Interface 1
0x2 : AHB_IF2
The buffer transfer descriptor is fetched via AHB-Lite Interface 2
End of enumeration elements list.
DSCR : Buffer Transfer Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
DMAC Channel Control A Register (ch_num = 5)
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTSIZE : Buffer Transfer Size
bits : 0 - 15 (16 bit)
access : read-write
SCSIZE : Source Chunk Transfer Size.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_4
4 data transferred
0x2 : CHK_8
8 data transferred
0x3 : CHK_16
16 data transferred
End of enumeration elements list.
DCSIZE : Destination Chunk Transfer Size
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_4
4 data transferred
0x2 : CHK_8
8 data transferred
0x3 : CHK_16
16 data transferred
End of enumeration elements list.
SRC_WIDTH : Transfer Width for the Source
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
the transfer size is set to 8-bit width
0x1 : HALF_WORD
the transfer size is set to 16-bit width
0x2 : WORD
the transfer size is set to 32-bit width
0x3 : DWORD
the transfer size is set to 64-bit width
End of enumeration elements list.
DST_WIDTH : Transfer Width for the Destination
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
the transfer size is set to 8-bit width
0x1 : HALF_WORD
the transfer size is set to 16-bit width
0x2 : WORD
the transfer size is set to 32-bit width
0x3 : DWORD
the transfer size is set to 64-bit width
End of enumeration elements list.
DONE : Current Descriptor Stop Command and Transfer Completed Memory Indicator
bits : 31 - 31 (1 bit)
access : read-write
DMAC Channel Control B Register (ch_num = 5)
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIF : Source Interface Selection Field
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The source transfer is done via AHB_Lite Interface 0
0x1 : AHB_IF1
The source transfer is done via AHB_Lite Interface 1
0x2 : AHB_IF2
The source transfer is done via AHB_Lite Interface 2
End of enumeration elements list.
DIF : Destination Interface Selection Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The destination transfer is done via AHB_Lite Interface 0
0x1 : AHB_IF1
The destination transfer is done via AHB_Lite Interface 1
0x2 : AHB_IF2
The destination transfer is done via AHB_Lite Interface 2
End of enumeration elements list.
SRC_PIP : Source Picture-in-Picture Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Picture-in-Picture mode is disabled. The source data area is contiguous.
1 : ENABLE
Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is automatically incremented by a user defined amount.
End of enumeration elements list.
DST_PIP : Destination Picture-in-Picture Mode
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Picture-in-Picture mode is disabled. The Destination data area is contiguous.
1 : ENABLE
Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address is automatically incremented by a user-defined amount.
End of enumeration elements list.
SRC_DSCR : Source Address Descriptor
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : FETCH_FROM_MEM
Source address is updated when the descriptor is fetched from the memory.
1 : FETCH_DISABLE
Buffer Descriptor Fetch operation is disabled for the source.
End of enumeration elements list.
DST_DSCR : Destination Address Descriptor
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : FETCH_FROM_MEM
Destination address is updated when the descriptor is fetched from the memory.
1 : FETCH_DISABLE
Buffer Descriptor Fetch operation is disabled for the destination.
End of enumeration elements list.
FC : Flow Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0x0 : MEM2MEM_DMA_FC
Memory-to-Memory Transfer DMAC is flow controller
0x1 : MEM2PER_DMA_FC
Memory-to-Peripheral Transfer DMAC is flow controller
0x2 : PER2MEM_DMA_FC
Peripheral-to-Memory Transfer DMAC is flow controller
0x3 : PER2PER_DMA_FC
Peripheral-to-Peripheral Transfer DMAC is flow controller
End of enumeration elements list.
SRC_INCR : Incrementing, Decrementing or Fixed Address for the Source
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : INCREMENTING
The source address is incremented
0x1 : DECREMENTING
The source address is decremented
0x2 : FIXED
The source address remains unchanged
End of enumeration elements list.
DST_INCR : Incrementing, Decrementing or Fixed Address for the Destination
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : INCREMENTING
The destination address is incremented
0x1 : DECREMENTING
The destination address is decremented
0x2 : FIXED
The destination address remains unchanged
End of enumeration elements list.
IEN : Interrupt Enable Not
bits : 30 - 30 (1 bit)
access : read-write
AUTO : Automatic Multiple Buffer Transfer
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic multiple buffer transfer is disabled.
1 : ENABLE
Automatic multiple buffer transfer is enabled. This bit enables replay mode or contiguous mode when several buffers are transferred.
End of enumeration elements list.
DMAC Channel Configuration Register (ch_num = 5)
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_PER : Source with Peripheral identifier
bits : 0 - 3 (4 bit)
access : read-write
DST_PER : Destination with Peripheral identifier
bits : 4 - 7 (4 bit)
access : read-write
SRC_REP : Source Reloaded from Previous
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CONTIGUOUS_ADDR
When automatic mode is activated, source address is contiguous between two buffers.
1 : RELOAD_ADDR
When automatic mode is activated, the source address and the control register are reloaded from previous transfer.
End of enumeration elements list.
SRC_H2SEL : Software or Hardware Selection for the Source
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SW
Software handshaking interface is used to trigger a transfer request.
1 : HW
Hardware handshaking interface is used to trigger a transfer request.
End of enumeration elements list.
SRC_PER_MSB : SRC_PER Most Significant Bits
bits : 10 - 11 (2 bit)
access : read-write
DST_REP : Destination Reloaded from Previous
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : CONTIGUOUS_ADDR
When automatic mode is activated, destination address is contiguous between two buffers.
1 : RELOAD_ADDR
When automatic mode is activated, the destination and the control register are reloaded from the pre-vious transfer.
End of enumeration elements list.
DST_H2SEL : Software or Hardware Selection for the Destination
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SW
Software handshaking interface is used to trigger a transfer request.
1 : HW
Hardware handshaking interface is used to trigger a transfer request.
End of enumeration elements list.
DST_PER_MSB : DST_PER Most Significant Bits
bits : 14 - 15 (2 bit)
access : read-write
SOD : Stop On Done
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
1 : ENABLE
STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
End of enumeration elements list.
LOCK_IF : Interface Lock
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Interface Lock capability is disabled
1 : ENABLE
Interface Lock capability is enabled
End of enumeration elements list.
LOCK_B : Bus Lock
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
AHB Bus Locking capability is disabled.
End of enumeration elements list.
LOCK_IF_L : Master Interface Arbiter Lock
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : CHUNK
The Master Interface Arbiter is locked by the channel x for a chunk transfer.
1 : BUFFER
The Master Interface Arbiter is locked by the channel x for a buffer transfer.
End of enumeration elements list.
AHB_PROT : AHB Protection
bits : 24 - 26 (3 bit)
access : read-write
FIFOCFG : FIFO Configuration
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : ALAP_CFG
The largest defined length AHB burst is performed on the destination AHB interface.
0x1 : HALF_CFG
When half FIFO size is available/filled, a source/destination request is serviced.
0x2 : ASAP_CFG
When there is enough space/data available to perform a single AHB access, then the request is serviced.
End of enumeration elements list.
DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 5)
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIP_HOLE : Source Picture-in-Picture Hole
bits : 0 - 15 (16 bit)
access : read-write
SPIP_BOUNDARY : Source Picture-in-Picture Boundary
bits : 16 - 25 (10 bit)
access : read-write
DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 5)
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPIP_HOLE : Destination Picture-in-Picture Hole
bits : 0 - 15 (16 bit)
access : read-write
DPIP_BOUNDARY : Destination Picture-in-Picture Boundary
bits : 16 - 25 (10 bit)
access : read-write
DMAC Channel Source Address Register (ch_num = 6)
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel Destination Address Register (ch_num = 6)
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel Descriptor Address Register (ch_num = 6)
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSCR_IF : Descriptor Interface Selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The buffer transfer descriptor is fetched via AHB-Lite Interface 0
0x1 : AHB_IF1
The buffer transfer descriptor is fetched via AHB-Lite Interface 1
0x2 : AHB_IF2
The buffer transfer descriptor is fetched via AHB-Lite Interface 2
End of enumeration elements list.
DSCR : Buffer Transfer Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
DMAC Channel Control A Register (ch_num = 6)
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTSIZE : Buffer Transfer Size
bits : 0 - 15 (16 bit)
access : read-write
SCSIZE : Source Chunk Transfer Size.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_4
4 data transferred
0x2 : CHK_8
8 data transferred
0x3 : CHK_16
16 data transferred
End of enumeration elements list.
DCSIZE : Destination Chunk Transfer Size
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_4
4 data transferred
0x2 : CHK_8
8 data transferred
0x3 : CHK_16
16 data transferred
End of enumeration elements list.
SRC_WIDTH : Transfer Width for the Source
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
the transfer size is set to 8-bit width
0x1 : HALF_WORD
the transfer size is set to 16-bit width
0x2 : WORD
the transfer size is set to 32-bit width
0x3 : DWORD
the transfer size is set to 64-bit width
End of enumeration elements list.
DST_WIDTH : Transfer Width for the Destination
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
the transfer size is set to 8-bit width
0x1 : HALF_WORD
the transfer size is set to 16-bit width
0x2 : WORD
the transfer size is set to 32-bit width
0x3 : DWORD
the transfer size is set to 64-bit width
End of enumeration elements list.
DONE : Current Descriptor Stop Command and Transfer Completed Memory Indicator
bits : 31 - 31 (1 bit)
access : read-write
DMAC Channel Control B Register (ch_num = 6)
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIF : Source Interface Selection Field
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The source transfer is done via AHB_Lite Interface 0
0x1 : AHB_IF1
The source transfer is done via AHB_Lite Interface 1
0x2 : AHB_IF2
The source transfer is done via AHB_Lite Interface 2
End of enumeration elements list.
DIF : Destination Interface Selection Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The destination transfer is done via AHB_Lite Interface 0
0x1 : AHB_IF1
The destination transfer is done via AHB_Lite Interface 1
0x2 : AHB_IF2
The destination transfer is done via AHB_Lite Interface 2
End of enumeration elements list.
SRC_PIP : Source Picture-in-Picture Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Picture-in-Picture mode is disabled. The source data area is contiguous.
1 : ENABLE
Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is automatically incremented by a user defined amount.
End of enumeration elements list.
DST_PIP : Destination Picture-in-Picture Mode
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Picture-in-Picture mode is disabled. The Destination data area is contiguous.
1 : ENABLE
Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address is automatically incremented by a user-defined amount.
End of enumeration elements list.
SRC_DSCR : Source Address Descriptor
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : FETCH_FROM_MEM
Source address is updated when the descriptor is fetched from the memory.
1 : FETCH_DISABLE
Buffer Descriptor Fetch operation is disabled for the source.
End of enumeration elements list.
DST_DSCR : Destination Address Descriptor
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : FETCH_FROM_MEM
Destination address is updated when the descriptor is fetched from the memory.
1 : FETCH_DISABLE
Buffer Descriptor Fetch operation is disabled for the destination.
End of enumeration elements list.
FC : Flow Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0x0 : MEM2MEM_DMA_FC
Memory-to-Memory Transfer DMAC is flow controller
0x1 : MEM2PER_DMA_FC
Memory-to-Peripheral Transfer DMAC is flow controller
0x2 : PER2MEM_DMA_FC
Peripheral-to-Memory Transfer DMAC is flow controller
0x3 : PER2PER_DMA_FC
Peripheral-to-Peripheral Transfer DMAC is flow controller
End of enumeration elements list.
SRC_INCR : Incrementing, Decrementing or Fixed Address for the Source
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : INCREMENTING
The source address is incremented
0x1 : DECREMENTING
The source address is decremented
0x2 : FIXED
The source address remains unchanged
End of enumeration elements list.
DST_INCR : Incrementing, Decrementing or Fixed Address for the Destination
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : INCREMENTING
The destination address is incremented
0x1 : DECREMENTING
The destination address is decremented
0x2 : FIXED
The destination address remains unchanged
End of enumeration elements list.
IEN : Interrupt Enable Not
bits : 30 - 30 (1 bit)
access : read-write
AUTO : Automatic Multiple Buffer Transfer
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic multiple buffer transfer is disabled.
1 : ENABLE
Automatic multiple buffer transfer is enabled. This bit enables replay mode or contiguous mode when several buffers are transferred.
End of enumeration elements list.
DMAC Channel Configuration Register (ch_num = 6)
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_PER : Source with Peripheral identifier
bits : 0 - 3 (4 bit)
access : read-write
DST_PER : Destination with Peripheral identifier
bits : 4 - 7 (4 bit)
access : read-write
SRC_REP : Source Reloaded from Previous
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CONTIGUOUS_ADDR
When automatic mode is activated, source address is contiguous between two buffers.
1 : RELOAD_ADDR
When automatic mode is activated, the source address and the control register are reloaded from previous transfer.
End of enumeration elements list.
SRC_H2SEL : Software or Hardware Selection for the Source
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SW
Software handshaking interface is used to trigger a transfer request.
1 : HW
Hardware handshaking interface is used to trigger a transfer request.
End of enumeration elements list.
SRC_PER_MSB : SRC_PER Most Significant Bits
bits : 10 - 11 (2 bit)
access : read-write
DST_REP : Destination Reloaded from Previous
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : CONTIGUOUS_ADDR
When automatic mode is activated, destination address is contiguous between two buffers.
1 : RELOAD_ADDR
When automatic mode is activated, the destination and the control register are reloaded from the pre-vious transfer.
End of enumeration elements list.
DST_H2SEL : Software or Hardware Selection for the Destination
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SW
Software handshaking interface is used to trigger a transfer request.
1 : HW
Hardware handshaking interface is used to trigger a transfer request.
End of enumeration elements list.
DST_PER_MSB : DST_PER Most Significant Bits
bits : 14 - 15 (2 bit)
access : read-write
SOD : Stop On Done
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
1 : ENABLE
STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
End of enumeration elements list.
LOCK_IF : Interface Lock
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Interface Lock capability is disabled
1 : ENABLE
Interface Lock capability is enabled
End of enumeration elements list.
LOCK_B : Bus Lock
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
AHB Bus Locking capability is disabled.
End of enumeration elements list.
LOCK_IF_L : Master Interface Arbiter Lock
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : CHUNK
The Master Interface Arbiter is locked by the channel x for a chunk transfer.
1 : BUFFER
The Master Interface Arbiter is locked by the channel x for a buffer transfer.
End of enumeration elements list.
AHB_PROT : AHB Protection
bits : 24 - 26 (3 bit)
access : read-write
FIFOCFG : FIFO Configuration
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : ALAP_CFG
The largest defined length AHB burst is performed on the destination AHB interface.
0x1 : HALF_CFG
When half FIFO size is available/filled, a source/destination request is serviced.
0x2 : ASAP_CFG
When there is enough space/data available to perform a single AHB access, then the request is serviced.
End of enumeration elements list.
DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 6)
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIP_HOLE : Source Picture-in-Picture Hole
bits : 0 - 15 (16 bit)
access : read-write
SPIP_BOUNDARY : Source Picture-in-Picture Boundary
bits : 16 - 25 (10 bit)
access : read-write
DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 6)
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPIP_HOLE : Destination Picture-in-Picture Hole
bits : 0 - 15 (16 bit)
access : read-write
DPIP_BOUNDARY : Destination Picture-in-Picture Boundary
bits : 16 - 25 (10 bit)
access : read-write
DMAC Channel Source Address Register (ch_num = 7)
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel Destination Address Register (ch_num = 7)
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel Descriptor Address Register (ch_num = 7)
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSCR_IF : Descriptor Interface Selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The buffer transfer descriptor is fetched via AHB-Lite Interface 0
0x1 : AHB_IF1
The buffer transfer descriptor is fetched via AHB-Lite Interface 1
0x2 : AHB_IF2
The buffer transfer descriptor is fetched via AHB-Lite Interface 2
End of enumeration elements list.
DSCR : Buffer Transfer Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
DMAC Channel Control A Register (ch_num = 7)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTSIZE : Buffer Transfer Size
bits : 0 - 15 (16 bit)
access : read-write
SCSIZE : Source Chunk Transfer Size.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_4
4 data transferred
0x2 : CHK_8
8 data transferred
0x3 : CHK_16
16 data transferred
End of enumeration elements list.
DCSIZE : Destination Chunk Transfer Size
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_4
4 data transferred
0x2 : CHK_8
8 data transferred
0x3 : CHK_16
16 data transferred
End of enumeration elements list.
SRC_WIDTH : Transfer Width for the Source
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
the transfer size is set to 8-bit width
0x1 : HALF_WORD
the transfer size is set to 16-bit width
0x2 : WORD
the transfer size is set to 32-bit width
0x3 : DWORD
the transfer size is set to 64-bit width
End of enumeration elements list.
DST_WIDTH : Transfer Width for the Destination
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
the transfer size is set to 8-bit width
0x1 : HALF_WORD
the transfer size is set to 16-bit width
0x2 : WORD
the transfer size is set to 32-bit width
0x3 : DWORD
the transfer size is set to 64-bit width
End of enumeration elements list.
DONE : Current Descriptor Stop Command and Transfer Completed Memory Indicator
bits : 31 - 31 (1 bit)
access : read-write
DMAC Channel Control B Register (ch_num = 7)
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIF : Source Interface Selection Field
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The source transfer is done via AHB_Lite Interface 0
0x1 : AHB_IF1
The source transfer is done via AHB_Lite Interface 1
0x2 : AHB_IF2
The source transfer is done via AHB_Lite Interface 2
End of enumeration elements list.
DIF : Destination Interface Selection Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The destination transfer is done via AHB_Lite Interface 0
0x1 : AHB_IF1
The destination transfer is done via AHB_Lite Interface 1
0x2 : AHB_IF2
The destination transfer is done via AHB_Lite Interface 2
End of enumeration elements list.
SRC_PIP : Source Picture-in-Picture Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Picture-in-Picture mode is disabled. The source data area is contiguous.
1 : ENABLE
Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is automatically incremented by a user defined amount.
End of enumeration elements list.
DST_PIP : Destination Picture-in-Picture Mode
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Picture-in-Picture mode is disabled. The Destination data area is contiguous.
1 : ENABLE
Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address is automatically incremented by a user-defined amount.
End of enumeration elements list.
SRC_DSCR : Source Address Descriptor
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : FETCH_FROM_MEM
Source address is updated when the descriptor is fetched from the memory.
1 : FETCH_DISABLE
Buffer Descriptor Fetch operation is disabled for the source.
End of enumeration elements list.
DST_DSCR : Destination Address Descriptor
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : FETCH_FROM_MEM
Destination address is updated when the descriptor is fetched from the memory.
1 : FETCH_DISABLE
Buffer Descriptor Fetch operation is disabled for the destination.
End of enumeration elements list.
FC : Flow Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0x0 : MEM2MEM_DMA_FC
Memory-to-Memory Transfer DMAC is flow controller
0x1 : MEM2PER_DMA_FC
Memory-to-Peripheral Transfer DMAC is flow controller
0x2 : PER2MEM_DMA_FC
Peripheral-to-Memory Transfer DMAC is flow controller
0x3 : PER2PER_DMA_FC
Peripheral-to-Peripheral Transfer DMAC is flow controller
End of enumeration elements list.
SRC_INCR : Incrementing, Decrementing or Fixed Address for the Source
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : INCREMENTING
The source address is incremented
0x1 : DECREMENTING
The source address is decremented
0x2 : FIXED
The source address remains unchanged
End of enumeration elements list.
DST_INCR : Incrementing, Decrementing or Fixed Address for the Destination
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : INCREMENTING
The destination address is incremented
0x1 : DECREMENTING
The destination address is decremented
0x2 : FIXED
The destination address remains unchanged
End of enumeration elements list.
IEN : Interrupt Enable Not
bits : 30 - 30 (1 bit)
access : read-write
AUTO : Automatic Multiple Buffer Transfer
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic multiple buffer transfer is disabled.
1 : ENABLE
Automatic multiple buffer transfer is enabled. This bit enables replay mode or contiguous mode when several buffers are transferred.
End of enumeration elements list.
DMAC Channel Configuration Register (ch_num = 7)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_PER : Source with Peripheral identifier
bits : 0 - 3 (4 bit)
access : read-write
DST_PER : Destination with Peripheral identifier
bits : 4 - 7 (4 bit)
access : read-write
SRC_REP : Source Reloaded from Previous
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CONTIGUOUS_ADDR
When automatic mode is activated, source address is contiguous between two buffers.
1 : RELOAD_ADDR
When automatic mode is activated, the source address and the control register are reloaded from previous transfer.
End of enumeration elements list.
SRC_H2SEL : Software or Hardware Selection for the Source
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SW
Software handshaking interface is used to trigger a transfer request.
1 : HW
Hardware handshaking interface is used to trigger a transfer request.
End of enumeration elements list.
SRC_PER_MSB : SRC_PER Most Significant Bits
bits : 10 - 11 (2 bit)
access : read-write
DST_REP : Destination Reloaded from Previous
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : CONTIGUOUS_ADDR
When automatic mode is activated, destination address is contiguous between two buffers.
1 : RELOAD_ADDR
When automatic mode is activated, the destination and the control register are reloaded from the pre-vious transfer.
End of enumeration elements list.
DST_H2SEL : Software or Hardware Selection for the Destination
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SW
Software handshaking interface is used to trigger a transfer request.
1 : HW
Hardware handshaking interface is used to trigger a transfer request.
End of enumeration elements list.
DST_PER_MSB : DST_PER Most Significant Bits
bits : 14 - 15 (2 bit)
access : read-write
SOD : Stop On Done
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
1 : ENABLE
STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
End of enumeration elements list.
LOCK_IF : Interface Lock
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Interface Lock capability is disabled
1 : ENABLE
Interface Lock capability is enabled
End of enumeration elements list.
LOCK_B : Bus Lock
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
AHB Bus Locking capability is disabled.
End of enumeration elements list.
LOCK_IF_L : Master Interface Arbiter Lock
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : CHUNK
The Master Interface Arbiter is locked by the channel x for a chunk transfer.
1 : BUFFER
The Master Interface Arbiter is locked by the channel x for a buffer transfer.
End of enumeration elements list.
AHB_PROT : AHB Protection
bits : 24 - 26 (3 bit)
access : read-write
FIFOCFG : FIFO Configuration
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : ALAP_CFG
The largest defined length AHB burst is performed on the destination AHB interface.
0x1 : HALF_CFG
When half FIFO size is available/filled, a source/destination request is serviced.
0x2 : ASAP_CFG
When there is enough space/data available to perform a single AHB access, then the request is serviced.
End of enumeration elements list.
DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 7)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIP_HOLE : Source Picture-in-Picture Hole
bits : 0 - 15 (16 bit)
access : read-write
SPIP_BOUNDARY : Source Picture-in-Picture Boundary
bits : 16 - 25 (10 bit)
access : read-write
DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 7)
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPIP_HOLE : Destination Picture-in-Picture Hole
bits : 0 - 15 (16 bit)
access : read-write
DPIP_BOUNDARY : Destination Picture-in-Picture Boundary
bits : 16 - 25 (10 bit)
access : read-write
DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BTC0 : Buffer Transfer Completed [7:0]
bits : 0 - 0 (1 bit)
access : write-only
BTC1 : Buffer Transfer Completed [7:0]
bits : 1 - 1 (1 bit)
access : write-only
BTC2 : Buffer Transfer Completed [7:0]
bits : 2 - 2 (1 bit)
access : write-only
BTC3 : Buffer Transfer Completed [7:0]
bits : 3 - 3 (1 bit)
access : write-only
BTC4 : Buffer Transfer Completed [7:0]
bits : 4 - 4 (1 bit)
access : write-only
BTC5 : Buffer Transfer Completed [7:0]
bits : 5 - 5 (1 bit)
access : write-only
BTC6 : Buffer Transfer Completed [7:0]
bits : 6 - 6 (1 bit)
access : write-only
BTC7 : Buffer Transfer Completed [7:0]
bits : 7 - 7 (1 bit)
access : write-only
CBTC0 : Chained Buffer Transfer Completed [7:0]
bits : 8 - 8 (1 bit)
access : write-only
CBTC1 : Chained Buffer Transfer Completed [7:0]
bits : 9 - 9 (1 bit)
access : write-only
CBTC2 : Chained Buffer Transfer Completed [7:0]
bits : 10 - 10 (1 bit)
access : write-only
CBTC3 : Chained Buffer Transfer Completed [7:0]
bits : 11 - 11 (1 bit)
access : write-only
CBTC4 : Chained Buffer Transfer Completed [7:0]
bits : 12 - 12 (1 bit)
access : write-only
CBTC5 : Chained Buffer Transfer Completed [7:0]
bits : 13 - 13 (1 bit)
access : write-only
CBTC6 : Chained Buffer Transfer Completed [7:0]
bits : 14 - 14 (1 bit)
access : write-only
CBTC7 : Chained Buffer Transfer Completed [7:0]
bits : 15 - 15 (1 bit)
access : write-only
ERR0 : Access Error [7:0]
bits : 16 - 16 (1 bit)
access : write-only
ERR1 : Access Error [7:0]
bits : 17 - 17 (1 bit)
access : write-only
ERR2 : Access Error [7:0]
bits : 18 - 18 (1 bit)
access : write-only
ERR3 : Access Error [7:0]
bits : 19 - 19 (1 bit)
access : write-only
ERR4 : Access Error [7:0]
bits : 20 - 20 (1 bit)
access : write-only
ERR5 : Access Error [7:0]
bits : 21 - 21 (1 bit)
access : write-only
ERR6 : Access Error [7:0]
bits : 22 - 22 (1 bit)
access : write-only
ERR7 : Access Error [7:0]
bits : 23 - 23 (1 bit)
access : write-only
DICERR0 : Descriptor Integrity Check Error [7:0]
bits : 24 - 24 (1 bit)
access : write-only
DICERR1 : Descriptor Integrity Check Error [7:0]
bits : 25 - 25 (1 bit)
access : write-only
DICERR2 : Descriptor Integrity Check Error [7:0]
bits : 26 - 26 (1 bit)
access : write-only
DICERR3 : Descriptor Integrity Check Error [7:0]
bits : 27 - 27 (1 bit)
access : write-only
DICERR4 : Descriptor Integrity Check Error [7:0]
bits : 28 - 28 (1 bit)
access : write-only
DICERR5 : Descriptor Integrity Check Error [7:0]
bits : 29 - 29 (1 bit)
access : write-only
DICERR6 : Descriptor Integrity Check Error [7:0]
bits : 30 - 30 (1 bit)
access : write-only
DICERR7 : Descriptor Integrity Check Error [7:0]
bits : 31 - 31 (1 bit)
access : write-only
DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BTC0 : Buffer Transfer Completed [7:0]
bits : 0 - 0 (1 bit)
access : write-only
BTC1 : Buffer Transfer Completed [7:0]
bits : 1 - 1 (1 bit)
access : write-only
BTC2 : Buffer Transfer Completed [7:0]
bits : 2 - 2 (1 bit)
access : write-only
BTC3 : Buffer Transfer Completed [7:0]
bits : 3 - 3 (1 bit)
access : write-only
BTC4 : Buffer Transfer Completed [7:0]
bits : 4 - 4 (1 bit)
access : write-only
BTC5 : Buffer Transfer Completed [7:0]
bits : 5 - 5 (1 bit)
access : write-only
BTC6 : Buffer Transfer Completed [7:0]
bits : 6 - 6 (1 bit)
access : write-only
BTC7 : Buffer Transfer Completed [7:0]
bits : 7 - 7 (1 bit)
access : write-only
CBTC0 : Chained Buffer Transfer Completed [7:0]
bits : 8 - 8 (1 bit)
access : write-only
CBTC1 : Chained Buffer Transfer Completed [7:0]
bits : 9 - 9 (1 bit)
access : write-only
CBTC2 : Chained Buffer Transfer Completed [7:0]
bits : 10 - 10 (1 bit)
access : write-only
CBTC3 : Chained Buffer Transfer Completed [7:0]
bits : 11 - 11 (1 bit)
access : write-only
CBTC4 : Chained Buffer Transfer Completed [7:0]
bits : 12 - 12 (1 bit)
access : write-only
CBTC5 : Chained Buffer Transfer Completed [7:0]
bits : 13 - 13 (1 bit)
access : write-only
CBTC6 : Chained Buffer Transfer Completed [7:0]
bits : 14 - 14 (1 bit)
access : write-only
CBTC7 : Chained Buffer Transfer Completed [7:0]
bits : 15 - 15 (1 bit)
access : write-only
ERR0 : Access Error [7:0]
bits : 16 - 16 (1 bit)
access : write-only
ERR1 : Access Error [7:0]
bits : 17 - 17 (1 bit)
access : write-only
ERR2 : Access Error [7:0]
bits : 18 - 18 (1 bit)
access : write-only
ERR3 : Access Error [7:0]
bits : 19 - 19 (1 bit)
access : write-only
ERR4 : Access Error [7:0]
bits : 20 - 20 (1 bit)
access : write-only
ERR5 : Access Error [7:0]
bits : 21 - 21 (1 bit)
access : write-only
ERR6 : Access Error [7:0]
bits : 22 - 22 (1 bit)
access : write-only
ERR7 : Access Error [7:0]
bits : 23 - 23 (1 bit)
access : write-only
DICERR0 : Descriptor Integrity Check Error [7:0]
bits : 24 - 24 (1 bit)
access : write-only
DICERR1 : Descriptor Integrity Check Error [7:0]
bits : 25 - 25 (1 bit)
access : write-only
DICERR2 : Descriptor Integrity Check Error [7:0]
bits : 26 - 26 (1 bit)
access : write-only
DICERR3 : Descriptor Integrity Check Error [7:0]
bits : 27 - 27 (1 bit)
access : write-only
DICERR4 : Descriptor Integrity Check Error [7:0]
bits : 28 - 28 (1 bit)
access : write-only
DICERR5 : Descriptor Integrity Check Error [7:0]
bits : 29 - 29 (1 bit)
access : write-only
DICERR6 : Descriptor Integrity Check Error [7:0]
bits : 30 - 30 (1 bit)
access : write-only
DICERR7 : Descriptor Integrity Check Error [7:0]
bits : 31 - 31 (1 bit)
access : write-only
DMAC Write Protect Mode Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protect KEY
bits : 8 - 31 (24 bit)
access : read-write
DMAC Write Protect Status Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protect Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protect Violation Source
bits : 8 - 23 (16 bit)
access : read-only
DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BTC0 : Buffer Transfer Completed [7:0]
bits : 0 - 0 (1 bit)
access : read-only
BTC1 : Buffer Transfer Completed [7:0]
bits : 1 - 1 (1 bit)
access : read-only
BTC2 : Buffer Transfer Completed [7:0]
bits : 2 - 2 (1 bit)
access : read-only
BTC3 : Buffer Transfer Completed [7:0]
bits : 3 - 3 (1 bit)
access : read-only
BTC4 : Buffer Transfer Completed [7:0]
bits : 4 - 4 (1 bit)
access : read-only
BTC5 : Buffer Transfer Completed [7:0]
bits : 5 - 5 (1 bit)
access : read-only
BTC6 : Buffer Transfer Completed [7:0]
bits : 6 - 6 (1 bit)
access : read-only
BTC7 : Buffer Transfer Completed [7:0]
bits : 7 - 7 (1 bit)
access : read-only
CBTC0 : Chained Buffer Transfer Completed [7:0]
bits : 8 - 8 (1 bit)
access : read-only
CBTC1 : Chained Buffer Transfer Completed [7:0]
bits : 9 - 9 (1 bit)
access : read-only
CBTC2 : Chained Buffer Transfer Completed [7:0]
bits : 10 - 10 (1 bit)
access : read-only
CBTC3 : Chained Buffer Transfer Completed [7:0]
bits : 11 - 11 (1 bit)
access : read-only
CBTC4 : Chained Buffer Transfer Completed [7:0]
bits : 12 - 12 (1 bit)
access : read-only
CBTC5 : Chained Buffer Transfer Completed [7:0]
bits : 13 - 13 (1 bit)
access : read-only
CBTC6 : Chained Buffer Transfer Completed [7:0]
bits : 14 - 14 (1 bit)
access : read-only
CBTC7 : Chained Buffer Transfer Completed [7:0]
bits : 15 - 15 (1 bit)
access : read-only
ERR0 : Access Error [7:0]
bits : 16 - 16 (1 bit)
access : read-only
ERR1 : Access Error [7:0]
bits : 17 - 17 (1 bit)
access : read-only
ERR2 : Access Error [7:0]
bits : 18 - 18 (1 bit)
access : read-only
ERR3 : Access Error [7:0]
bits : 19 - 19 (1 bit)
access : read-only
ERR4 : Access Error [7:0]
bits : 20 - 20 (1 bit)
access : read-only
ERR5 : Access Error [7:0]
bits : 21 - 21 (1 bit)
access : read-only
ERR6 : Access Error [7:0]
bits : 22 - 22 (1 bit)
access : read-only
ERR7 : Access Error [7:0]
bits : 23 - 23 (1 bit)
access : read-only
DICERR0 : Descriptor Integrity Check Error [7:0]
bits : 24 - 24 (1 bit)
access : read-only
DICERR1 : Descriptor Integrity Check Error [7:0]
bits : 25 - 25 (1 bit)
access : read-only
DICERR2 : Descriptor Integrity Check Error [7:0]
bits : 26 - 26 (1 bit)
access : read-only
DICERR3 : Descriptor Integrity Check Error [7:0]
bits : 27 - 27 (1 bit)
access : read-only
DICERR4 : Descriptor Integrity Check Error [7:0]
bits : 28 - 28 (1 bit)
access : read-only
DICERR5 : Descriptor Integrity Check Error [7:0]
bits : 29 - 29 (1 bit)
access : read-only
DICERR6 : Descriptor Integrity Check Error [7:0]
bits : 30 - 30 (1 bit)
access : read-only
DICERR7 : Descriptor Integrity Check Error [7:0]
bits : 31 - 31 (1 bit)
access : read-only
DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BTC0 : Buffer Transfer Completed [7:0]
bits : 0 - 0 (1 bit)
access : read-only
BTC1 : Buffer Transfer Completed [7:0]
bits : 1 - 1 (1 bit)
access : read-only
BTC2 : Buffer Transfer Completed [7:0]
bits : 2 - 2 (1 bit)
access : read-only
BTC3 : Buffer Transfer Completed [7:0]
bits : 3 - 3 (1 bit)
access : read-only
BTC4 : Buffer Transfer Completed [7:0]
bits : 4 - 4 (1 bit)
access : read-only
BTC5 : Buffer Transfer Completed [7:0]
bits : 5 - 5 (1 bit)
access : read-only
BTC6 : Buffer Transfer Completed [7:0]
bits : 6 - 6 (1 bit)
access : read-only
BTC7 : Buffer Transfer Completed [7:0]
bits : 7 - 7 (1 bit)
access : read-only
CBTC0 : Chained Buffer Transfer Completed [7:0]
bits : 8 - 8 (1 bit)
access : read-only
CBTC1 : Chained Buffer Transfer Completed [7:0]
bits : 9 - 9 (1 bit)
access : read-only
CBTC2 : Chained Buffer Transfer Completed [7:0]
bits : 10 - 10 (1 bit)
access : read-only
CBTC3 : Chained Buffer Transfer Completed [7:0]
bits : 11 - 11 (1 bit)
access : read-only
CBTC4 : Chained Buffer Transfer Completed [7:0]
bits : 12 - 12 (1 bit)
access : read-only
CBTC5 : Chained Buffer Transfer Completed [7:0]
bits : 13 - 13 (1 bit)
access : read-only
CBTC6 : Chained Buffer Transfer Completed [7:0]
bits : 14 - 14 (1 bit)
access : read-only
CBTC7 : Chained Buffer Transfer Completed [7:0]
bits : 15 - 15 (1 bit)
access : read-only
ERR0 : Access Error [7:0]
bits : 16 - 16 (1 bit)
access : read-only
ERR1 : Access Error [7:0]
bits : 17 - 17 (1 bit)
access : read-only
ERR2 : Access Error [7:0]
bits : 18 - 18 (1 bit)
access : read-only
ERR3 : Access Error [7:0]
bits : 19 - 19 (1 bit)
access : read-only
ERR4 : Access Error [7:0]
bits : 20 - 20 (1 bit)
access : read-only
ERR5 : Access Error [7:0]
bits : 21 - 21 (1 bit)
access : read-only
ERR6 : Access Error [7:0]
bits : 22 - 22 (1 bit)
access : read-only
ERR7 : Access Error [7:0]
bits : 23 - 23 (1 bit)
access : read-only
DICERR0 : Descriptor Integrity Check Error [7:0]
bits : 24 - 24 (1 bit)
access : read-only
DICERR1 : Descriptor Integrity Check Error [7:0]
bits : 25 - 25 (1 bit)
access : read-only
DICERR2 : Descriptor Integrity Check Error [7:0]
bits : 26 - 26 (1 bit)
access : read-only
DICERR3 : Descriptor Integrity Check Error [7:0]
bits : 27 - 27 (1 bit)
access : read-only
DICERR4 : Descriptor Integrity Check Error [7:0]
bits : 28 - 28 (1 bit)
access : read-only
DICERR5 : Descriptor Integrity Check Error [7:0]
bits : 29 - 29 (1 bit)
access : read-only
DICERR6 : Descriptor Integrity Check Error [7:0]
bits : 30 - 30 (1 bit)
access : read-only
DICERR7 : Descriptor Integrity Check Error [7:0]
bits : 31 - 31 (1 bit)
access : read-only
DMAC Channel Handler Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ENA0 : Enable [7:0]
bits : 0 - 0 (1 bit)
access : write-only
ENA1 : Enable [7:0]
bits : 1 - 1 (1 bit)
access : write-only
ENA2 : Enable [7:0]
bits : 2 - 2 (1 bit)
access : write-only
ENA3 : Enable [7:0]
bits : 3 - 3 (1 bit)
access : write-only
ENA4 : Enable [7:0]
bits : 4 - 4 (1 bit)
access : write-only
ENA5 : Enable [7:0]
bits : 5 - 5 (1 bit)
access : write-only
ENA6 : Enable [7:0]
bits : 6 - 6 (1 bit)
access : write-only
ENA7 : Enable [7:0]
bits : 7 - 7 (1 bit)
access : write-only
SUSP0 : Suspend [7:0]
bits : 8 - 8 (1 bit)
access : write-only
SUSP1 : Suspend [7:0]
bits : 9 - 9 (1 bit)
access : write-only
SUSP2 : Suspend [7:0]
bits : 10 - 10 (1 bit)
access : write-only
SUSP3 : Suspend [7:0]
bits : 11 - 11 (1 bit)
access : write-only
SUSP4 : Suspend [7:0]
bits : 12 - 12 (1 bit)
access : write-only
SUSP5 : Suspend [7:0]
bits : 13 - 13 (1 bit)
access : write-only
SUSP6 : Suspend [7:0]
bits : 14 - 14 (1 bit)
access : write-only
SUSP7 : Suspend [7:0]
bits : 15 - 15 (1 bit)
access : write-only
KEEP0 : Keep on [7:0]
bits : 24 - 24 (1 bit)
access : write-only
KEEP1 : Keep on [7:0]
bits : 25 - 25 (1 bit)
access : write-only
KEEP2 : Keep on [7:0]
bits : 26 - 26 (1 bit)
access : write-only
KEEP3 : Keep on [7:0]
bits : 27 - 27 (1 bit)
access : write-only
KEEP4 : Keep on [7:0]
bits : 28 - 28 (1 bit)
access : write-only
KEEP5 : Keep on [7:0]
bits : 29 - 29 (1 bit)
access : write-only
KEEP6 : Keep on [7:0]
bits : 30 - 30 (1 bit)
access : write-only
KEEP7 : Keep on [7:0]
bits : 31 - 31 (1 bit)
access : write-only
DMAC Channel Handler Disable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DIS0 : Disable [7:0]
bits : 0 - 0 (1 bit)
access : write-only
DIS1 : Disable [7:0]
bits : 1 - 1 (1 bit)
access : write-only
DIS2 : Disable [7:0]
bits : 2 - 2 (1 bit)
access : write-only
DIS3 : Disable [7:0]
bits : 3 - 3 (1 bit)
access : write-only
DIS4 : Disable [7:0]
bits : 4 - 4 (1 bit)
access : write-only
DIS5 : Disable [7:0]
bits : 5 - 5 (1 bit)
access : write-only
DIS6 : Disable [7:0]
bits : 6 - 6 (1 bit)
access : write-only
DIS7 : Disable [7:0]
bits : 7 - 7 (1 bit)
access : write-only
RES0 : Resume [7:0]
bits : 8 - 8 (1 bit)
access : write-only
RES1 : Resume [7:0]
bits : 9 - 9 (1 bit)
access : write-only
RES2 : Resume [7:0]
bits : 10 - 10 (1 bit)
access : write-only
RES3 : Resume [7:0]
bits : 11 - 11 (1 bit)
access : write-only
RES4 : Resume [7:0]
bits : 12 - 12 (1 bit)
access : write-only
RES5 : Resume [7:0]
bits : 13 - 13 (1 bit)
access : write-only
RES6 : Resume [7:0]
bits : 14 - 14 (1 bit)
access : write-only
RES7 : Resume [7:0]
bits : 15 - 15 (1 bit)
access : write-only
DMAC Channel Handler Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENA0 : Enable [7:0]
bits : 0 - 0 (1 bit)
access : read-only
ENA1 : Enable [7:0]
bits : 1 - 1 (1 bit)
access : read-only
ENA2 : Enable [7:0]
bits : 2 - 2 (1 bit)
access : read-only
ENA3 : Enable [7:0]
bits : 3 - 3 (1 bit)
access : read-only
ENA4 : Enable [7:0]
bits : 4 - 4 (1 bit)
access : read-only
ENA5 : Enable [7:0]
bits : 5 - 5 (1 bit)
access : read-only
ENA6 : Enable [7:0]
bits : 6 - 6 (1 bit)
access : read-only
ENA7 : Enable [7:0]
bits : 7 - 7 (1 bit)
access : read-only
SUSP0 : Suspend [7:0]
bits : 8 - 8 (1 bit)
access : read-only
SUSP1 : Suspend [7:0]
bits : 9 - 9 (1 bit)
access : read-only
SUSP2 : Suspend [7:0]
bits : 10 - 10 (1 bit)
access : read-only
SUSP3 : Suspend [7:0]
bits : 11 - 11 (1 bit)
access : read-only
SUSP4 : Suspend [7:0]
bits : 12 - 12 (1 bit)
access : read-only
SUSP5 : Suspend [7:0]
bits : 13 - 13 (1 bit)
access : read-only
SUSP6 : Suspend [7:0]
bits : 14 - 14 (1 bit)
access : read-only
SUSP7 : Suspend [7:0]
bits : 15 - 15 (1 bit)
access : read-only
EMPT0 : Empty [7:0]
bits : 16 - 16 (1 bit)
access : read-only
EMPT1 : Empty [7:0]
bits : 17 - 17 (1 bit)
access : read-only
EMPT2 : Empty [7:0]
bits : 18 - 18 (1 bit)
access : read-only
EMPT3 : Empty [7:0]
bits : 19 - 19 (1 bit)
access : read-only
EMPT4 : Empty [7:0]
bits : 20 - 20 (1 bit)
access : read-only
EMPT5 : Empty [7:0]
bits : 21 - 21 (1 bit)
access : read-only
EMPT6 : Empty [7:0]
bits : 22 - 22 (1 bit)
access : read-only
EMPT7 : Empty [7:0]
bits : 23 - 23 (1 bit)
access : read-only
STAL0 : Stalled [7:0]
bits : 24 - 24 (1 bit)
access : read-only
STAL1 : Stalled [7:0]
bits : 25 - 25 (1 bit)
access : read-only
STAL2 : Stalled [7:0]
bits : 26 - 26 (1 bit)
access : read-only
STAL3 : Stalled [7:0]
bits : 27 - 27 (1 bit)
access : read-only
STAL4 : Stalled [7:0]
bits : 28 - 28 (1 bit)
access : read-only
STAL5 : Stalled [7:0]
bits : 29 - 29 (1 bit)
access : read-only
STAL6 : Stalled [7:0]
bits : 30 - 30 (1 bit)
access : read-only
STAL7 : Stalled [7:0]
bits : 31 - 31 (1 bit)
access : read-only
DMAC Channel Source Address Register (ch_num = 0)
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
DMAC Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : General Enable of DMA
bits : 0 - 0 (1 bit)
access : read-write
DMAC Channel Destination Address Register (ch_num = 0)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel Descriptor Address Register (ch_num = 0)
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSCR_IF : Descriptor Interface Selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The buffer transfer descriptor is fetched via AHB-Lite Interface 0
0x1 : AHB_IF1
The buffer transfer descriptor is fetched via AHB-Lite Interface 1
0x2 : AHB_IF2
The buffer transfer descriptor is fetched via AHB-Lite Interface 2
End of enumeration elements list.
DSCR : Buffer Transfer Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
DMAC Channel Control A Register (ch_num = 0)
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTSIZE : Buffer Transfer Size
bits : 0 - 15 (16 bit)
access : read-write
SCSIZE : Source Chunk Transfer Size.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_4
4 data transferred
0x2 : CHK_8
8 data transferred
0x3 : CHK_16
16 data transferred
End of enumeration elements list.
DCSIZE : Destination Chunk Transfer Size
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_4
4 data transferred
0x2 : CHK_8
8 data transferred
0x3 : CHK_16
16 data transferred
End of enumeration elements list.
SRC_WIDTH : Transfer Width for the Source
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
the transfer size is set to 8-bit width
0x1 : HALF_WORD
the transfer size is set to 16-bit width
0x2 : WORD
the transfer size is set to 32-bit width
0x3 : DWORD
the transfer size is set to 64-bit width
End of enumeration elements list.
DST_WIDTH : Transfer Width for the Destination
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
the transfer size is set to 8-bit width
0x1 : HALF_WORD
the transfer size is set to 16-bit width
0x2 : WORD
the transfer size is set to 32-bit width
0x3 : DWORD
the transfer size is set to 64-bit width
End of enumeration elements list.
DONE : Current Descriptor Stop Command and Transfer Completed Memory Indicator
bits : 31 - 31 (1 bit)
access : read-write
DMAC Channel Control B Register (ch_num = 0)
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIF : Source Interface Selection Field
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The source transfer is done via AHB_Lite Interface 0
0x1 : AHB_IF1
The source transfer is done via AHB_Lite Interface 1
0x2 : AHB_IF2
The source transfer is done via AHB_Lite Interface 2
End of enumeration elements list.
DIF : Destination Interface Selection Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The destination transfer is done via AHB_Lite Interface 0
0x1 : AHB_IF1
The destination transfer is done via AHB_Lite Interface 1
0x2 : AHB_IF2
The destination transfer is done via AHB_Lite Interface 2
End of enumeration elements list.
SRC_PIP : Source Picture-in-Picture Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Picture-in-Picture mode is disabled. The source data area is contiguous.
1 : ENABLE
Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is automatically incremented by a user defined amount.
End of enumeration elements list.
DST_PIP : Destination Picture-in-Picture Mode
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Picture-in-Picture mode is disabled. The Destination data area is contiguous.
1 : ENABLE
Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address is automatically incremented by a user-defined amount.
End of enumeration elements list.
SRC_DSCR : Source Address Descriptor
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : FETCH_FROM_MEM
Source address is updated when the descriptor is fetched from the memory.
1 : FETCH_DISABLE
Buffer Descriptor Fetch operation is disabled for the source.
End of enumeration elements list.
DST_DSCR : Destination Address Descriptor
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : FETCH_FROM_MEM
Destination address is updated when the descriptor is fetched from the memory.
1 : FETCH_DISABLE
Buffer Descriptor Fetch operation is disabled for the destination.
End of enumeration elements list.
FC : Flow Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0x0 : MEM2MEM_DMA_FC
Memory-to-Memory Transfer DMAC is flow controller
0x1 : MEM2PER_DMA_FC
Memory-to-Peripheral Transfer DMAC is flow controller
0x2 : PER2MEM_DMA_FC
Peripheral-to-Memory Transfer DMAC is flow controller
0x3 : PER2PER_DMA_FC
Peripheral-to-Peripheral Transfer DMAC is flow controller
End of enumeration elements list.
SRC_INCR : Incrementing, Decrementing or Fixed Address for the Source
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : INCREMENTING
The source address is incremented
0x1 : DECREMENTING
The source address is decremented
0x2 : FIXED
The source address remains unchanged
End of enumeration elements list.
DST_INCR : Incrementing, Decrementing or Fixed Address for the Destination
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : INCREMENTING
The destination address is incremented
0x1 : DECREMENTING
The destination address is decremented
0x2 : FIXED
The destination address remains unchanged
End of enumeration elements list.
IEN : Interrupt Enable Not
bits : 30 - 30 (1 bit)
access : read-write
AUTO : Automatic Multiple Buffer Transfer
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic multiple buffer transfer is disabled.
1 : ENABLE
Automatic multiple buffer transfer is enabled. This bit enables replay mode or contiguous mode when several buffers are transferred.
End of enumeration elements list.
DMAC Channel Configuration Register (ch_num = 0)
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_PER : Source with Peripheral identifier
bits : 0 - 3 (4 bit)
access : read-write
DST_PER : Destination with Peripheral identifier
bits : 4 - 7 (4 bit)
access : read-write
SRC_REP : Source Reloaded from Previous
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CONTIGUOUS_ADDR
When automatic mode is activated, source address is contiguous between two buffers.
1 : RELOAD_ADDR
When automatic mode is activated, the source address and the control register are reloaded from previous transfer.
End of enumeration elements list.
SRC_H2SEL : Software or Hardware Selection for the Source
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SW
Software handshaking interface is used to trigger a transfer request.
1 : HW
Hardware handshaking interface is used to trigger a transfer request.
End of enumeration elements list.
SRC_PER_MSB : SRC_PER Most Significant Bits
bits : 10 - 11 (2 bit)
access : read-write
DST_REP : Destination Reloaded from Previous
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : CONTIGUOUS_ADDR
When automatic mode is activated, destination address is contiguous between two buffers.
1 : RELOAD_ADDR
When automatic mode is activated, the destination and the control register are reloaded from the pre-vious transfer.
End of enumeration elements list.
DST_H2SEL : Software or Hardware Selection for the Destination
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SW
Software handshaking interface is used to trigger a transfer request.
1 : HW
Hardware handshaking interface is used to trigger a transfer request.
End of enumeration elements list.
DST_PER_MSB : DST_PER Most Significant Bits
bits : 14 - 15 (2 bit)
access : read-write
SOD : Stop On Done
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
1 : ENABLE
STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
End of enumeration elements list.
LOCK_IF : Interface Lock
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Interface Lock capability is disabled
1 : ENABLE
Interface Lock capability is enabled
End of enumeration elements list.
LOCK_B : Bus Lock
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
AHB Bus Locking capability is disabled.
End of enumeration elements list.
LOCK_IF_L : Master Interface Arbiter Lock
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : CHUNK
The Master Interface Arbiter is locked by the channel x for a chunk transfer.
1 : BUFFER
The Master Interface Arbiter is locked by the channel x for a buffer transfer.
End of enumeration elements list.
AHB_PROT : AHB Protection
bits : 24 - 26 (3 bit)
access : read-write
FIFOCFG : FIFO Configuration
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : ALAP_CFG
The largest defined length AHB burst is performed on the destination AHB interface.
0x1 : HALF_CFG
When half FIFO size is available/filled, a source/destination request is serviced.
0x2 : ASAP_CFG
When there is enough space/data available to perform a single AHB access, then the request is serviced.
End of enumeration elements list.
DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 0)
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIP_HOLE : Source Picture-in-Picture Hole
bits : 0 - 15 (16 bit)
access : read-write
SPIP_BOUNDARY : Source Picture-in-Picture Boundary
bits : 16 - 25 (10 bit)
access : read-write
DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 0)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPIP_HOLE : Destination Picture-in-Picture Hole
bits : 0 - 15 (16 bit)
access : read-write
DPIP_BOUNDARY : Destination Picture-in-Picture Boundary
bits : 16 - 25 (10 bit)
access : read-write
DMAC Channel Source Address Register (ch_num = 1)
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel Destination Address Register (ch_num = 1)
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel Descriptor Address Register (ch_num = 1)
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSCR_IF : Descriptor Interface Selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The buffer transfer descriptor is fetched via AHB-Lite Interface 0
0x1 : AHB_IF1
The buffer transfer descriptor is fetched via AHB-Lite Interface 1
0x2 : AHB_IF2
The buffer transfer descriptor is fetched via AHB-Lite Interface 2
End of enumeration elements list.
DSCR : Buffer Transfer Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
DMAC Channel Control A Register (ch_num = 1)
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTSIZE : Buffer Transfer Size
bits : 0 - 15 (16 bit)
access : read-write
SCSIZE : Source Chunk Transfer Size.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_4
4 data transferred
0x2 : CHK_8
8 data transferred
0x3 : CHK_16
16 data transferred
End of enumeration elements list.
DCSIZE : Destination Chunk Transfer Size
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_4
4 data transferred
0x2 : CHK_8
8 data transferred
0x3 : CHK_16
16 data transferred
End of enumeration elements list.
SRC_WIDTH : Transfer Width for the Source
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
the transfer size is set to 8-bit width
0x1 : HALF_WORD
the transfer size is set to 16-bit width
0x2 : WORD
the transfer size is set to 32-bit width
0x3 : DWORD
the transfer size is set to 64-bit width
End of enumeration elements list.
DST_WIDTH : Transfer Width for the Destination
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
the transfer size is set to 8-bit width
0x1 : HALF_WORD
the transfer size is set to 16-bit width
0x2 : WORD
the transfer size is set to 32-bit width
0x3 : DWORD
the transfer size is set to 64-bit width
End of enumeration elements list.
DONE : Current Descriptor Stop Command and Transfer Completed Memory Indicator
bits : 31 - 31 (1 bit)
access : read-write
DMAC Channel Control B Register (ch_num = 1)
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIF : Source Interface Selection Field
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The source transfer is done via AHB_Lite Interface 0
0x1 : AHB_IF1
The source transfer is done via AHB_Lite Interface 1
0x2 : AHB_IF2
The source transfer is done via AHB_Lite Interface 2
End of enumeration elements list.
DIF : Destination Interface Selection Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The destination transfer is done via AHB_Lite Interface 0
0x1 : AHB_IF1
The destination transfer is done via AHB_Lite Interface 1
0x2 : AHB_IF2
The destination transfer is done via AHB_Lite Interface 2
End of enumeration elements list.
SRC_PIP : Source Picture-in-Picture Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Picture-in-Picture mode is disabled. The source data area is contiguous.
1 : ENABLE
Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is automatically incremented by a user defined amount.
End of enumeration elements list.
DST_PIP : Destination Picture-in-Picture Mode
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Picture-in-Picture mode is disabled. The Destination data area is contiguous.
1 : ENABLE
Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address is automatically incremented by a user-defined amount.
End of enumeration elements list.
SRC_DSCR : Source Address Descriptor
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : FETCH_FROM_MEM
Source address is updated when the descriptor is fetched from the memory.
1 : FETCH_DISABLE
Buffer Descriptor Fetch operation is disabled for the source.
End of enumeration elements list.
DST_DSCR : Destination Address Descriptor
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : FETCH_FROM_MEM
Destination address is updated when the descriptor is fetched from the memory.
1 : FETCH_DISABLE
Buffer Descriptor Fetch operation is disabled for the destination.
End of enumeration elements list.
FC : Flow Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0x0 : MEM2MEM_DMA_FC
Memory-to-Memory Transfer DMAC is flow controller
0x1 : MEM2PER_DMA_FC
Memory-to-Peripheral Transfer DMAC is flow controller
0x2 : PER2MEM_DMA_FC
Peripheral-to-Memory Transfer DMAC is flow controller
0x3 : PER2PER_DMA_FC
Peripheral-to-Peripheral Transfer DMAC is flow controller
End of enumeration elements list.
SRC_INCR : Incrementing, Decrementing or Fixed Address for the Source
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : INCREMENTING
The source address is incremented
0x1 : DECREMENTING
The source address is decremented
0x2 : FIXED
The source address remains unchanged
End of enumeration elements list.
DST_INCR : Incrementing, Decrementing or Fixed Address for the Destination
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : INCREMENTING
The destination address is incremented
0x1 : DECREMENTING
The destination address is decremented
0x2 : FIXED
The destination address remains unchanged
End of enumeration elements list.
IEN : Interrupt Enable Not
bits : 30 - 30 (1 bit)
access : read-write
AUTO : Automatic Multiple Buffer Transfer
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic multiple buffer transfer is disabled.
1 : ENABLE
Automatic multiple buffer transfer is enabled. This bit enables replay mode or contiguous mode when several buffers are transferred.
End of enumeration elements list.
DMAC Channel Configuration Register (ch_num = 1)
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_PER : Source with Peripheral identifier
bits : 0 - 3 (4 bit)
access : read-write
DST_PER : Destination with Peripheral identifier
bits : 4 - 7 (4 bit)
access : read-write
SRC_REP : Source Reloaded from Previous
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CONTIGUOUS_ADDR
When automatic mode is activated, source address is contiguous between two buffers.
1 : RELOAD_ADDR
When automatic mode is activated, the source address and the control register are reloaded from previous transfer.
End of enumeration elements list.
SRC_H2SEL : Software or Hardware Selection for the Source
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SW
Software handshaking interface is used to trigger a transfer request.
1 : HW
Hardware handshaking interface is used to trigger a transfer request.
End of enumeration elements list.
SRC_PER_MSB : SRC_PER Most Significant Bits
bits : 10 - 11 (2 bit)
access : read-write
DST_REP : Destination Reloaded from Previous
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : CONTIGUOUS_ADDR
When automatic mode is activated, destination address is contiguous between two buffers.
1 : RELOAD_ADDR
When automatic mode is activated, the destination and the control register are reloaded from the pre-vious transfer.
End of enumeration elements list.
DST_H2SEL : Software or Hardware Selection for the Destination
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SW
Software handshaking interface is used to trigger a transfer request.
1 : HW
Hardware handshaking interface is used to trigger a transfer request.
End of enumeration elements list.
DST_PER_MSB : DST_PER Most Significant Bits
bits : 14 - 15 (2 bit)
access : read-write
SOD : Stop On Done
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
1 : ENABLE
STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
End of enumeration elements list.
LOCK_IF : Interface Lock
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Interface Lock capability is disabled
1 : ENABLE
Interface Lock capability is enabled
End of enumeration elements list.
LOCK_B : Bus Lock
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
AHB Bus Locking capability is disabled.
End of enumeration elements list.
LOCK_IF_L : Master Interface Arbiter Lock
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : CHUNK
The Master Interface Arbiter is locked by the channel x for a chunk transfer.
1 : BUFFER
The Master Interface Arbiter is locked by the channel x for a buffer transfer.
End of enumeration elements list.
AHB_PROT : AHB Protection
bits : 24 - 26 (3 bit)
access : read-write
FIFOCFG : FIFO Configuration
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : ALAP_CFG
The largest defined length AHB burst is performed on the destination AHB interface.
0x1 : HALF_CFG
When half FIFO size is available/filled, a source/destination request is serviced.
0x2 : ASAP_CFG
When there is enough space/data available to perform a single AHB access, then the request is serviced.
End of enumeration elements list.
DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 1)
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIP_HOLE : Source Picture-in-Picture Hole
bits : 0 - 15 (16 bit)
access : read-write
SPIP_BOUNDARY : Source Picture-in-Picture Boundary
bits : 16 - 25 (10 bit)
access : read-write
DMAC Software Single Request Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSREQ0 : Source Request
bits : 0 - 0 (1 bit)
access : read-write
DSREQ0 : Destination Request
bits : 1 - 1 (1 bit)
access : read-write
SSREQ1 : Source Request
bits : 2 - 2 (1 bit)
access : read-write
DSREQ1 : Destination Request
bits : 3 - 3 (1 bit)
access : read-write
SSREQ2 : Source Request
bits : 4 - 4 (1 bit)
access : read-write
DSREQ2 : Destination Request
bits : 5 - 5 (1 bit)
access : read-write
SSREQ3 : Source Request
bits : 6 - 6 (1 bit)
access : read-write
DSREQ3 : Destination Request
bits : 7 - 7 (1 bit)
access : read-write
SSREQ4 : Source Request
bits : 8 - 8 (1 bit)
access : read-write
DSREQ4 : Destination Request
bits : 9 - 9 (1 bit)
access : read-write
SSREQ5 : Source Request
bits : 10 - 10 (1 bit)
access : read-write
DSREQ5 : Destination Request
bits : 11 - 11 (1 bit)
access : read-write
SSREQ6 : Source Request
bits : 12 - 12 (1 bit)
access : read-write
DSREQ6 : Destination Request
bits : 13 - 13 (1 bit)
access : read-write
SSREQ7 : Source Request
bits : 14 - 14 (1 bit)
access : read-write
DSREQ7 : Destination Request
bits : 15 - 15 (1 bit)
access : read-write
DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 1)
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPIP_HOLE : Destination Picture-in-Picture Hole
bits : 0 - 15 (16 bit)
access : read-write
DPIP_BOUNDARY : Destination Picture-in-Picture Boundary
bits : 16 - 25 (10 bit)
access : read-write
DMAC Channel Source Address Register (ch_num = 2)
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel Destination Address Register (ch_num = 2)
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel Descriptor Address Register (ch_num = 2)
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSCR_IF : Descriptor Interface Selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The buffer transfer descriptor is fetched via AHB-Lite Interface 0
0x1 : AHB_IF1
The buffer transfer descriptor is fetched via AHB-Lite Interface 1
0x2 : AHB_IF2
The buffer transfer descriptor is fetched via AHB-Lite Interface 2
End of enumeration elements list.
DSCR : Buffer Transfer Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
DMAC Channel Control A Register (ch_num = 2)
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTSIZE : Buffer Transfer Size
bits : 0 - 15 (16 bit)
access : read-write
SCSIZE : Source Chunk Transfer Size.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_4
4 data transferred
0x2 : CHK_8
8 data transferred
0x3 : CHK_16
16 data transferred
End of enumeration elements list.
DCSIZE : Destination Chunk Transfer Size
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_4
4 data transferred
0x2 : CHK_8
8 data transferred
0x3 : CHK_16
16 data transferred
End of enumeration elements list.
SRC_WIDTH : Transfer Width for the Source
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
the transfer size is set to 8-bit width
0x1 : HALF_WORD
the transfer size is set to 16-bit width
0x2 : WORD
the transfer size is set to 32-bit width
0x3 : DWORD
the transfer size is set to 64-bit width
End of enumeration elements list.
DST_WIDTH : Transfer Width for the Destination
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
the transfer size is set to 8-bit width
0x1 : HALF_WORD
the transfer size is set to 16-bit width
0x2 : WORD
the transfer size is set to 32-bit width
0x3 : DWORD
the transfer size is set to 64-bit width
End of enumeration elements list.
DONE : Current Descriptor Stop Command and Transfer Completed Memory Indicator
bits : 31 - 31 (1 bit)
access : read-write
DMAC Channel Control B Register (ch_num = 2)
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIF : Source Interface Selection Field
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The source transfer is done via AHB_Lite Interface 0
0x1 : AHB_IF1
The source transfer is done via AHB_Lite Interface 1
0x2 : AHB_IF2
The source transfer is done via AHB_Lite Interface 2
End of enumeration elements list.
DIF : Destination Interface Selection Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The destination transfer is done via AHB_Lite Interface 0
0x1 : AHB_IF1
The destination transfer is done via AHB_Lite Interface 1
0x2 : AHB_IF2
The destination transfer is done via AHB_Lite Interface 2
End of enumeration elements list.
SRC_PIP : Source Picture-in-Picture Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Picture-in-Picture mode is disabled. The source data area is contiguous.
1 : ENABLE
Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is automatically incremented by a user defined amount.
End of enumeration elements list.
DST_PIP : Destination Picture-in-Picture Mode
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Picture-in-Picture mode is disabled. The Destination data area is contiguous.
1 : ENABLE
Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address is automatically incremented by a user-defined amount.
End of enumeration elements list.
SRC_DSCR : Source Address Descriptor
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : FETCH_FROM_MEM
Source address is updated when the descriptor is fetched from the memory.
1 : FETCH_DISABLE
Buffer Descriptor Fetch operation is disabled for the source.
End of enumeration elements list.
DST_DSCR : Destination Address Descriptor
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : FETCH_FROM_MEM
Destination address is updated when the descriptor is fetched from the memory.
1 : FETCH_DISABLE
Buffer Descriptor Fetch operation is disabled for the destination.
End of enumeration elements list.
FC : Flow Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0x0 : MEM2MEM_DMA_FC
Memory-to-Memory Transfer DMAC is flow controller
0x1 : MEM2PER_DMA_FC
Memory-to-Peripheral Transfer DMAC is flow controller
0x2 : PER2MEM_DMA_FC
Peripheral-to-Memory Transfer DMAC is flow controller
0x3 : PER2PER_DMA_FC
Peripheral-to-Peripheral Transfer DMAC is flow controller
End of enumeration elements list.
SRC_INCR : Incrementing, Decrementing or Fixed Address for the Source
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : INCREMENTING
The source address is incremented
0x1 : DECREMENTING
The source address is decremented
0x2 : FIXED
The source address remains unchanged
End of enumeration elements list.
DST_INCR : Incrementing, Decrementing or Fixed Address for the Destination
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : INCREMENTING
The destination address is incremented
0x1 : DECREMENTING
The destination address is decremented
0x2 : FIXED
The destination address remains unchanged
End of enumeration elements list.
IEN : Interrupt Enable Not
bits : 30 - 30 (1 bit)
access : read-write
AUTO : Automatic Multiple Buffer Transfer
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic multiple buffer transfer is disabled.
1 : ENABLE
Automatic multiple buffer transfer is enabled. This bit enables replay mode or contiguous mode when several buffers are transferred.
End of enumeration elements list.
DMAC Channel Configuration Register (ch_num = 2)
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_PER : Source with Peripheral identifier
bits : 0 - 3 (4 bit)
access : read-write
DST_PER : Destination with Peripheral identifier
bits : 4 - 7 (4 bit)
access : read-write
SRC_REP : Source Reloaded from Previous
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CONTIGUOUS_ADDR
When automatic mode is activated, source address is contiguous between two buffers.
1 : RELOAD_ADDR
When automatic mode is activated, the source address and the control register are reloaded from previous transfer.
End of enumeration elements list.
SRC_H2SEL : Software or Hardware Selection for the Source
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SW
Software handshaking interface is used to trigger a transfer request.
1 : HW
Hardware handshaking interface is used to trigger a transfer request.
End of enumeration elements list.
SRC_PER_MSB : SRC_PER Most Significant Bits
bits : 10 - 11 (2 bit)
access : read-write
DST_REP : Destination Reloaded from Previous
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : CONTIGUOUS_ADDR
When automatic mode is activated, destination address is contiguous between two buffers.
1 : RELOAD_ADDR
When automatic mode is activated, the destination and the control register are reloaded from the pre-vious transfer.
End of enumeration elements list.
DST_H2SEL : Software or Hardware Selection for the Destination
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SW
Software handshaking interface is used to trigger a transfer request.
1 : HW
Hardware handshaking interface is used to trigger a transfer request.
End of enumeration elements list.
DST_PER_MSB : DST_PER Most Significant Bits
bits : 14 - 15 (2 bit)
access : read-write
SOD : Stop On Done
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
1 : ENABLE
STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
End of enumeration elements list.
LOCK_IF : Interface Lock
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Interface Lock capability is disabled
1 : ENABLE
Interface Lock capability is enabled
End of enumeration elements list.
LOCK_B : Bus Lock
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
AHB Bus Locking capability is disabled.
End of enumeration elements list.
LOCK_IF_L : Master Interface Arbiter Lock
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : CHUNK
The Master Interface Arbiter is locked by the channel x for a chunk transfer.
1 : BUFFER
The Master Interface Arbiter is locked by the channel x for a buffer transfer.
End of enumeration elements list.
AHB_PROT : AHB Protection
bits : 24 - 26 (3 bit)
access : read-write
FIFOCFG : FIFO Configuration
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : ALAP_CFG
The largest defined length AHB burst is performed on the destination AHB interface.
0x1 : HALF_CFG
When half FIFO size is available/filled, a source/destination request is serviced.
0x2 : ASAP_CFG
When there is enough space/data available to perform a single AHB access, then the request is serviced.
End of enumeration elements list.
DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 2)
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIP_HOLE : Source Picture-in-Picture Hole
bits : 0 - 15 (16 bit)
access : read-write
SPIP_BOUNDARY : Source Picture-in-Picture Boundary
bits : 16 - 25 (10 bit)
access : read-write
DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 2)
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPIP_HOLE : Destination Picture-in-Picture Hole
bits : 0 - 15 (16 bit)
access : read-write
DPIP_BOUNDARY : Destination Picture-in-Picture Boundary
bits : 16 - 25 (10 bit)
access : read-write
DMAC Channel Source Address Register (ch_num = 3)
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel Destination Address Register (ch_num = 3)
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel Descriptor Address Register (ch_num = 3)
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSCR_IF : Descriptor Interface Selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The buffer transfer descriptor is fetched via AHB-Lite Interface 0
0x1 : AHB_IF1
The buffer transfer descriptor is fetched via AHB-Lite Interface 1
0x2 : AHB_IF2
The buffer transfer descriptor is fetched via AHB-Lite Interface 2
End of enumeration elements list.
DSCR : Buffer Transfer Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
DMAC Software Chunk Transfer Request Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCREQ0 : Source Chunk Request
bits : 0 - 0 (1 bit)
access : read-write
DCREQ0 : Destination Chunk Request
bits : 1 - 1 (1 bit)
access : read-write
SCREQ1 : Source Chunk Request
bits : 2 - 2 (1 bit)
access : read-write
DCREQ1 : Destination Chunk Request
bits : 3 - 3 (1 bit)
access : read-write
SCREQ2 : Source Chunk Request
bits : 4 - 4 (1 bit)
access : read-write
DCREQ2 : Destination Chunk Request
bits : 5 - 5 (1 bit)
access : read-write
SCREQ3 : Source Chunk Request
bits : 6 - 6 (1 bit)
access : read-write
DCREQ3 : Destination Chunk Request
bits : 7 - 7 (1 bit)
access : read-write
SCREQ4 : Source Chunk Request
bits : 8 - 8 (1 bit)
access : read-write
DCREQ4 : Destination Chunk Request
bits : 9 - 9 (1 bit)
access : read-write
SCREQ5 : Source Chunk Request
bits : 10 - 10 (1 bit)
access : read-write
DCREQ5 : Destination Chunk Request
bits : 11 - 11 (1 bit)
access : read-write
SCREQ6 : Source Chunk Request
bits : 12 - 12 (1 bit)
access : read-write
DCREQ6 : Destination Chunk Request
bits : 13 - 13 (1 bit)
access : read-write
SCREQ7 : Source Chunk Request
bits : 14 - 14 (1 bit)
access : read-write
DCREQ7 : Destination Chunk Request
bits : 15 - 15 (1 bit)
access : read-write
DMAC Channel Control A Register (ch_num = 3)
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTSIZE : Buffer Transfer Size
bits : 0 - 15 (16 bit)
access : read-write
SCSIZE : Source Chunk Transfer Size.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_4
4 data transferred
0x2 : CHK_8
8 data transferred
0x3 : CHK_16
16 data transferred
End of enumeration elements list.
DCSIZE : Destination Chunk Transfer Size
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_4
4 data transferred
0x2 : CHK_8
8 data transferred
0x3 : CHK_16
16 data transferred
End of enumeration elements list.
SRC_WIDTH : Transfer Width for the Source
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
the transfer size is set to 8-bit width
0x1 : HALF_WORD
the transfer size is set to 16-bit width
0x2 : WORD
the transfer size is set to 32-bit width
0x3 : DWORD
the transfer size is set to 64-bit width
End of enumeration elements list.
DST_WIDTH : Transfer Width for the Destination
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
the transfer size is set to 8-bit width
0x1 : HALF_WORD
the transfer size is set to 16-bit width
0x2 : WORD
the transfer size is set to 32-bit width
0x3 : DWORD
the transfer size is set to 64-bit width
End of enumeration elements list.
DONE : Current Descriptor Stop Command and Transfer Completed Memory Indicator
bits : 31 - 31 (1 bit)
access : read-write
DMAC Channel Control B Register (ch_num = 3)
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIF : Source Interface Selection Field
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The source transfer is done via AHB_Lite Interface 0
0x1 : AHB_IF1
The source transfer is done via AHB_Lite Interface 1
0x2 : AHB_IF2
The source transfer is done via AHB_Lite Interface 2
End of enumeration elements list.
DIF : Destination Interface Selection Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The destination transfer is done via AHB_Lite Interface 0
0x1 : AHB_IF1
The destination transfer is done via AHB_Lite Interface 1
0x2 : AHB_IF2
The destination transfer is done via AHB_Lite Interface 2
End of enumeration elements list.
SRC_PIP : Source Picture-in-Picture Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Picture-in-Picture mode is disabled. The source data area is contiguous.
1 : ENABLE
Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is automatically incremented by a user defined amount.
End of enumeration elements list.
DST_PIP : Destination Picture-in-Picture Mode
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Picture-in-Picture mode is disabled. The Destination data area is contiguous.
1 : ENABLE
Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address is automatically incremented by a user-defined amount.
End of enumeration elements list.
SRC_DSCR : Source Address Descriptor
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : FETCH_FROM_MEM
Source address is updated when the descriptor is fetched from the memory.
1 : FETCH_DISABLE
Buffer Descriptor Fetch operation is disabled for the source.
End of enumeration elements list.
DST_DSCR : Destination Address Descriptor
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : FETCH_FROM_MEM
Destination address is updated when the descriptor is fetched from the memory.
1 : FETCH_DISABLE
Buffer Descriptor Fetch operation is disabled for the destination.
End of enumeration elements list.
FC : Flow Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0x0 : MEM2MEM_DMA_FC
Memory-to-Memory Transfer DMAC is flow controller
0x1 : MEM2PER_DMA_FC
Memory-to-Peripheral Transfer DMAC is flow controller
0x2 : PER2MEM_DMA_FC
Peripheral-to-Memory Transfer DMAC is flow controller
0x3 : PER2PER_DMA_FC
Peripheral-to-Peripheral Transfer DMAC is flow controller
End of enumeration elements list.
SRC_INCR : Incrementing, Decrementing or Fixed Address for the Source
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : INCREMENTING
The source address is incremented
0x1 : DECREMENTING
The source address is decremented
0x2 : FIXED
The source address remains unchanged
End of enumeration elements list.
DST_INCR : Incrementing, Decrementing or Fixed Address for the Destination
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : INCREMENTING
The destination address is incremented
0x1 : DECREMENTING
The destination address is decremented
0x2 : FIXED
The destination address remains unchanged
End of enumeration elements list.
IEN : Interrupt Enable Not
bits : 30 - 30 (1 bit)
access : read-write
AUTO : Automatic Multiple Buffer Transfer
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic multiple buffer transfer is disabled.
1 : ENABLE
Automatic multiple buffer transfer is enabled. This bit enables replay mode or contiguous mode when several buffers are transferred.
End of enumeration elements list.
DMAC Channel Configuration Register (ch_num = 3)
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_PER : Source with Peripheral identifier
bits : 0 - 3 (4 bit)
access : read-write
DST_PER : Destination with Peripheral identifier
bits : 4 - 7 (4 bit)
access : read-write
SRC_REP : Source Reloaded from Previous
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CONTIGUOUS_ADDR
When automatic mode is activated, source address is contiguous between two buffers.
1 : RELOAD_ADDR
When automatic mode is activated, the source address and the control register are reloaded from previous transfer.
End of enumeration elements list.
SRC_H2SEL : Software or Hardware Selection for the Source
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SW
Software handshaking interface is used to trigger a transfer request.
1 : HW
Hardware handshaking interface is used to trigger a transfer request.
End of enumeration elements list.
SRC_PER_MSB : SRC_PER Most Significant Bits
bits : 10 - 11 (2 bit)
access : read-write
DST_REP : Destination Reloaded from Previous
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : CONTIGUOUS_ADDR
When automatic mode is activated, destination address is contiguous between two buffers.
1 : RELOAD_ADDR
When automatic mode is activated, the destination and the control register are reloaded from the pre-vious transfer.
End of enumeration elements list.
DST_H2SEL : Software or Hardware Selection for the Destination
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SW
Software handshaking interface is used to trigger a transfer request.
1 : HW
Hardware handshaking interface is used to trigger a transfer request.
End of enumeration elements list.
DST_PER_MSB : DST_PER Most Significant Bits
bits : 14 - 15 (2 bit)
access : read-write
SOD : Stop On Done
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
1 : ENABLE
STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
End of enumeration elements list.
LOCK_IF : Interface Lock
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Interface Lock capability is disabled
1 : ENABLE
Interface Lock capability is enabled
End of enumeration elements list.
LOCK_B : Bus Lock
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
AHB Bus Locking capability is disabled.
End of enumeration elements list.
LOCK_IF_L : Master Interface Arbiter Lock
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : CHUNK
The Master Interface Arbiter is locked by the channel x for a chunk transfer.
1 : BUFFER
The Master Interface Arbiter is locked by the channel x for a buffer transfer.
End of enumeration elements list.
AHB_PROT : AHB Protection
bits : 24 - 26 (3 bit)
access : read-write
FIFOCFG : FIFO Configuration
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : ALAP_CFG
The largest defined length AHB burst is performed on the destination AHB interface.
0x1 : HALF_CFG
When half FIFO size is available/filled, a source/destination request is serviced.
0x2 : ASAP_CFG
When there is enough space/data available to perform a single AHB access, then the request is serviced.
End of enumeration elements list.
DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 3)
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIP_HOLE : Source Picture-in-Picture Hole
bits : 0 - 15 (16 bit)
access : read-write
SPIP_BOUNDARY : Source Picture-in-Picture Boundary
bits : 16 - 25 (10 bit)
access : read-write
DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 3)
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPIP_HOLE : Destination Picture-in-Picture Hole
bits : 0 - 15 (16 bit)
access : read-write
DPIP_BOUNDARY : Destination Picture-in-Picture Boundary
bits : 16 - 25 (10 bit)
access : read-write
DMAC Channel Source Address Register (ch_num = 4)
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel Destination Address Register (ch_num = 4)
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
DMAC Channel Descriptor Address Register (ch_num = 4)
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSCR_IF : Descriptor Interface Selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The buffer transfer descriptor is fetched via AHB-Lite Interface 0
0x1 : AHB_IF1
The buffer transfer descriptor is fetched via AHB-Lite Interface 1
0x2 : AHB_IF2
The buffer transfer descriptor is fetched via AHB-Lite Interface 2
End of enumeration elements list.
DSCR : Buffer Transfer Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
DMAC Channel Control A Register (ch_num = 4)
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTSIZE : Buffer Transfer Size
bits : 0 - 15 (16 bit)
access : read-write
SCSIZE : Source Chunk Transfer Size.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_4
4 data transferred
0x2 : CHK_8
8 data transferred
0x3 : CHK_16
16 data transferred
End of enumeration elements list.
DCSIZE : Destination Chunk Transfer Size
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_4
4 data transferred
0x2 : CHK_8
8 data transferred
0x3 : CHK_16
16 data transferred
End of enumeration elements list.
SRC_WIDTH : Transfer Width for the Source
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
the transfer size is set to 8-bit width
0x1 : HALF_WORD
the transfer size is set to 16-bit width
0x2 : WORD
the transfer size is set to 32-bit width
0x3 : DWORD
the transfer size is set to 64-bit width
End of enumeration elements list.
DST_WIDTH : Transfer Width for the Destination
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
the transfer size is set to 8-bit width
0x1 : HALF_WORD
the transfer size is set to 16-bit width
0x2 : WORD
the transfer size is set to 32-bit width
0x3 : DWORD
the transfer size is set to 64-bit width
End of enumeration elements list.
DONE : Current Descriptor Stop Command and Transfer Completed Memory Indicator
bits : 31 - 31 (1 bit)
access : read-write
DMAC Channel Control B Register (ch_num = 4)
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIF : Source Interface Selection Field
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The source transfer is done via AHB_Lite Interface 0
0x1 : AHB_IF1
The source transfer is done via AHB_Lite Interface 1
0x2 : AHB_IF2
The source transfer is done via AHB_Lite Interface 2
End of enumeration elements list.
DIF : Destination Interface Selection Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : AHB_IF0
The destination transfer is done via AHB_Lite Interface 0
0x1 : AHB_IF1
The destination transfer is done via AHB_Lite Interface 1
0x2 : AHB_IF2
The destination transfer is done via AHB_Lite Interface 2
End of enumeration elements list.
SRC_PIP : Source Picture-in-Picture Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Picture-in-Picture mode is disabled. The source data area is contiguous.
1 : ENABLE
Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is automatically incremented by a user defined amount.
End of enumeration elements list.
DST_PIP : Destination Picture-in-Picture Mode
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Picture-in-Picture mode is disabled. The Destination data area is contiguous.
1 : ENABLE
Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address is automatically incremented by a user-defined amount.
End of enumeration elements list.
SRC_DSCR : Source Address Descriptor
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : FETCH_FROM_MEM
Source address is updated when the descriptor is fetched from the memory.
1 : FETCH_DISABLE
Buffer Descriptor Fetch operation is disabled for the source.
End of enumeration elements list.
DST_DSCR : Destination Address Descriptor
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : FETCH_FROM_MEM
Destination address is updated when the descriptor is fetched from the memory.
1 : FETCH_DISABLE
Buffer Descriptor Fetch operation is disabled for the destination.
End of enumeration elements list.
FC : Flow Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0x0 : MEM2MEM_DMA_FC
Memory-to-Memory Transfer DMAC is flow controller
0x1 : MEM2PER_DMA_FC
Memory-to-Peripheral Transfer DMAC is flow controller
0x2 : PER2MEM_DMA_FC
Peripheral-to-Memory Transfer DMAC is flow controller
0x3 : PER2PER_DMA_FC
Peripheral-to-Peripheral Transfer DMAC is flow controller
End of enumeration elements list.
SRC_INCR : Incrementing, Decrementing or Fixed Address for the Source
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : INCREMENTING
The source address is incremented
0x1 : DECREMENTING
The source address is decremented
0x2 : FIXED
The source address remains unchanged
End of enumeration elements list.
DST_INCR : Incrementing, Decrementing or Fixed Address for the Destination
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : INCREMENTING
The destination address is incremented
0x1 : DECREMENTING
The destination address is decremented
0x2 : FIXED
The destination address remains unchanged
End of enumeration elements list.
IEN : Interrupt Enable Not
bits : 30 - 30 (1 bit)
access : read-write
AUTO : Automatic Multiple Buffer Transfer
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic multiple buffer transfer is disabled.
1 : ENABLE
Automatic multiple buffer transfer is enabled. This bit enables replay mode or contiguous mode when several buffers are transferred.
End of enumeration elements list.
DMAC Channel Configuration Register (ch_num = 4)
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_PER : Source with Peripheral identifier
bits : 0 - 3 (4 bit)
access : read-write
DST_PER : Destination with Peripheral identifier
bits : 4 - 7 (4 bit)
access : read-write
SRC_REP : Source Reloaded from Previous
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CONTIGUOUS_ADDR
When automatic mode is activated, source address is contiguous between two buffers.
1 : RELOAD_ADDR
When automatic mode is activated, the source address and the control register are reloaded from previous transfer.
End of enumeration elements list.
SRC_H2SEL : Software or Hardware Selection for the Source
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SW
Software handshaking interface is used to trigger a transfer request.
1 : HW
Hardware handshaking interface is used to trigger a transfer request.
End of enumeration elements list.
SRC_PER_MSB : SRC_PER Most Significant Bits
bits : 10 - 11 (2 bit)
access : read-write
DST_REP : Destination Reloaded from Previous
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : CONTIGUOUS_ADDR
When automatic mode is activated, destination address is contiguous between two buffers.
1 : RELOAD_ADDR
When automatic mode is activated, the destination and the control register are reloaded from the pre-vious transfer.
End of enumeration elements list.
DST_H2SEL : Software or Hardware Selection for the Destination
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SW
Software handshaking interface is used to trigger a transfer request.
1 : HW
Hardware handshaking interface is used to trigger a transfer request.
End of enumeration elements list.
DST_PER_MSB : DST_PER Most Significant Bits
bits : 14 - 15 (2 bit)
access : read-write
SOD : Stop On Done
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
1 : ENABLE
STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
End of enumeration elements list.
LOCK_IF : Interface Lock
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Interface Lock capability is disabled
1 : ENABLE
Interface Lock capability is enabled
End of enumeration elements list.
LOCK_B : Bus Lock
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
AHB Bus Locking capability is disabled.
End of enumeration elements list.
LOCK_IF_L : Master Interface Arbiter Lock
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : CHUNK
The Master Interface Arbiter is locked by the channel x for a chunk transfer.
1 : BUFFER
The Master Interface Arbiter is locked by the channel x for a buffer transfer.
End of enumeration elements list.
AHB_PROT : AHB Protection
bits : 24 - 26 (3 bit)
access : read-write
FIFOCFG : FIFO Configuration
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : ALAP_CFG
The largest defined length AHB burst is performed on the destination AHB interface.
0x1 : HALF_CFG
When half FIFO size is available/filled, a source/destination request is serviced.
0x2 : ASAP_CFG
When there is enough space/data available to perform a single AHB access, then the request is serviced.
End of enumeration elements list.
DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 4)
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIP_HOLE : Source Picture-in-Picture Hole
bits : 0 - 15 (16 bit)
access : read-write
SPIP_BOUNDARY : Source Picture-in-Picture Boundary
bits : 16 - 25 (10 bit)
access : read-write
DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 4)
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPIP_HOLE : Destination Picture-in-Picture Hole
bits : 0 - 15 (16 bit)
access : read-write
DPIP_BOUNDARY : Destination Picture-in-Picture Boundary
bits : 16 - 25 (10 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.