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AIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SSR

IVR

FVR

ISR

IPR0

IPR1

IPR2

IPR3

IMR

CISR

EOICR

SPU

SMR

IECR

IDCR

ICCR

ISCR

FFER

FFDR

FFSR

DCR

SVR

WPMR

WPSR


SSR

Source Select Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR SSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSEL

INTSEL : Interrupt line Selection
bits : 0 - 6 (7 bit)
access : read-write


IVR

Interrupt Vector Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IVR IVR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQV

IRQV : Interrupt Vector Register
bits : 0 - 31 (32 bit)
access : read-only


FVR

FIQ Interrupt Vector Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FVR FVR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIQV

FIQV : FIQ Vector Register
bits : 0 - 31 (32 bit)
access : read-only


ISR

Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQID

IRQID : Current Interrupt Identifier
bits : 0 - 6 (7 bit)
access : read-only


IPR0

Interrupt Pending Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPR0 IPR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIQ SYS PID2 PID3 PID4 PID5 PID6 PID7 PID8 PID9 PID10 PID11 PID12 PID13 PID14 PID15 PID16 PID17 PID18 PID19 PID20 PID21 PID22 PID23 PID24 PID25 PID26 PID27 PID28 PID29 PID30 PID31

FIQ : Interrupt Pending
bits : 0 - 0 (1 bit)
access : read-only

SYS : Interrupt Pending
bits : 1 - 1 (1 bit)
access : read-only

PID2 : Interrupt Pending
bits : 2 - 2 (1 bit)
access : read-only

PID3 : Interrupt Pending
bits : 3 - 3 (1 bit)
access : read-only

PID4 : Interrupt Pending
bits : 4 - 4 (1 bit)
access : read-only

PID5 : Interrupt Pending
bits : 5 - 5 (1 bit)
access : read-only

PID6 : Interrupt Pending
bits : 6 - 6 (1 bit)
access : read-only

PID7 : Interrupt Pending
bits : 7 - 7 (1 bit)
access : read-only

PID8 : Interrupt Pending
bits : 8 - 8 (1 bit)
access : read-only

PID9 : Interrupt Pending
bits : 9 - 9 (1 bit)
access : read-only

PID10 : Interrupt Pending
bits : 10 - 10 (1 bit)
access : read-only

PID11 : Interrupt Pending
bits : 11 - 11 (1 bit)
access : read-only

PID12 : Interrupt Pending
bits : 12 - 12 (1 bit)
access : read-only

PID13 : Interrupt Pending
bits : 13 - 13 (1 bit)
access : read-only

PID14 : Interrupt Pending
bits : 14 - 14 (1 bit)
access : read-only

PID15 : Interrupt Pending
bits : 15 - 15 (1 bit)
access : read-only

PID16 : Interrupt Pending
bits : 16 - 16 (1 bit)
access : read-only

PID17 : Interrupt Pending
bits : 17 - 17 (1 bit)
access : read-only

PID18 : Interrupt Pending
bits : 18 - 18 (1 bit)
access : read-only

PID19 : Interrupt Pending
bits : 19 - 19 (1 bit)
access : read-only

PID20 : Interrupt Pending
bits : 20 - 20 (1 bit)
access : read-only

PID21 : Interrupt Pending
bits : 21 - 21 (1 bit)
access : read-only

PID22 : Interrupt Pending
bits : 22 - 22 (1 bit)
access : read-only

PID23 : Interrupt Pending
bits : 23 - 23 (1 bit)
access : read-only

PID24 : Interrupt Pending
bits : 24 - 24 (1 bit)
access : read-only

PID25 : Interrupt Pending
bits : 25 - 25 (1 bit)
access : read-only

PID26 : Interrupt Pending
bits : 26 - 26 (1 bit)
access : read-only

PID27 : Interrupt Pending
bits : 27 - 27 (1 bit)
access : read-only

PID28 : Interrupt Pending
bits : 28 - 28 (1 bit)
access : read-only

PID29 : Interrupt Pending
bits : 29 - 29 (1 bit)
access : read-only

PID30 : Interrupt Pending
bits : 30 - 30 (1 bit)
access : read-only

PID31 : Interrupt Pending
bits : 31 - 31 (1 bit)
access : read-only


IPR1

Interrupt Pending Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPR1 IPR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID32 PID33 PID34 PID35 PID36 PID37 PID38 PID39 PID40 PID41 PID42 PID43 PID44 PID45 PID46 PID47 PID48 PID49 PID50 PID51 PID52 PID53 PID54 PID55 PID56 PID57 PID58 PID59 PID60 PID61 PID62 PID63

PID32 : Interrupt Pending
bits : 0 - 0 (1 bit)
access : read-only

PID33 : Interrupt Pending
bits : 1 - 1 (1 bit)
access : read-only

PID34 : Interrupt Pending
bits : 2 - 2 (1 bit)
access : read-only

PID35 : Interrupt Pending
bits : 3 - 3 (1 bit)
access : read-only

PID36 : Interrupt Pending
bits : 4 - 4 (1 bit)
access : read-only

PID37 : Interrupt Pending
bits : 5 - 5 (1 bit)
access : read-only

PID38 : Interrupt Pending
bits : 6 - 6 (1 bit)
access : read-only

PID39 : Interrupt Pending
bits : 7 - 7 (1 bit)
access : read-only

PID40 : Interrupt Pending
bits : 8 - 8 (1 bit)
access : read-only

PID41 : Interrupt Pending
bits : 9 - 9 (1 bit)
access : read-only

PID42 : Interrupt Pending
bits : 10 - 10 (1 bit)
access : read-only

PID43 : Interrupt Pending
bits : 11 - 11 (1 bit)
access : read-only

PID44 : Interrupt Pending
bits : 12 - 12 (1 bit)
access : read-only

PID45 : Interrupt Pending
bits : 13 - 13 (1 bit)
access : read-only

PID46 : Interrupt Pending
bits : 14 - 14 (1 bit)
access : read-only

PID47 : Interrupt Pending
bits : 15 - 15 (1 bit)
access : read-only

PID48 : Interrupt Pending
bits : 16 - 16 (1 bit)
access : read-only

PID49 : Interrupt Pending
bits : 17 - 17 (1 bit)
access : read-only

PID50 : Interrupt Pending
bits : 18 - 18 (1 bit)
access : read-only

PID51 : Interrupt Pending
bits : 19 - 19 (1 bit)
access : read-only

PID52 : Interrupt Pending
bits : 20 - 20 (1 bit)
access : read-only

PID53 : Interrupt Pending
bits : 21 - 21 (1 bit)
access : read-only

PID54 : Interrupt Pending
bits : 22 - 22 (1 bit)
access : read-only

PID55 : Interrupt Pending
bits : 23 - 23 (1 bit)
access : read-only

PID56 : Interrupt Pending
bits : 24 - 24 (1 bit)
access : read-only

PID57 : Interrupt Pending
bits : 25 - 25 (1 bit)
access : read-only

PID58 : Interrupt Pending
bits : 26 - 26 (1 bit)
access : read-only

PID59 : Interrupt Pending
bits : 27 - 27 (1 bit)
access : read-only

PID60 : Interrupt Pending
bits : 28 - 28 (1 bit)
access : read-only

PID61 : Interrupt Pending
bits : 29 - 29 (1 bit)
access : read-only

PID62 : Interrupt Pending
bits : 30 - 30 (1 bit)
access : read-only

PID63 : Interrupt Pending
bits : 31 - 31 (1 bit)
access : read-only


IPR2

Interrupt Pending Register 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPR2 IPR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID64 PID65 PID66 PID67 PID68 PID69 PID70 PID71 PID72 PID73 PID74 PID75 PID76 PID77 PID78 PID79 PID80 PID81 PID82 PID83 PID84 PID85 PID86 PID87 PID88 PID89 PID90 PID91 PID92 PID93 PID94 PID95

PID64 : Interrupt Pending
bits : 0 - 0 (1 bit)
access : read-only

PID65 : Interrupt Pending
bits : 1 - 1 (1 bit)
access : read-only

PID66 : Interrupt Pending
bits : 2 - 2 (1 bit)
access : read-only

PID67 : Interrupt Pending
bits : 3 - 3 (1 bit)
access : read-only

PID68 : Interrupt Pending
bits : 4 - 4 (1 bit)
access : read-only

PID69 : Interrupt Pending
bits : 5 - 5 (1 bit)
access : read-only

PID70 : Interrupt Pending
bits : 6 - 6 (1 bit)
access : read-only

PID71 : Interrupt Pending
bits : 7 - 7 (1 bit)
access : read-only

PID72 : Interrupt Pending
bits : 8 - 8 (1 bit)
access : read-only

PID73 : Interrupt Pending
bits : 9 - 9 (1 bit)
access : read-only

PID74 : Interrupt Pending
bits : 10 - 10 (1 bit)
access : read-only

PID75 : Interrupt Pending
bits : 11 - 11 (1 bit)
access : read-only

PID76 : Interrupt Pending
bits : 12 - 12 (1 bit)
access : read-only

PID77 : Interrupt Pending
bits : 13 - 13 (1 bit)
access : read-only

PID78 : Interrupt Pending
bits : 14 - 14 (1 bit)
access : read-only

PID79 : Interrupt Pending
bits : 15 - 15 (1 bit)
access : read-only

PID80 : Interrupt Pending
bits : 16 - 16 (1 bit)
access : read-only

PID81 : Interrupt Pending
bits : 17 - 17 (1 bit)
access : read-only

PID82 : Interrupt Pending
bits : 18 - 18 (1 bit)
access : read-only

PID83 : Interrupt Pending
bits : 19 - 19 (1 bit)
access : read-only

PID84 : Interrupt Pending
bits : 20 - 20 (1 bit)
access : read-only

PID85 : Interrupt Pending
bits : 21 - 21 (1 bit)
access : read-only

PID86 : Interrupt Pending
bits : 22 - 22 (1 bit)
access : read-only

PID87 : Interrupt Pending
bits : 23 - 23 (1 bit)
access : read-only

PID88 : Interrupt Pending
bits : 24 - 24 (1 bit)
access : read-only

PID89 : Interrupt Pending
bits : 25 - 25 (1 bit)
access : read-only

PID90 : Interrupt Pending
bits : 26 - 26 (1 bit)
access : read-only

PID91 : Interrupt Pending
bits : 27 - 27 (1 bit)
access : read-only

PID92 : Interrupt Pending
bits : 28 - 28 (1 bit)
access : read-only

PID93 : Interrupt Pending
bits : 29 - 29 (1 bit)
access : read-only

PID94 : Interrupt Pending
bits : 30 - 30 (1 bit)
access : read-only

PID95 : Interrupt Pending
bits : 31 - 31 (1 bit)
access : read-only


IPR3

Interrupt Pending Register 3
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPR3 IPR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID96 PID97 PID98 PID99 PID100 PID101 PID102 PID103 PID104 PID105 PID106 PID107 PID108 PID109 PID110 PID111 PID112 PID113 PID114 PID115 PID116 PID117 PID118 PID119 PID120 PID121 PID122 PID123 PID124 PID125 PID126 PID127

PID96 : Interrupt Pending
bits : 0 - 0 (1 bit)
access : read-only

PID97 : Interrupt Pending
bits : 1 - 1 (1 bit)
access : read-only

PID98 : Interrupt Pending
bits : 2 - 2 (1 bit)
access : read-only

PID99 : Interrupt Pending
bits : 3 - 3 (1 bit)
access : read-only

PID100 : Interrupt Pending
bits : 4 - 4 (1 bit)
access : read-only

PID101 : Interrupt Pending
bits : 5 - 5 (1 bit)
access : read-only

PID102 : Interrupt Pending
bits : 6 - 6 (1 bit)
access : read-only

PID103 : Interrupt Pending
bits : 7 - 7 (1 bit)
access : read-only

PID104 : Interrupt Pending
bits : 8 - 8 (1 bit)
access : read-only

PID105 : Interrupt Pending
bits : 9 - 9 (1 bit)
access : read-only

PID106 : Interrupt Pending
bits : 10 - 10 (1 bit)
access : read-only

PID107 : Interrupt Pending
bits : 11 - 11 (1 bit)
access : read-only

PID108 : Interrupt Pending
bits : 12 - 12 (1 bit)
access : read-only

PID109 : Interrupt Pending
bits : 13 - 13 (1 bit)
access : read-only

PID110 : Interrupt Pending
bits : 14 - 14 (1 bit)
access : read-only

PID111 : Interrupt Pending
bits : 15 - 15 (1 bit)
access : read-only

PID112 : Interrupt Pending
bits : 16 - 16 (1 bit)
access : read-only

PID113 : Interrupt Pending
bits : 17 - 17 (1 bit)
access : read-only

PID114 : Interrupt Pending
bits : 18 - 18 (1 bit)
access : read-only

PID115 : Interrupt Pending
bits : 19 - 19 (1 bit)
access : read-only

PID116 : Interrupt Pending
bits : 20 - 20 (1 bit)
access : read-only

PID117 : Interrupt Pending
bits : 21 - 21 (1 bit)
access : read-only

PID118 : Interrupt Pending
bits : 22 - 22 (1 bit)
access : read-only

PID119 : Interrupt Pending
bits : 23 - 23 (1 bit)
access : read-only

PID120 : Interrupt Pending
bits : 24 - 24 (1 bit)
access : read-only

PID121 : Interrupt Pending
bits : 25 - 25 (1 bit)
access : read-only

PID122 : Interrupt Pending
bits : 26 - 26 (1 bit)
access : read-only

PID123 : Interrupt Pending
bits : 27 - 27 (1 bit)
access : read-only

PID124 : Interrupt Pending
bits : 28 - 28 (1 bit)
access : read-only

PID125 : Interrupt Pending
bits : 29 - 29 (1 bit)
access : read-only

PID126 : Interrupt Pending
bits : 30 - 30 (1 bit)
access : read-only

PID127 : Interrupt Pending
bits : 31 - 31 (1 bit)
access : read-only


IMR

Interrupt Mask Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTM

INTM : Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only


CISR

Core Interrupt Status Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CISR CISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NFIQ NIRQ

NFIQ : NFIQ Status
bits : 0 - 0 (1 bit)
access : read-only

NIRQ : NIRQ Status
bits : 1 - 1 (1 bit)
access : read-only


EOICR

End of Interrupt Command Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EOICR EOICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENDIT

ENDIT : Interrupt Processing Complete Command
bits : 0 - 0 (1 bit)
access : write-only


SPU

Spurious Interrupt Vector Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPU SPU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIVR

SIVR : Spurious Interrupt Vector Register
bits : 0 - 31 (32 bit)
access : read-write


SMR

Source Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMR SMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIOR SRCTYPE

PRIOR : Priority Level
bits : 0 - 2 (3 bit)
access : read-write

SRCTYPE : Interrupt Source Type
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

0x0 : INT_LEVEL_SENSITIVE

High level Sensitive for internal sourceLow level Sensitive for external source

0x1 : INT_EDGE_TRIGGERED

Positive edge triggered for internal sourceNegative edge triggered for external source

0x2 : EXT_HIGH_LEVEL

High level Sensitive for internal sourceHigh level Sensitive for external source

0x3 : EXT_POSITIVE_EDGE

Positive edge triggered for internal sourcePositive edge triggered for external source

End of enumeration elements list.


IECR

Interrupt Enable Command Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IECR IECR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTEN

INTEN : Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only


IDCR

Interrupt Disable Command Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDCR IDCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTD

INTD : Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only


ICCR

Interrupt Clear Command Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICCR ICCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTCLR

INTCLR : Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only


ISCR

Interrupt Set Command Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ISCR ISCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSET

INTSET : Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only


FFER

Fast Forcing Enable Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FFER FFER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FFEN

FFEN : Fast Forcing Enable
bits : 0 - 0 (1 bit)
access : write-only


FFDR

Fast Forcing Disable Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FFDR FFDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FFDIS

FFDIS : Fast Forcing Disable
bits : 0 - 0 (1 bit)
access : write-only


FFSR

Fast Forcing Status Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FFSR FFSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FFS

FFS : Fast Forcing Status
bits : 0 - 0 (1 bit)
access : read-only


DCR

Debug Control Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCR DCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROT GMSK

PROT : Protection Mode
bits : 0 - 0 (1 bit)
access : read-write

GMSK : General Mask
bits : 1 - 1 (1 bit)
access : read-write


SVR

Source Vector Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SVR SVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTOR

VECTOR : Source Vector
bits : 0 - 31 (32 bit)
access : read-write


WPMR

Write Protect Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protect KEY
bits : 8 - 31 (24 bit)
access : read-write


WPSR

Write Protect Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protect Violation Status
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protect Violation Source
bits : 8 - 23 (16 bit)
access : read-only



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