\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
PWM Clock Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVA : CLKA, CLKB Divide Factor
bits : 0 - 7 (8 bit)
access : read-write
PREA : CLKA, CLKB Source Clock Selection
bits : 8 - 11 (4 bit)
access : read-write
DIVB : CLKA, CLKB Divide Factor
bits : 16 - 23 (8 bit)
access : read-write
PREB : CLKA, CLKB Source Clock Selection
bits : 24 - 27 (4 bit)
access : read-write
PWM Interrupt Enable Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Counter Event on Channel 0 Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
CHID1 : Counter Event on Channel 1 Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
CHID2 : Counter Event on Channel 2 Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
CHID3 : Counter Event on Channel 3 Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
CHID4 : Counter Event on Channel 4 Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
CHID5 : Counter Event on Channel 5 Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
CHID6 : Counter Event on Channel 6 Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
CHID7 : Counter Event on Channel 7 Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
FCHID0 : Fault Protection Trigger on Channel 0 Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
FCHID1 : Fault Protection Trigger on Channel 1 Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only
FCHID2 : Fault Protection Trigger on Channel 2 Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
FCHID3 : Fault Protection Trigger on Channel 3 Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
FCHID4 : Fault Protection Trigger on Channel 4 Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only
FCHID5 : Fault Protection Trigger on Channel 5 Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only
FCHID6 : Fault Protection Trigger on Channel 6 Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only
FCHID7 : Fault Protection Trigger on Channel 7 Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only
Transmit Pointer Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPTR : Transmit Counter Register
bits : 0 - 31 (32 bit)
access : read-write
Transmit Counter Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCTR : Transmit Counter Register
bits : 0 - 15 (16 bit)
access : read-write
Transmit Next Pointer Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNPTR : Transmit Next Pointer
bits : 0 - 31 (32 bit)
access : read-write
Transmit Next Counter Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNCTR : Transmit Counter Next
bits : 0 - 15 (16 bit)
access : read-write
Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only
RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only
TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only
Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only
PWM Comparison 0 Value Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Comparison 0 Value Update Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only
PWM Comparison 0 Mode Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write
PWM Comparison 0 Mode Update Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only
PWM Interrupt Disable Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Counter Event on Channel 0 Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
CHID1 : Counter Event on Channel 1 Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
CHID2 : Counter Event on Channel 2 Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
CHID3 : Counter Event on Channel 3 Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
CHID4 : Counter Event on Channel 4 Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
CHID5 : Counter Event on Channel 5 Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
CHID6 : Counter Event on Channel 6 Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
CHID7 : Counter Event on Channel 7 Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
FCHID0 : Fault Protection Trigger on Channel 0 Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
FCHID1 : Fault Protection Trigger on Channel 1 Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only
FCHID2 : Fault Protection Trigger on Channel 2 Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
FCHID3 : Fault Protection Trigger on Channel 3 Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
FCHID4 : Fault Protection Trigger on Channel 4 Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only
FCHID5 : Fault Protection Trigger on Channel 5 Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only
FCHID6 : Fault Protection Trigger on Channel 6 Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only
FCHID7 : Fault Protection Trigger on Channel 7 Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only
PWM Comparison 1 Value Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Comparison 1 Value Update Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only
PWM Comparison 1 Mode Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write
PWM Comparison 1 Mode Update Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only
PWM Comparison 2 Value Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Comparison 2 Value Update Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only
PWM Comparison 2 Mode Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write
PWM Comparison 2 Mode Update Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only
PWM Comparison 3 Value Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Comparison 3 Value Update Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only
PWM Comparison 3 Mode Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write
PWM Comparison 3 Mode Update Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only
PWM Comparison 4 Value Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Comparison 4 Value Update Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only
PWM Event Line 0 Mode Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL0 : Comparison 0 Selection
bits : 0 - 0 (1 bit)
access : read-write
CSEL1 : Comparison 1 Selection
bits : 1 - 1 (1 bit)
access : read-write
CSEL2 : Comparison 2 Selection
bits : 2 - 2 (1 bit)
access : read-write
CSEL3 : Comparison 3 Selection
bits : 3 - 3 (1 bit)
access : read-write
CSEL4 : Comparison 4 Selection
bits : 4 - 4 (1 bit)
access : read-write
CSEL5 : Comparison 5 Selection
bits : 5 - 5 (1 bit)
access : read-write
CSEL6 : Comparison 6 Selection
bits : 6 - 6 (1 bit)
access : read-write
CSEL7 : Comparison 7 Selection
bits : 7 - 7 (1 bit)
access : read-write
PWM Comparison 4 Mode Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write
PWM Comparison 4 Mode Update Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only
PWM Interrupt Mask Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Counter Event on Channel 0 Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
CHID1 : Counter Event on Channel 1 Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
CHID2 : Counter Event on Channel 2 Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
CHID3 : Counter Event on Channel 3 Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
CHID4 : Counter Event on Channel 4 Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
CHID5 : Counter Event on Channel 5 Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
CHID6 : Counter Event on Channel 6 Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
CHID7 : Counter Event on Channel 7 Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only
FCHID0 : Fault Protection Trigger on Channel 0 Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
FCHID1 : Fault Protection Trigger on Channel 1 Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only
FCHID2 : Fault Protection Trigger on Channel 2 Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only
FCHID3 : Fault Protection Trigger on Channel 3 Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only
FCHID4 : Fault Protection Trigger on Channel 4 Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only
FCHID5 : Fault Protection Trigger on Channel 5 Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only
FCHID6 : Fault Protection Trigger on Channel 6 Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only
FCHID7 : Fault Protection Trigger on Channel 7 Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only
PWM Comparison 5 Value Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Comparison 5 Value Update Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only
PWM Comparison 5 Mode Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write
PWM Comparison 5 Mode Update Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only
PWM Comparison 6 Value Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Comparison 6 Value Update Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only
PWM Comparison 6 Mode Register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write
PWM Comparison 6 Mode Update Register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only
PWM Comparison 7 Value Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Comparison 7 Value Update Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only
PWM Comparison 7 Mode Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write
PWM Comparison 7 Mode Update Register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only
PWM Interrupt Status Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Counter Event on Channel 0
bits : 0 - 0 (1 bit)
access : read-only
CHID1 : Counter Event on Channel 1
bits : 1 - 1 (1 bit)
access : read-only
CHID2 : Counter Event on Channel 2
bits : 2 - 2 (1 bit)
access : read-only
CHID3 : Counter Event on Channel 3
bits : 3 - 3 (1 bit)
access : read-only
CHID4 : Counter Event on Channel 4
bits : 4 - 4 (1 bit)
access : read-only
CHID5 : Counter Event on Channel 5
bits : 5 - 5 (1 bit)
access : read-only
CHID6 : Counter Event on Channel 6
bits : 6 - 6 (1 bit)
access : read-only
CHID7 : Counter Event on Channel 7
bits : 7 - 7 (1 bit)
access : read-only
FCHID0 : Fault Protection Trigger on Channel 0
bits : 16 - 16 (1 bit)
access : read-only
FCHID1 : Fault Protection Trigger on Channel 1
bits : 17 - 17 (1 bit)
access : read-only
FCHID2 : Fault Protection Trigger on Channel 2
bits : 18 - 18 (1 bit)
access : read-only
FCHID3 : Fault Protection Trigger on Channel 3
bits : 19 - 19 (1 bit)
access : read-only
FCHID4 : Fault Protection Trigger on Channel 4
bits : 20 - 20 (1 bit)
access : read-only
FCHID5 : Fault Protection Trigger on Channel 5
bits : 21 - 21 (1 bit)
access : read-only
FCHID6 : Fault Protection Trigger on Channel 6
bits : 22 - 22 (1 bit)
access : read-only
FCHID7 : Fault Protection Trigger on Channel 7
bits : 23 - 23 (1 bit)
access : read-only
PWM Sync Channels Mode Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC0 : Synchronous Channel 0
bits : 0 - 0 (1 bit)
access : read-write
SYNC1 : Synchronous Channel 1
bits : 1 - 1 (1 bit)
access : read-write
SYNC2 : Synchronous Channel 2
bits : 2 - 2 (1 bit)
access : read-write
SYNC3 : Synchronous Channel 3
bits : 3 - 3 (1 bit)
access : read-write
SYNC4 : Synchronous Channel 4
bits : 4 - 4 (1 bit)
access : read-write
SYNC5 : Synchronous Channel 5
bits : 5 - 5 (1 bit)
access : read-write
SYNC6 : Synchronous Channel 6
bits : 6 - 6 (1 bit)
access : read-write
SYNC7 : Synchronous Channel 7
bits : 7 - 7 (1 bit)
access : read-write
UPDM : Synchronous Channels Update Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : MODE0
Manual write of double buffer registers and manual update of synchronous channels
0x1 : MODE1
Manual write of double buffer registers and automatic update of synchronous channels
0x2 : MODE2
Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels
End of enumeration elements list.
PTRM : PDC Transfer Request Mode
bits : 20 - 20 (1 bit)
access : read-write
PTRCS : PDC Transfer Request Comparison Selection
bits : 21 - 23 (3 bit)
access : read-write
PWM Channel Mode Register (ch_num = 0)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Master clock
0x1 : MCK_DIV_2
Master clock/2
0x2 : MCK_DIV_4
Master clock/4
0x3 : MCK_DIV_8
Master clock/8
0x4 : MCK_DIV_16
Master clock/16
0x5 : MCK_DIV_32
Master clock/32
0x6 : MCK_DIV_64
Master clock/64
0x7 : MCK_DIV_128
Master clock/128
0x8 : MCK_DIV_256
Master clock/256
0x9 : MCK_DIV_512
Master clock/512
0xA : MCK_DIV_1024
Master clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write
PWM Channel Duty Cycle Register (ch_num = 0)
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Duty Cycle Update Register (ch_num = 0)
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Period Register (ch_num = 0)
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Period Update Register (ch_num = 0)
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Counter Register (ch_num = 0)
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only
PWM Channel Dead Time Register (ch_num = 0)
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write
PWM Channel Dead Time Update Register (ch_num = 0)
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only
PWM Channel Mode Register (ch_num = 1)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Master clock
0x1 : MCK_DIV_2
Master clock/2
0x2 : MCK_DIV_4
Master clock/4
0x3 : MCK_DIV_8
Master clock/8
0x4 : MCK_DIV_16
Master clock/16
0x5 : MCK_DIV_32
Master clock/32
0x6 : MCK_DIV_64
Master clock/64
0x7 : MCK_DIV_128
Master clock/128
0x8 : MCK_DIV_256
Master clock/256
0x9 : MCK_DIV_512
Master clock/512
0xA : MCK_DIV_1024
Master clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write
PWM Channel Duty Cycle Register (ch_num = 1)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Duty Cycle Update Register (ch_num = 1)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Period Register (ch_num = 1)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Period Update Register (ch_num = 1)
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Counter Register (ch_num = 1)
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only
PWM Channel Dead Time Register (ch_num = 1)
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write
PWM Channel Dead Time Update Register (ch_num = 1)
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only
PWM Channel Mode Register (ch_num = 2)
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Master clock
0x1 : MCK_DIV_2
Master clock/2
0x2 : MCK_DIV_4
Master clock/4
0x3 : MCK_DIV_8
Master clock/8
0x4 : MCK_DIV_16
Master clock/16
0x5 : MCK_DIV_32
Master clock/32
0x6 : MCK_DIV_64
Master clock/64
0x7 : MCK_DIV_128
Master clock/128
0x8 : MCK_DIV_256
Master clock/256
0x9 : MCK_DIV_512
Master clock/512
0xA : MCK_DIV_1024
Master clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write
PWM Channel Duty Cycle Register (ch_num = 2)
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Duty Cycle Update Register (ch_num = 2)
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Period Register (ch_num = 2)
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Period Update Register (ch_num = 2)
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Counter Register (ch_num = 2)
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only
PWM Channel Dead Time Register (ch_num = 2)
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write
PWM Channel Dead Time Update Register (ch_num = 2)
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only
PWM Channel Mode Register (ch_num = 3)
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Master clock
0x1 : MCK_DIV_2
Master clock/2
0x2 : MCK_DIV_4
Master clock/4
0x3 : MCK_DIV_8
Master clock/8
0x4 : MCK_DIV_16
Master clock/16
0x5 : MCK_DIV_32
Master clock/32
0x6 : MCK_DIV_64
Master clock/64
0x7 : MCK_DIV_128
Master clock/128
0x8 : MCK_DIV_256
Master clock/256
0x9 : MCK_DIV_512
Master clock/512
0xA : MCK_DIV_1024
Master clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write
PWM Channel Duty Cycle Register (ch_num = 3)
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Duty Cycle Update Register (ch_num = 3)
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Period Register (ch_num = 3)
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Period Update Register (ch_num = 3)
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Counter Register (ch_num = 3)
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only
PWM Channel Dead Time Register (ch_num = 3)
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write
PWM Channel Dead Time Update Register (ch_num = 3)
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only
PWM Sync Channels Update Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPDULOCK : Synchronous Channels Update Unlock
bits : 0 - 0 (1 bit)
access : read-write
PWM Channel Mode Register (ch_num = 4)
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Master clock
0x1 : MCK_DIV_2
Master clock/2
0x2 : MCK_DIV_4
Master clock/4
0x3 : MCK_DIV_8
Master clock/8
0x4 : MCK_DIV_16
Master clock/16
0x5 : MCK_DIV_32
Master clock/32
0x6 : MCK_DIV_64
Master clock/64
0x7 : MCK_DIV_128
Master clock/128
0x8 : MCK_DIV_256
Master clock/256
0x9 : MCK_DIV_512
Master clock/512
0xA : MCK_DIV_1024
Master clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write
PWM Channel Duty Cycle Register (ch_num = 4)
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Duty Cycle Update Register (ch_num = 4)
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Period Register (ch_num = 4)
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Period Update Register (ch_num = 4)
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Counter Register (ch_num = 4)
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only
PWM Channel Dead Time Register (ch_num = 4)
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write
PWM Channel Dead Time Update Register (ch_num = 4)
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only
PWM Channel Mode Register (ch_num = 5)
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Master clock
0x1 : MCK_DIV_2
Master clock/2
0x2 : MCK_DIV_4
Master clock/4
0x3 : MCK_DIV_8
Master clock/8
0x4 : MCK_DIV_16
Master clock/16
0x5 : MCK_DIV_32
Master clock/32
0x6 : MCK_DIV_64
Master clock/64
0x7 : MCK_DIV_128
Master clock/128
0x8 : MCK_DIV_256
Master clock/256
0x9 : MCK_DIV_512
Master clock/512
0xA : MCK_DIV_1024
Master clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write
PWM Channel Duty Cycle Register (ch_num = 5)
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Duty Cycle Update Register (ch_num = 5)
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Period Register (ch_num = 5)
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Period Update Register (ch_num = 5)
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Counter Register (ch_num = 5)
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only
PWM Channel Dead Time Register (ch_num = 5)
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write
PWM Channel Dead Time Update Register (ch_num = 5)
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only
PWM Sync Channels Update Period Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPR : Update Period
bits : 0 - 3 (4 bit)
access : read-write
UPRCNT : Update Period Counter
bits : 4 - 7 (4 bit)
access : read-write
PWM Channel Mode Register (ch_num = 6)
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Master clock
0x1 : MCK_DIV_2
Master clock/2
0x2 : MCK_DIV_4
Master clock/4
0x3 : MCK_DIV_8
Master clock/8
0x4 : MCK_DIV_16
Master clock/16
0x5 : MCK_DIV_32
Master clock/32
0x6 : MCK_DIV_64
Master clock/64
0x7 : MCK_DIV_128
Master clock/128
0x8 : MCK_DIV_256
Master clock/256
0x9 : MCK_DIV_512
Master clock/512
0xA : MCK_DIV_1024
Master clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write
PWM Channel Duty Cycle Register (ch_num = 6)
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Duty Cycle Update Register (ch_num = 6)
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Period Register (ch_num = 6)
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Period Update Register (ch_num = 6)
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Counter Register (ch_num = 6)
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only
PWM Channel Dead Time Register (ch_num = 6)
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write
PWM Channel Dead Time Update Register (ch_num = 6)
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only
PWM Channel Mode Register (ch_num = 7)
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Master clock
0x1 : MCK_DIV_2
Master clock/2
0x2 : MCK_DIV_4
Master clock/4
0x3 : MCK_DIV_8
Master clock/8
0x4 : MCK_DIV_16
Master clock/16
0x5 : MCK_DIV_32
Master clock/32
0x6 : MCK_DIV_64
Master clock/64
0x7 : MCK_DIV_128
Master clock/128
0x8 : MCK_DIV_256
Master clock/256
0x9 : MCK_DIV_512
Master clock/512
0xA : MCK_DIV_1024
Master clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write
PWM Channel Duty Cycle Register (ch_num = 7)
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Duty Cycle Update Register (ch_num = 7)
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Period Register (ch_num = 7)
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Period Update Register (ch_num = 7)
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Counter Register (ch_num = 7)
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only
PWM Channel Dead Time Register (ch_num = 7)
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write
PWM Channel Dead Time Update Register (ch_num = 7)
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only
PWM Sync Channels Update Period Update Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UPRUPD : Update Period Update
bits : 0 - 3 (4 bit)
access : write-only
PWM Interrupt Enable Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRDY : Write Ready for Synchronous Channels Update Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
ENDTX : PDC End of TX Buffer Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
TXBUFE : PDC TX Buffer Empty Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
UNRE : Synchronous Channels Update Underrun Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
CMPM0 : Comparison 0 Match Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
CMPM1 : Comparison 1 Match Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
CMPM2 : Comparison 2 Match Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
CMPM3 : Comparison 3 Match Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
CMPM4 : Comparison 4 Match Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
CMPM5 : Comparison 5 Match Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
CMPM6 : Comparison 6 Match Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
CMPM7 : Comparison 7 Match Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
CMPU0 : Comparison 0 Update Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
CMPU1 : Comparison 1 Update Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only
CMPU2 : Comparison 2 Update Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
CMPU3 : Comparison 3 Update Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
CMPU4 : Comparison 4 Update Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only
CMPU5 : Comparison 5 Update Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only
CMPU6 : Comparison 6 Update Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only
CMPU7 : Comparison 7 Update Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only
PWM Interrupt Disable Register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRDY : Write Ready for Synchronous Channels Update Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
ENDTX : PDC End of TX Buffer Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
TXBUFE : PDC TX Buffer Empty Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
UNRE : Synchronous Channels Update Underrun Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
CMPM0 : Comparison 0 Match Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
CMPM1 : Comparison 1 Match Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
CMPM2 : Comparison 2 Match Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
CMPM3 : Comparison 3 Match Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
CMPM4 : Comparison 4 Match Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
CMPM5 : Comparison 5 Match Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
CMPM6 : Comparison 6 Match Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
CMPM7 : Comparison 7 Match Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
CMPU0 : Comparison 0 Update Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
CMPU1 : Comparison 1 Update Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only
CMPU2 : Comparison 2 Update Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
CMPU3 : Comparison 3 Update Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
CMPU4 : Comparison 4 Update Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only
CMPU5 : Comparison 5 Update Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only
CMPU6 : Comparison 6 Update Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only
CMPU7 : Comparison 7 Update Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only
PWM Interrupt Mask Register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WRDY : Write Ready for Synchronous Channels Update Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
ENDTX : PDC End of TX Buffer Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
TXBUFE : PDC TX Buffer Empty Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
UNRE : Synchronous Channels Update Underrun Error Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
CMPM0 : Comparison 0 Match Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
CMPM1 : Comparison 1 Match Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
CMPM2 : Comparison 2 Match Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
CMPM3 : Comparison 3 Match Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only
CMPM4 : Comparison 4 Match Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only
CMPM5 : Comparison 5 Match Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
CMPM6 : Comparison 6 Match Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only
CMPM7 : Comparison 7 Match Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only
CMPU0 : Comparison 0 Update Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
CMPU1 : Comparison 1 Update Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only
CMPU2 : Comparison 2 Update Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only
CMPU3 : Comparison 3 Update Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only
CMPU4 : Comparison 4 Update Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only
CMPU5 : Comparison 5 Update Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only
CMPU6 : Comparison 6 Update Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only
CMPU7 : Comparison 7 Update Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only
PWM Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : write-only
CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : write-only
CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : write-only
CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : write-only
CHID4 : Channel ID
bits : 4 - 4 (1 bit)
access : write-only
CHID5 : Channel ID
bits : 5 - 5 (1 bit)
access : write-only
CHID6 : Channel ID
bits : 6 - 6 (1 bit)
access : write-only
CHID7 : Channel ID
bits : 7 - 7 (1 bit)
access : write-only
PWM Interrupt Status Register 2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WRDY : Write Ready for Synchronous Channels Update
bits : 0 - 0 (1 bit)
access : read-only
ENDTX : PDC End of TX Buffer
bits : 1 - 1 (1 bit)
access : read-only
TXBUFE : PDC TX Buffer Empty
bits : 2 - 2 (1 bit)
access : read-only
UNRE : Synchronous Channels Update Underrun Error
bits : 3 - 3 (1 bit)
access : read-only
CMPM0 : Comparison 0 Match
bits : 8 - 8 (1 bit)
access : read-only
CMPM1 : Comparison 1 Match
bits : 9 - 9 (1 bit)
access : read-only
CMPM2 : Comparison 2 Match
bits : 10 - 10 (1 bit)
access : read-only
CMPM3 : Comparison 3 Match
bits : 11 - 11 (1 bit)
access : read-only
CMPM4 : Comparison 4 Match
bits : 12 - 12 (1 bit)
access : read-only
CMPM5 : Comparison 5 Match
bits : 13 - 13 (1 bit)
access : read-only
CMPM6 : Comparison 6 Match
bits : 14 - 14 (1 bit)
access : read-only
CMPM7 : Comparison 7 Match
bits : 15 - 15 (1 bit)
access : read-only
CMPU0 : Comparison 0 Update
bits : 16 - 16 (1 bit)
access : read-only
CMPU1 : Comparison 1 Update
bits : 17 - 17 (1 bit)
access : read-only
CMPU2 : Comparison 2 Update
bits : 18 - 18 (1 bit)
access : read-only
CMPU3 : Comparison 3 Update
bits : 19 - 19 (1 bit)
access : read-only
CMPU4 : Comparison 4 Update
bits : 20 - 20 (1 bit)
access : read-only
CMPU5 : Comparison 5 Update
bits : 21 - 21 (1 bit)
access : read-only
CMPU6 : Comparison 6 Update
bits : 22 - 22 (1 bit)
access : read-only
CMPU7 : Comparison 7 Update
bits : 23 - 23 (1 bit)
access : read-only
PWM Output Override Value Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OOVH0 : Output Override Value for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : read-write
OOVH1 : Output Override Value for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : read-write
OOVH2 : Output Override Value for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : read-write
OOVH3 : Output Override Value for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : read-write
OOVH4 : Output Override Value for PWMH output of the channel 4
bits : 4 - 4 (1 bit)
access : read-write
OOVH5 : Output Override Value for PWMH output of the channel 5
bits : 5 - 5 (1 bit)
access : read-write
OOVH6 : Output Override Value for PWMH output of the channel 6
bits : 6 - 6 (1 bit)
access : read-write
OOVH7 : Output Override Value for PWMH output of the channel 7
bits : 7 - 7 (1 bit)
access : read-write
OOVL0 : Output Override Value for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : read-write
OOVL1 : Output Override Value for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : read-write
OOVL2 : Output Override Value for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : read-write
OOVL3 : Output Override Value for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : read-write
OOVL4 : Output Override Value for PWML output of the channel 4
bits : 20 - 20 (1 bit)
access : read-write
OOVL5 : Output Override Value for PWML output of the channel 5
bits : 21 - 21 (1 bit)
access : read-write
OOVL6 : Output Override Value for PWML output of the channel 6
bits : 22 - 22 (1 bit)
access : read-write
OOVL7 : Output Override Value for PWML output of the channel 7
bits : 23 - 23 (1 bit)
access : read-write
PWM Output Selection Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSH0 : Output Selection for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : read-write
OSH1 : Output Selection for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : read-write
OSH2 : Output Selection for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : read-write
OSH3 : Output Selection for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : read-write
OSH4 : Output Selection for PWMH output of the channel 4
bits : 4 - 4 (1 bit)
access : read-write
OSH5 : Output Selection for PWMH output of the channel 5
bits : 5 - 5 (1 bit)
access : read-write
OSH6 : Output Selection for PWMH output of the channel 6
bits : 6 - 6 (1 bit)
access : read-write
OSH7 : Output Selection for PWMH output of the channel 7
bits : 7 - 7 (1 bit)
access : read-write
OSL0 : Output Selection for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : read-write
OSL1 : Output Selection for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : read-write
OSL2 : Output Selection for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : read-write
OSL3 : Output Selection for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : read-write
OSL4 : Output Selection for PWML output of the channel 4
bits : 20 - 20 (1 bit)
access : read-write
OSL5 : Output Selection for PWML output of the channel 5
bits : 21 - 21 (1 bit)
access : read-write
OSL6 : Output Selection for PWML output of the channel 6
bits : 22 - 22 (1 bit)
access : read-write
OSL7 : Output Selection for PWML output of the channel 7
bits : 23 - 23 (1 bit)
access : read-write
PWM Output Selection Set Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSSH0 : Output Selection Set for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : write-only
OSSH1 : Output Selection Set for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : write-only
OSSH2 : Output Selection Set for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : write-only
OSSH3 : Output Selection Set for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : write-only
OSSH4 : Output Selection Set for PWMH output of the channel 4
bits : 4 - 4 (1 bit)
access : write-only
OSSH5 : Output Selection Set for PWMH output of the channel 5
bits : 5 - 5 (1 bit)
access : write-only
OSSH6 : Output Selection Set for PWMH output of the channel 6
bits : 6 - 6 (1 bit)
access : write-only
OSSH7 : Output Selection Set for PWMH output of the channel 7
bits : 7 - 7 (1 bit)
access : write-only
OSSL0 : Output Selection Set for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : write-only
OSSL1 : Output Selection Set for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : write-only
OSSL2 : Output Selection Set for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : write-only
OSSL3 : Output Selection Set for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : write-only
OSSL4 : Output Selection Set for PWML output of the channel 4
bits : 20 - 20 (1 bit)
access : write-only
OSSL5 : Output Selection Set for PWML output of the channel 5
bits : 21 - 21 (1 bit)
access : write-only
OSSL6 : Output Selection Set for PWML output of the channel 6
bits : 22 - 22 (1 bit)
access : write-only
OSSL7 : Output Selection Set for PWML output of the channel 7
bits : 23 - 23 (1 bit)
access : write-only
PWM Output Selection Clear Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSCH0 : Output Selection Clear for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : write-only
OSCH1 : Output Selection Clear for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : write-only
OSCH2 : Output Selection Clear for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : write-only
OSCH3 : Output Selection Clear for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : write-only
OSCH4 : Output Selection Clear for PWMH output of the channel 4
bits : 4 - 4 (1 bit)
access : write-only
OSCH5 : Output Selection Clear for PWMH output of the channel 5
bits : 5 - 5 (1 bit)
access : write-only
OSCH6 : Output Selection Clear for PWMH output of the channel 6
bits : 6 - 6 (1 bit)
access : write-only
OSCH7 : Output Selection Clear for PWMH output of the channel 7
bits : 7 - 7 (1 bit)
access : write-only
OSCL0 : Output Selection Clear for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : write-only
OSCL1 : Output Selection Clear for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : write-only
OSCL2 : Output Selection Clear for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : write-only
OSCL3 : Output Selection Clear for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : write-only
OSCL4 : Output Selection Clear for PWML output of the channel 4
bits : 20 - 20 (1 bit)
access : write-only
OSCL5 : Output Selection Clear for PWML output of the channel 5
bits : 21 - 21 (1 bit)
access : write-only
OSCL6 : Output Selection Clear for PWML output of the channel 6
bits : 22 - 22 (1 bit)
access : write-only
OSCL7 : Output Selection Clear for PWML output of the channel 7
bits : 23 - 23 (1 bit)
access : write-only
PWM Output Selection Set Update Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSSUPH0 : Output Selection Set for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : write-only
OSSUPH1 : Output Selection Set for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : write-only
OSSUPH2 : Output Selection Set for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : write-only
OSSUPH3 : Output Selection Set for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : write-only
OSSUPH4 : Output Selection Set for PWMH output of the channel 4
bits : 4 - 4 (1 bit)
access : write-only
OSSUPH5 : Output Selection Set for PWMH output of the channel 5
bits : 5 - 5 (1 bit)
access : write-only
OSSUPH6 : Output Selection Set for PWMH output of the channel 6
bits : 6 - 6 (1 bit)
access : write-only
OSSUPH7 : Output Selection Set for PWMH output of the channel 7
bits : 7 - 7 (1 bit)
access : write-only
OSSUPL0 : Output Selection Set for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : write-only
OSSUPL1 : Output Selection Set for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : write-only
OSSUPL2 : Output Selection Set for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : write-only
OSSUPL3 : Output Selection Set for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : write-only
OSSUPL4 : Output Selection Set for PWML output of the channel 4
bits : 20 - 20 (1 bit)
access : write-only
OSSUPL5 : Output Selection Set for PWML output of the channel 5
bits : 21 - 21 (1 bit)
access : write-only
OSSUPL6 : Output Selection Set for PWML output of the channel 6
bits : 22 - 22 (1 bit)
access : write-only
OSSUPL7 : Output Selection Set for PWML output of the channel 7
bits : 23 - 23 (1 bit)
access : write-only
PWM Output Selection Clear Update Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSCUPH0 : Output Selection Clear for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : write-only
OSCUPH1 : Output Selection Clear for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : write-only
OSCUPH2 : Output Selection Clear for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : write-only
OSCUPH3 : Output Selection Clear for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : write-only
OSCUPH4 : Output Selection Clear for PWMH output of the channel 4
bits : 4 - 4 (1 bit)
access : write-only
OSCUPH5 : Output Selection Clear for PWMH output of the channel 5
bits : 5 - 5 (1 bit)
access : write-only
OSCUPH6 : Output Selection Clear for PWMH output of the channel 6
bits : 6 - 6 (1 bit)
access : write-only
OSCUPH7 : Output Selection Clear for PWMH output of the channel 7
bits : 7 - 7 (1 bit)
access : write-only
OSCUPL0 : Output Selection Clear for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : write-only
OSCUPL1 : Output Selection Clear for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : write-only
OSCUPL2 : Output Selection Clear for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : write-only
OSCUPL3 : Output Selection Clear for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : write-only
OSCUPL4 : Output Selection Clear for PWML output of the channel 4
bits : 20 - 20 (1 bit)
access : write-only
OSCUPL5 : Output Selection Clear for PWML output of the channel 5
bits : 21 - 21 (1 bit)
access : write-only
OSCUPL6 : Output Selection Clear for PWML output of the channel 6
bits : 22 - 22 (1 bit)
access : write-only
OSCUPL7 : Output Selection Clear for PWML output of the channel 7
bits : 23 - 23 (1 bit)
access : write-only
PWM Fault Mode Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPOL : Fault Polarity (fault input bit varies from 0 to 5)
bits : 0 - 7 (8 bit)
access : read-write
FMOD : Fault Activation Mode (fault input bit varies from 0 to 5)
bits : 8 - 15 (8 bit)
access : read-write
FFIL : Fault Filtering (fault input bit varies from 0 to 5)
bits : 16 - 23 (8 bit)
access : read-write
PWM Fault Status Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FIV : Fault Input Value (fault input bit varies from 0 to 5)
bits : 0 - 7 (8 bit)
access : read-only
FS : Fault Status (fault input bit varies from 0 to 5)
bits : 8 - 15 (8 bit)
access : read-only
PWM Fault Clear Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FCLR : Fault Clear (fault input bit varies from 0 to 5)
bits : 0 - 7 (8 bit)
access : write-only
PWM Fault Protection Value Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPVH0 : Fault Protection Value for PWMH output on channel 0
bits : 0 - 0 (1 bit)
access : read-write
FPVH1 : Fault Protection Value for PWMH output on channel 1
bits : 1 - 1 (1 bit)
access : read-write
FPVH2 : Fault Protection Value for PWMH output on channel 2
bits : 2 - 2 (1 bit)
access : read-write
FPVH3 : Fault Protection Value for PWMH output on channel 3
bits : 3 - 3 (1 bit)
access : read-write
FPVH4 : Fault Protection Value for PWMH output on channel 4
bits : 4 - 4 (1 bit)
access : read-write
FPVH5 : Fault Protection Value for PWMH output on channel 5
bits : 5 - 5 (1 bit)
access : read-write
FPVH6 : Fault Protection Value for PWMH output on channel 6
bits : 6 - 6 (1 bit)
access : read-write
FPVH7 : Fault Protection Value for PWMH output on channel 7
bits : 7 - 7 (1 bit)
access : read-write
FPVL0 : Fault Protection Value for PWML output on channel 0
bits : 16 - 16 (1 bit)
access : read-write
FPVL1 : Fault Protection Value for PWML output on channel 1
bits : 17 - 17 (1 bit)
access : read-write
FPVL2 : Fault Protection Value for PWML output on channel 2
bits : 18 - 18 (1 bit)
access : read-write
FPVL3 : Fault Protection Value for PWML output on channel 3
bits : 19 - 19 (1 bit)
access : read-write
FPVL4 : Fault Protection Value for PWML output on channel 4
bits : 20 - 20 (1 bit)
access : read-write
FPVL5 : Fault Protection Value for PWML output on channel 5
bits : 21 - 21 (1 bit)
access : read-write
FPVL6 : Fault Protection Value for PWML output on channel 6
bits : 22 - 22 (1 bit)
access : read-write
FPVL7 : Fault Protection Value for PWML output on channel 7
bits : 23 - 23 (1 bit)
access : read-write
PWM Fault Protection Enable Register 1
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPE0 : Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5)
bits : 0 - 7 (8 bit)
access : read-write
FPE1 : Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5)
bits : 8 - 15 (8 bit)
access : read-write
FPE2 : Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5)
bits : 16 - 23 (8 bit)
access : read-write
FPE3 : Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5)
bits : 24 - 31 (8 bit)
access : read-write
PWM Fault Protection Enable Register 2
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPE4 : Fault Protection Enable for channel 4 (fault input bit varies from 0 to 5)
bits : 0 - 7 (8 bit)
access : read-write
FPE5 : Fault Protection Enable for channel 5 (fault input bit varies from 0 to 5)
bits : 8 - 15 (8 bit)
access : read-write
FPE6 : Fault Protection Enable for channel 6 (fault input bit varies from 0 to 5)
bits : 16 - 23 (8 bit)
access : read-write
FPE7 : Fault Protection Enable for channel 7 (fault input bit varies from 0 to 5)
bits : 24 - 31 (8 bit)
access : read-write
PWM Event Line 0 Mode Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CSEL0 : Comparison 0 Selection
bits : 0 - 0 (1 bit)
access : read-write
CSEL1 : Comparison 1 Selection
bits : 1 - 1 (1 bit)
access : read-write
CSEL2 : Comparison 2 Selection
bits : 2 - 2 (1 bit)
access : read-write
CSEL3 : Comparison 3 Selection
bits : 3 - 3 (1 bit)
access : read-write
CSEL4 : Comparison 4 Selection
bits : 4 - 4 (1 bit)
access : read-write
CSEL5 : Comparison 5 Selection
bits : 5 - 5 (1 bit)
access : read-write
CSEL6 : Comparison 6 Selection
bits : 6 - 6 (1 bit)
access : read-write
CSEL7 : Comparison 7 Selection
bits : 7 - 7 (1 bit)
access : read-write
PWM Disable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : write-only
CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : write-only
CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : write-only
CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : write-only
CHID4 : Channel ID
bits : 4 - 4 (1 bit)
access : write-only
CHID5 : Channel ID
bits : 5 - 5 (1 bit)
access : write-only
CHID6 : Channel ID
bits : 6 - 6 (1 bit)
access : write-only
CHID7 : Channel ID
bits : 7 - 7 (1 bit)
access : write-only
PWM Event Line 0 Mode Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CSEL0 : Comparison 0 Selection
bits : 0 - 0 (1 bit)
access : read-write
CSEL1 : Comparison 1 Selection
bits : 1 - 1 (1 bit)
access : read-write
CSEL2 : Comparison 2 Selection
bits : 2 - 2 (1 bit)
access : read-write
CSEL3 : Comparison 3 Selection
bits : 3 - 3 (1 bit)
access : read-write
CSEL4 : Comparison 4 Selection
bits : 4 - 4 (1 bit)
access : read-write
CSEL5 : Comparison 5 Selection
bits : 5 - 5 (1 bit)
access : read-write
CSEL6 : Comparison 6 Selection
bits : 6 - 6 (1 bit)
access : read-write
CSEL7 : Comparison 7 Selection
bits : 7 - 7 (1 bit)
access : read-write
PWM Stepper Motor Mode Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN0 : Gray Count ENable
bits : 0 - 0 (1 bit)
access : read-write
GCEN1 : Gray Count ENable
bits : 1 - 1 (1 bit)
access : read-write
GCEN2 : Gray Count ENable
bits : 2 - 2 (1 bit)
access : read-write
GCEN3 : Gray Count ENable
bits : 3 - 3 (1 bit)
access : read-write
DOWN0 : DOWN Count
bits : 16 - 16 (1 bit)
access : read-write
DOWN1 : DOWN Count
bits : 17 - 17 (1 bit)
access : read-write
DOWN2 : DOWN Count
bits : 18 - 18 (1 bit)
access : read-write
DOWN3 : DOWN Count
bits : 19 - 19 (1 bit)
access : read-write
PWM Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : read-only
CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : read-only
CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : read-only
CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : read-only
CHID4 : Channel ID
bits : 4 - 4 (1 bit)
access : read-only
CHID5 : Channel ID
bits : 5 - 5 (1 bit)
access : read-only
CHID6 : Channel ID
bits : 6 - 6 (1 bit)
access : read-only
CHID7 : Channel ID
bits : 7 - 7 (1 bit)
access : read-only
PWM Write Protect Control Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WPCMD : Write Protect Command
bits : 0 - 1 (2 bit)
access : write-only
WPRG0 : Write Protect Register Group 0
bits : 2 - 2 (1 bit)
access : write-only
WPRG1 : Write Protect Register Group 1
bits : 3 - 3 (1 bit)
access : write-only
WPRG2 : Write Protect Register Group 2
bits : 4 - 4 (1 bit)
access : write-only
WPRG3 : Write Protect Register Group 3
bits : 5 - 5 (1 bit)
access : write-only
WPRG4 : Write Protect Register Group 4
bits : 6 - 6 (1 bit)
access : write-only
WPRG5 : Write Protect Register Group 5
bits : 7 - 7 (1 bit)
access : write-only
WPKEY : Write Protect Key
bits : 8 - 31 (24 bit)
access : write-only
PWM Write Protect Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPSWS0 : Write Protect SW Status
bits : 0 - 0 (1 bit)
access : read-only
WPSWS1 : Write Protect SW Status
bits : 1 - 1 (1 bit)
access : read-only
WPSWS2 : Write Protect SW Status
bits : 2 - 2 (1 bit)
access : read-only
WPSWS3 : Write Protect SW Status
bits : 3 - 3 (1 bit)
access : read-only
WPSWS4 : Write Protect SW Status
bits : 4 - 4 (1 bit)
access : read-only
WPSWS5 : Write Protect SW Status
bits : 5 - 5 (1 bit)
access : read-only
WPVS : Write Protect Violation Status
bits : 7 - 7 (1 bit)
access : read-only
WPHWS0 : Write Protect HW Status
bits : 8 - 8 (1 bit)
access : read-only
WPHWS1 : Write Protect HW Status
bits : 9 - 9 (1 bit)
access : read-only
WPHWS2 : Write Protect HW Status
bits : 10 - 10 (1 bit)
access : read-only
WPHWS3 : Write Protect HW Status
bits : 11 - 11 (1 bit)
access : read-only
WPHWS4 : Write Protect HW Status
bits : 12 - 12 (1 bit)
access : read-only
WPHWS5 : Write Protect HW Status
bits : 13 - 13 (1 bit)
access : read-only
WPVSRC : Write Protect Violation Source
bits : 16 - 31 (16 bit)
access : read-only
PWM Event Line 0 Mode Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL0 : Comparison 0 Selection
bits : 0 - 0 (1 bit)
access : read-write
CSEL1 : Comparison 1 Selection
bits : 1 - 1 (1 bit)
access : read-write
CSEL2 : Comparison 2 Selection
bits : 2 - 2 (1 bit)
access : read-write
CSEL3 : Comparison 3 Selection
bits : 3 - 3 (1 bit)
access : read-write
CSEL4 : Comparison 4 Selection
bits : 4 - 4 (1 bit)
access : read-write
CSEL5 : Comparison 5 Selection
bits : 5 - 5 (1 bit)
access : read-write
CSEL6 : Comparison 6 Selection
bits : 6 - 6 (1 bit)
access : read-write
CSEL7 : Comparison 7 Selection
bits : 7 - 7 (1 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.