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PWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CLK

IER1

TPR

TCR

TNPR

TNCR

PTCR

PTSR

CMPV0

CMPVUPD0

CMPM0

CMPMUPD0

IDR1

CMPV1

CMPVUPD1

CMPM1

CMPMUPD1

CMPV2

CMPVUPD2

CMPM2

CMPMUPD2

CMPV3

CMPVUPD3

CMPM3

CMPMUPD3

CMPV4

CMPVUPD4

ELMR[1]

CMPM4

CMPMUPD4

IMR1

CMPV5

CMPVUPD5

CMPM5

CMPMUPD5

CMPV6

CMPVUPD6

CMPM6

CMPMUPD6

CMPV7

CMPVUPD7

CMPM7

CMPMUPD7

ISR1

SCM

CMR0

CDTY0

CDTYUPD0

CPRD0

CPRDUPD0

CCNT0

DT0

DTUPD0

CMR1

CDTY1

CDTYUPD1

CPRD1

CPRDUPD1

CCNT1

DT1

DTUPD1

CMR2

CDTY2

CDTYUPD2

CPRD2

CPRDUPD2

CCNT2

DT2

DTUPD2

CMR3

CDTY3

CDTYUPD3

CPRD3

CPRDUPD3

CCNT3

DT3

DTUPD3

SCUC

CMR4

CDTY4

CDTYUPD4

CPRD4

CPRDUPD4

CCNT4

DT4

DTUPD4

CMR5

CDTY5

CDTYUPD5

CPRD5

CPRDUPD5

CCNT5

DT5

DTUPD5

SCUP

CMR6

CDTY6

CDTYUPD6

CPRD6

CPRDUPD6

CCNT6

DT6

DTUPD6

CMR7

CDTY7

CDTYUPD7

CPRD7

CPRDUPD7

CCNT7

DT7

DTUPD7

SCUPUPD

IER2

IDR2

IMR2

ENA

ISR2

OOV

OS

OSS

OSC

OSSUPD

OSCUPD

FMR

FSR

FCR

FPV

FPE1

FPE2

ELMR0

DIS

ELMR1

SMMR

SR

WPCR

WPSR

ELMR[0]


CLK

PWM Clock Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVA PREA DIVB PREB

DIVA : CLKA, CLKB Divide Factor
bits : 0 - 7 (8 bit)
access : read-write

PREA : CLKA, CLKB Source Clock Selection
bits : 8 - 11 (4 bit)
access : read-write

DIVB : CLKA, CLKB Divide Factor
bits : 16 - 23 (8 bit)
access : read-write

PREB : CLKA, CLKB Source Clock Selection
bits : 24 - 27 (4 bit)
access : read-write


IER1

PWM Interrupt Enable Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER1 IER1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHID0 CHID1 CHID2 CHID3 CHID4 CHID5 CHID6 CHID7 FCHID0 FCHID1 FCHID2 FCHID3 FCHID4 FCHID5 FCHID6 FCHID7

CHID0 : Counter Event on Channel 0 Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

CHID1 : Counter Event on Channel 1 Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

CHID2 : Counter Event on Channel 2 Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

CHID3 : Counter Event on Channel 3 Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

CHID4 : Counter Event on Channel 4 Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

CHID5 : Counter Event on Channel 5 Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

CHID6 : Counter Event on Channel 6 Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

CHID7 : Counter Event on Channel 7 Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

FCHID0 : Fault Protection Trigger on Channel 0 Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only

FCHID1 : Fault Protection Trigger on Channel 1 Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only

FCHID2 : Fault Protection Trigger on Channel 2 Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

FCHID3 : Fault Protection Trigger on Channel 3 Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only

FCHID4 : Fault Protection Trigger on Channel 4 Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only

FCHID5 : Fault Protection Trigger on Channel 5 Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only

FCHID6 : Fault Protection Trigger on Channel 6 Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only

FCHID7 : Fault Protection Trigger on Channel 7 Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only


TPR

Transmit Pointer Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPR TPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXPTR

TXPTR : Transmit Counter Register
bits : 0 - 31 (32 bit)
access : read-write


TCR

Transmit Counter Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCTR

TXCTR : Transmit Counter Register
bits : 0 - 15 (16 bit)
access : read-write


TNPR

Transmit Next Pointer Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TNPR TNPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXNPTR

TXNPTR : Transmit Next Pointer
bits : 0 - 31 (32 bit)
access : read-write


TNCR

Transmit Next Counter Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TNCR TNCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXNCTR

TXNCTR : Transmit Counter Next
bits : 0 - 15 (16 bit)
access : read-write


PTCR

Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PTCR PTCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN RXTDIS TXTEN TXTDIS

RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only

RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only

TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only

TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only


PTSR

Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PTSR PTSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN TXTEN

RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only

TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only


CMPV0

PWM Comparison 0 Value Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPV0 CMPV0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CV CVM

CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write

CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write


CMPVUPD0

PWM Comparison 0 Value Update Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMPVUPD0 CMPVUPD0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CVUPD CVMUPD

CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only

CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only


CMPM0

PWM Comparison 0 Mode Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPM0 CMPM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN CTR CPR CPRCNT CUPR CUPRCNT

CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write

CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write

CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write

CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write

CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write

CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write


CMPMUPD0

PWM Comparison 0 Mode Update Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMPMUPD0 CMPMUPD0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CENUPD CTRUPD CPRUPD CUPRUPD

CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only

CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only

CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only

CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only


IDR1

PWM Interrupt Disable Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR1 IDR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHID0 CHID1 CHID2 CHID3 CHID4 CHID5 CHID6 CHID7 FCHID0 FCHID1 FCHID2 FCHID3 FCHID4 FCHID5 FCHID6 FCHID7

CHID0 : Counter Event on Channel 0 Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

CHID1 : Counter Event on Channel 1 Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

CHID2 : Counter Event on Channel 2 Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

CHID3 : Counter Event on Channel 3 Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

CHID4 : Counter Event on Channel 4 Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

CHID5 : Counter Event on Channel 5 Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

CHID6 : Counter Event on Channel 6 Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

CHID7 : Counter Event on Channel 7 Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

FCHID0 : Fault Protection Trigger on Channel 0 Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only

FCHID1 : Fault Protection Trigger on Channel 1 Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only

FCHID2 : Fault Protection Trigger on Channel 2 Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

FCHID3 : Fault Protection Trigger on Channel 3 Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only

FCHID4 : Fault Protection Trigger on Channel 4 Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only

FCHID5 : Fault Protection Trigger on Channel 5 Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only

FCHID6 : Fault Protection Trigger on Channel 6 Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only

FCHID7 : Fault Protection Trigger on Channel 7 Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only


CMPV1

PWM Comparison 1 Value Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPV1 CMPV1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CV CVM

CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write

CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write


CMPVUPD1

PWM Comparison 1 Value Update Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMPVUPD1 CMPVUPD1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CVUPD CVMUPD

CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only

CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only


CMPM1

PWM Comparison 1 Mode Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPM1 CMPM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN CTR CPR CPRCNT CUPR CUPRCNT

CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write

CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write

CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write

CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write

CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write

CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write


CMPMUPD1

PWM Comparison 1 Mode Update Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMPMUPD1 CMPMUPD1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CENUPD CTRUPD CPRUPD CUPRUPD

CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only

CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only

CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only

CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only


CMPV2

PWM Comparison 2 Value Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPV2 CMPV2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CV CVM

CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write

CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write


CMPVUPD2

PWM Comparison 2 Value Update Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMPVUPD2 CMPVUPD2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CVUPD CVMUPD

CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only

CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only


CMPM2

PWM Comparison 2 Mode Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPM2 CMPM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN CTR CPR CPRCNT CUPR CUPRCNT

CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write

CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write

CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write

CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write

CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write

CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write


CMPMUPD2

PWM Comparison 2 Mode Update Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMPMUPD2 CMPMUPD2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CENUPD CTRUPD CPRUPD CUPRUPD

CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only

CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only

CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only

CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only


CMPV3

PWM Comparison 3 Value Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPV3 CMPV3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CV CVM

CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write

CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write


CMPVUPD3

PWM Comparison 3 Value Update Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMPVUPD3 CMPVUPD3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CVUPD CVMUPD

CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only

CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only


CMPM3

PWM Comparison 3 Mode Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPM3 CMPM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN CTR CPR CPRCNT CUPR CUPRCNT

CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write

CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write

CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write

CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write

CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write

CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write


CMPMUPD3

PWM Comparison 3 Mode Update Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMPMUPD3 CMPMUPD3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CENUPD CTRUPD CPRUPD CUPRUPD

CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only

CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only

CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only

CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only


CMPV4

PWM Comparison 4 Value Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPV4 CMPV4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CV CVM

CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write

CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write


CMPVUPD4

PWM Comparison 4 Value Update Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMPVUPD4 CMPVUPD4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CVUPD CVMUPD

CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only

CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only


ELMR[1]

PWM Event Line 0 Mode Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ELMR[1] ELMR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSEL0 CSEL1 CSEL2 CSEL3 CSEL4 CSEL5 CSEL6 CSEL7

CSEL0 : Comparison 0 Selection
bits : 0 - 0 (1 bit)
access : read-write

CSEL1 : Comparison 1 Selection
bits : 1 - 1 (1 bit)
access : read-write

CSEL2 : Comparison 2 Selection
bits : 2 - 2 (1 bit)
access : read-write

CSEL3 : Comparison 3 Selection
bits : 3 - 3 (1 bit)
access : read-write

CSEL4 : Comparison 4 Selection
bits : 4 - 4 (1 bit)
access : read-write

CSEL5 : Comparison 5 Selection
bits : 5 - 5 (1 bit)
access : read-write

CSEL6 : Comparison 6 Selection
bits : 6 - 6 (1 bit)
access : read-write

CSEL7 : Comparison 7 Selection
bits : 7 - 7 (1 bit)
access : read-write


CMPM4

PWM Comparison 4 Mode Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPM4 CMPM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN CTR CPR CPRCNT CUPR CUPRCNT

CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write

CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write

CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write

CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write

CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write

CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write


CMPMUPD4

PWM Comparison 4 Mode Update Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMPMUPD4 CMPMUPD4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CENUPD CTRUPD CPRUPD CUPRUPD

CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only

CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only

CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only

CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only


IMR1

PWM Interrupt Mask Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR1 IMR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHID0 CHID1 CHID2 CHID3 CHID4 CHID5 CHID6 CHID7 FCHID0 FCHID1 FCHID2 FCHID3 FCHID4 FCHID5 FCHID6 FCHID7

CHID0 : Counter Event on Channel 0 Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

CHID1 : Counter Event on Channel 1 Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

CHID2 : Counter Event on Channel 2 Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

CHID3 : Counter Event on Channel 3 Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only

CHID4 : Counter Event on Channel 4 Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only

CHID5 : Counter Event on Channel 5 Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

CHID6 : Counter Event on Channel 6 Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only

CHID7 : Counter Event on Channel 7 Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only

FCHID0 : Fault Protection Trigger on Channel 0 Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only

FCHID1 : Fault Protection Trigger on Channel 1 Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only

FCHID2 : Fault Protection Trigger on Channel 2 Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only

FCHID3 : Fault Protection Trigger on Channel 3 Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only

FCHID4 : Fault Protection Trigger on Channel 4 Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only

FCHID5 : Fault Protection Trigger on Channel 5 Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only

FCHID6 : Fault Protection Trigger on Channel 6 Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only

FCHID7 : Fault Protection Trigger on Channel 7 Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only


CMPV5

PWM Comparison 5 Value Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPV5 CMPV5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CV CVM

CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write

CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write


CMPVUPD5

PWM Comparison 5 Value Update Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMPVUPD5 CMPVUPD5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CVUPD CVMUPD

CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only

CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only


CMPM5

PWM Comparison 5 Mode Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPM5 CMPM5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN CTR CPR CPRCNT CUPR CUPRCNT

CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write

CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write

CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write

CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write

CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write

CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write


CMPMUPD5

PWM Comparison 5 Mode Update Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMPMUPD5 CMPMUPD5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CENUPD CTRUPD CPRUPD CUPRUPD

CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only

CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only

CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only

CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only


CMPV6

PWM Comparison 6 Value Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPV6 CMPV6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CV CVM

CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write

CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write


CMPVUPD6

PWM Comparison 6 Value Update Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMPVUPD6 CMPVUPD6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CVUPD CVMUPD

CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only

CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only


CMPM6

PWM Comparison 6 Mode Register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPM6 CMPM6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN CTR CPR CPRCNT CUPR CUPRCNT

CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write

CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write

CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write

CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write

CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write

CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write


CMPMUPD6

PWM Comparison 6 Mode Update Register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMPMUPD6 CMPMUPD6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CENUPD CTRUPD CPRUPD CUPRUPD

CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only

CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only

CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only

CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only


CMPV7

PWM Comparison 7 Value Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPV7 CMPV7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CV CVM

CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write

CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write


CMPVUPD7

PWM Comparison 7 Value Update Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMPVUPD7 CMPVUPD7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CVUPD CVMUPD

CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only

CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only


CMPM7

PWM Comparison 7 Mode Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPM7 CMPM7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN CTR CPR CPRCNT CUPR CUPRCNT

CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write

CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write

CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write

CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write

CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write

CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write


CMPMUPD7

PWM Comparison 7 Mode Update Register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMPMUPD7 CMPMUPD7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CENUPD CTRUPD CPRUPD CUPRUPD

CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only

CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only

CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only

CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only


ISR1

PWM Interrupt Status Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR1 ISR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHID0 CHID1 CHID2 CHID3 CHID4 CHID5 CHID6 CHID7 FCHID0 FCHID1 FCHID2 FCHID3 FCHID4 FCHID5 FCHID6 FCHID7

CHID0 : Counter Event on Channel 0
bits : 0 - 0 (1 bit)
access : read-only

CHID1 : Counter Event on Channel 1
bits : 1 - 1 (1 bit)
access : read-only

CHID2 : Counter Event on Channel 2
bits : 2 - 2 (1 bit)
access : read-only

CHID3 : Counter Event on Channel 3
bits : 3 - 3 (1 bit)
access : read-only

CHID4 : Counter Event on Channel 4
bits : 4 - 4 (1 bit)
access : read-only

CHID5 : Counter Event on Channel 5
bits : 5 - 5 (1 bit)
access : read-only

CHID6 : Counter Event on Channel 6
bits : 6 - 6 (1 bit)
access : read-only

CHID7 : Counter Event on Channel 7
bits : 7 - 7 (1 bit)
access : read-only

FCHID0 : Fault Protection Trigger on Channel 0
bits : 16 - 16 (1 bit)
access : read-only

FCHID1 : Fault Protection Trigger on Channel 1
bits : 17 - 17 (1 bit)
access : read-only

FCHID2 : Fault Protection Trigger on Channel 2
bits : 18 - 18 (1 bit)
access : read-only

FCHID3 : Fault Protection Trigger on Channel 3
bits : 19 - 19 (1 bit)
access : read-only

FCHID4 : Fault Protection Trigger on Channel 4
bits : 20 - 20 (1 bit)
access : read-only

FCHID5 : Fault Protection Trigger on Channel 5
bits : 21 - 21 (1 bit)
access : read-only

FCHID6 : Fault Protection Trigger on Channel 6
bits : 22 - 22 (1 bit)
access : read-only

FCHID7 : Fault Protection Trigger on Channel 7
bits : 23 - 23 (1 bit)
access : read-only


SCM

PWM Sync Channels Mode Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCM SCM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNC0 SYNC1 SYNC2 SYNC3 SYNC4 SYNC5 SYNC6 SYNC7 UPDM PTRM PTRCS

SYNC0 : Synchronous Channel 0
bits : 0 - 0 (1 bit)
access : read-write

SYNC1 : Synchronous Channel 1
bits : 1 - 1 (1 bit)
access : read-write

SYNC2 : Synchronous Channel 2
bits : 2 - 2 (1 bit)
access : read-write

SYNC3 : Synchronous Channel 3
bits : 3 - 3 (1 bit)
access : read-write

SYNC4 : Synchronous Channel 4
bits : 4 - 4 (1 bit)
access : read-write

SYNC5 : Synchronous Channel 5
bits : 5 - 5 (1 bit)
access : read-write

SYNC6 : Synchronous Channel 6
bits : 6 - 6 (1 bit)
access : read-write

SYNC7 : Synchronous Channel 7
bits : 7 - 7 (1 bit)
access : read-write

UPDM : Synchronous Channels Update Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : MODE0

Manual write of double buffer registers and manual update of synchronous channels

0x1 : MODE1

Manual write of double buffer registers and automatic update of synchronous channels

0x2 : MODE2

Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels

End of enumeration elements list.

PTRM : PDC Transfer Request Mode
bits : 20 - 20 (1 bit)
access : read-write

PTRCS : PDC Transfer Request Comparison Selection
bits : 21 - 23 (3 bit)
access : read-write


CMR0

PWM Channel Mode Register (ch_num = 0)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR0 CMR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRE CALG CPOL CES DTE DTHI DTLI

CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x0 : MCK

Master clock

0x1 : MCK_DIV_2

Master clock/2

0x2 : MCK_DIV_4

Master clock/4

0x3 : MCK_DIV_8

Master clock/8

0x4 : MCK_DIV_16

Master clock/16

0x5 : MCK_DIV_32

Master clock/32

0x6 : MCK_DIV_64

Master clock/64

0x7 : MCK_DIV_128

Master clock/128

0x8 : MCK_DIV_256

Master clock/256

0x9 : MCK_DIV_512

Master clock/512

0xA : MCK_DIV_1024

Master clock/1024

0xB : CLKA

Clock A

0xC : CLKB

Clock B

End of enumeration elements list.

CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write

CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write

CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write

DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write

DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write

DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write


CDTY0

PWM Channel Duty Cycle Register (ch_num = 0)
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDTY0 CDTY0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTY

CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write


CDTYUPD0

PWM Channel Duty Cycle Update Register (ch_num = 0)
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CDTYUPD0 CDTYUPD0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTYUPD

CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only


CPRD0

PWM Channel Period Register (ch_num = 0)
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPRD0 CPRD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRD

CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write


CPRDUPD0

PWM Channel Period Update Register (ch_num = 0)
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CPRDUPD0 CPRDUPD0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRDUPD

CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only


CCNT0

PWM Channel Counter Register (ch_num = 0)
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CCNT0 CCNT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only


DT0

PWM Channel Dead Time Register (ch_num = 0)
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT0 DT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTH DTL

DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write

DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write


DTUPD0

PWM Channel Dead Time Update Register (ch_num = 0)
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DTUPD0 DTUPD0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTHUPD DTLUPD

DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only

DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only


CMR1

PWM Channel Mode Register (ch_num = 1)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR1 CMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRE CALG CPOL CES DTE DTHI DTLI

CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x0 : MCK

Master clock

0x1 : MCK_DIV_2

Master clock/2

0x2 : MCK_DIV_4

Master clock/4

0x3 : MCK_DIV_8

Master clock/8

0x4 : MCK_DIV_16

Master clock/16

0x5 : MCK_DIV_32

Master clock/32

0x6 : MCK_DIV_64

Master clock/64

0x7 : MCK_DIV_128

Master clock/128

0x8 : MCK_DIV_256

Master clock/256

0x9 : MCK_DIV_512

Master clock/512

0xA : MCK_DIV_1024

Master clock/1024

0xB : CLKA

Clock A

0xC : CLKB

Clock B

End of enumeration elements list.

CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write

CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write

CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write

DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write

DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write

DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write


CDTY1

PWM Channel Duty Cycle Register (ch_num = 1)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDTY1 CDTY1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTY

CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write


CDTYUPD1

PWM Channel Duty Cycle Update Register (ch_num = 1)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CDTYUPD1 CDTYUPD1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTYUPD

CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only


CPRD1

PWM Channel Period Register (ch_num = 1)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPRD1 CPRD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRD

CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write


CPRDUPD1

PWM Channel Period Update Register (ch_num = 1)
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CPRDUPD1 CPRDUPD1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRDUPD

CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only


CCNT1

PWM Channel Counter Register (ch_num = 1)
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CCNT1 CCNT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only


DT1

PWM Channel Dead Time Register (ch_num = 1)
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT1 DT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTH DTL

DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write

DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write


DTUPD1

PWM Channel Dead Time Update Register (ch_num = 1)
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DTUPD1 DTUPD1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTHUPD DTLUPD

DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only

DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only


CMR2

PWM Channel Mode Register (ch_num = 2)
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR2 CMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRE CALG CPOL CES DTE DTHI DTLI

CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x0 : MCK

Master clock

0x1 : MCK_DIV_2

Master clock/2

0x2 : MCK_DIV_4

Master clock/4

0x3 : MCK_DIV_8

Master clock/8

0x4 : MCK_DIV_16

Master clock/16

0x5 : MCK_DIV_32

Master clock/32

0x6 : MCK_DIV_64

Master clock/64

0x7 : MCK_DIV_128

Master clock/128

0x8 : MCK_DIV_256

Master clock/256

0x9 : MCK_DIV_512

Master clock/512

0xA : MCK_DIV_1024

Master clock/1024

0xB : CLKA

Clock A

0xC : CLKB

Clock B

End of enumeration elements list.

CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write

CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write

CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write

DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write

DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write

DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write


CDTY2

PWM Channel Duty Cycle Register (ch_num = 2)
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDTY2 CDTY2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTY

CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write


CDTYUPD2

PWM Channel Duty Cycle Update Register (ch_num = 2)
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CDTYUPD2 CDTYUPD2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTYUPD

CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only


CPRD2

PWM Channel Period Register (ch_num = 2)
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPRD2 CPRD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRD

CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write


CPRDUPD2

PWM Channel Period Update Register (ch_num = 2)
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CPRDUPD2 CPRDUPD2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRDUPD

CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only


CCNT2

PWM Channel Counter Register (ch_num = 2)
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CCNT2 CCNT2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only


DT2

PWM Channel Dead Time Register (ch_num = 2)
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT2 DT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTH DTL

DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write

DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write


DTUPD2

PWM Channel Dead Time Update Register (ch_num = 2)
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DTUPD2 DTUPD2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTHUPD DTLUPD

DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only

DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only


CMR3

PWM Channel Mode Register (ch_num = 3)
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR3 CMR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRE CALG CPOL CES DTE DTHI DTLI

CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x0 : MCK

Master clock

0x1 : MCK_DIV_2

Master clock/2

0x2 : MCK_DIV_4

Master clock/4

0x3 : MCK_DIV_8

Master clock/8

0x4 : MCK_DIV_16

Master clock/16

0x5 : MCK_DIV_32

Master clock/32

0x6 : MCK_DIV_64

Master clock/64

0x7 : MCK_DIV_128

Master clock/128

0x8 : MCK_DIV_256

Master clock/256

0x9 : MCK_DIV_512

Master clock/512

0xA : MCK_DIV_1024

Master clock/1024

0xB : CLKA

Clock A

0xC : CLKB

Clock B

End of enumeration elements list.

CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write

CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write

CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write

DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write

DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write

DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write


CDTY3

PWM Channel Duty Cycle Register (ch_num = 3)
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDTY3 CDTY3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTY

CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write


CDTYUPD3

PWM Channel Duty Cycle Update Register (ch_num = 3)
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CDTYUPD3 CDTYUPD3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTYUPD

CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only


CPRD3

PWM Channel Period Register (ch_num = 3)
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPRD3 CPRD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRD

CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write


CPRDUPD3

PWM Channel Period Update Register (ch_num = 3)
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CPRDUPD3 CPRDUPD3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRDUPD

CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only


CCNT3

PWM Channel Counter Register (ch_num = 3)
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CCNT3 CCNT3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only


DT3

PWM Channel Dead Time Register (ch_num = 3)
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT3 DT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTH DTL

DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write

DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write


DTUPD3

PWM Channel Dead Time Update Register (ch_num = 3)
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DTUPD3 DTUPD3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTHUPD DTLUPD

DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only

DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only


SCUC

PWM Sync Channels Update Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCUC SCUC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPDULOCK

UPDULOCK : Synchronous Channels Update Unlock
bits : 0 - 0 (1 bit)
access : read-write


CMR4

PWM Channel Mode Register (ch_num = 4)
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR4 CMR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRE CALG CPOL CES DTE DTHI DTLI

CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x0 : MCK

Master clock

0x1 : MCK_DIV_2

Master clock/2

0x2 : MCK_DIV_4

Master clock/4

0x3 : MCK_DIV_8

Master clock/8

0x4 : MCK_DIV_16

Master clock/16

0x5 : MCK_DIV_32

Master clock/32

0x6 : MCK_DIV_64

Master clock/64

0x7 : MCK_DIV_128

Master clock/128

0x8 : MCK_DIV_256

Master clock/256

0x9 : MCK_DIV_512

Master clock/512

0xA : MCK_DIV_1024

Master clock/1024

0xB : CLKA

Clock A

0xC : CLKB

Clock B

End of enumeration elements list.

CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write

CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write

CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write

DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write

DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write

DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write


CDTY4

PWM Channel Duty Cycle Register (ch_num = 4)
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDTY4 CDTY4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTY

CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write


CDTYUPD4

PWM Channel Duty Cycle Update Register (ch_num = 4)
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CDTYUPD4 CDTYUPD4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTYUPD

CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only


CPRD4

PWM Channel Period Register (ch_num = 4)
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPRD4 CPRD4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRD

CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write


CPRDUPD4

PWM Channel Period Update Register (ch_num = 4)
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CPRDUPD4 CPRDUPD4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRDUPD

CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only


CCNT4

PWM Channel Counter Register (ch_num = 4)
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CCNT4 CCNT4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only


DT4

PWM Channel Dead Time Register (ch_num = 4)
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT4 DT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTH DTL

DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write

DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write


DTUPD4

PWM Channel Dead Time Update Register (ch_num = 4)
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DTUPD4 DTUPD4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTHUPD DTLUPD

DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only

DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only


CMR5

PWM Channel Mode Register (ch_num = 5)
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR5 CMR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRE CALG CPOL CES DTE DTHI DTLI

CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x0 : MCK

Master clock

0x1 : MCK_DIV_2

Master clock/2

0x2 : MCK_DIV_4

Master clock/4

0x3 : MCK_DIV_8

Master clock/8

0x4 : MCK_DIV_16

Master clock/16

0x5 : MCK_DIV_32

Master clock/32

0x6 : MCK_DIV_64

Master clock/64

0x7 : MCK_DIV_128

Master clock/128

0x8 : MCK_DIV_256

Master clock/256

0x9 : MCK_DIV_512

Master clock/512

0xA : MCK_DIV_1024

Master clock/1024

0xB : CLKA

Clock A

0xC : CLKB

Clock B

End of enumeration elements list.

CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write

CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write

CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write

DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write

DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write

DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write


CDTY5

PWM Channel Duty Cycle Register (ch_num = 5)
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDTY5 CDTY5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTY

CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write


CDTYUPD5

PWM Channel Duty Cycle Update Register (ch_num = 5)
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CDTYUPD5 CDTYUPD5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTYUPD

CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only


CPRD5

PWM Channel Period Register (ch_num = 5)
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPRD5 CPRD5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRD

CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write


CPRDUPD5

PWM Channel Period Update Register (ch_num = 5)
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CPRDUPD5 CPRDUPD5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRDUPD

CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only


CCNT5

PWM Channel Counter Register (ch_num = 5)
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CCNT5 CCNT5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only


DT5

PWM Channel Dead Time Register (ch_num = 5)
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT5 DT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTH DTL

DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write

DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write


DTUPD5

PWM Channel Dead Time Update Register (ch_num = 5)
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DTUPD5 DTUPD5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTHUPD DTLUPD

DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only

DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only


SCUP

PWM Sync Channels Update Period Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCUP SCUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPR UPRCNT

UPR : Update Period
bits : 0 - 3 (4 bit)
access : read-write

UPRCNT : Update Period Counter
bits : 4 - 7 (4 bit)
access : read-write


CMR6

PWM Channel Mode Register (ch_num = 6)
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR6 CMR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRE CALG CPOL CES DTE DTHI DTLI

CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x0 : MCK

Master clock

0x1 : MCK_DIV_2

Master clock/2

0x2 : MCK_DIV_4

Master clock/4

0x3 : MCK_DIV_8

Master clock/8

0x4 : MCK_DIV_16

Master clock/16

0x5 : MCK_DIV_32

Master clock/32

0x6 : MCK_DIV_64

Master clock/64

0x7 : MCK_DIV_128

Master clock/128

0x8 : MCK_DIV_256

Master clock/256

0x9 : MCK_DIV_512

Master clock/512

0xA : MCK_DIV_1024

Master clock/1024

0xB : CLKA

Clock A

0xC : CLKB

Clock B

End of enumeration elements list.

CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write

CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write

CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write

DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write

DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write

DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write


CDTY6

PWM Channel Duty Cycle Register (ch_num = 6)
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDTY6 CDTY6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTY

CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write


CDTYUPD6

PWM Channel Duty Cycle Update Register (ch_num = 6)
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CDTYUPD6 CDTYUPD6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTYUPD

CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only


CPRD6

PWM Channel Period Register (ch_num = 6)
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPRD6 CPRD6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRD

CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write


CPRDUPD6

PWM Channel Period Update Register (ch_num = 6)
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CPRDUPD6 CPRDUPD6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRDUPD

CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only


CCNT6

PWM Channel Counter Register (ch_num = 6)
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CCNT6 CCNT6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only


DT6

PWM Channel Dead Time Register (ch_num = 6)
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT6 DT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTH DTL

DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write

DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write


DTUPD6

PWM Channel Dead Time Update Register (ch_num = 6)
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DTUPD6 DTUPD6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTHUPD DTLUPD

DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only

DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only


CMR7

PWM Channel Mode Register (ch_num = 7)
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR7 CMR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRE CALG CPOL CES DTE DTHI DTLI

CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x0 : MCK

Master clock

0x1 : MCK_DIV_2

Master clock/2

0x2 : MCK_DIV_4

Master clock/4

0x3 : MCK_DIV_8

Master clock/8

0x4 : MCK_DIV_16

Master clock/16

0x5 : MCK_DIV_32

Master clock/32

0x6 : MCK_DIV_64

Master clock/64

0x7 : MCK_DIV_128

Master clock/128

0x8 : MCK_DIV_256

Master clock/256

0x9 : MCK_DIV_512

Master clock/512

0xA : MCK_DIV_1024

Master clock/1024

0xB : CLKA

Clock A

0xC : CLKB

Clock B

End of enumeration elements list.

CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write

CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write

CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write

DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write

DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write

DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write


CDTY7

PWM Channel Duty Cycle Register (ch_num = 7)
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDTY7 CDTY7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTY

CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write


CDTYUPD7

PWM Channel Duty Cycle Update Register (ch_num = 7)
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CDTYUPD7 CDTYUPD7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTYUPD

CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only


CPRD7

PWM Channel Period Register (ch_num = 7)
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPRD7 CPRD7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRD

CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write


CPRDUPD7

PWM Channel Period Update Register (ch_num = 7)
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CPRDUPD7 CPRDUPD7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRDUPD

CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only


CCNT7

PWM Channel Counter Register (ch_num = 7)
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CCNT7 CCNT7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only


DT7

PWM Channel Dead Time Register (ch_num = 7)
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT7 DT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTH DTL

DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write

DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write


DTUPD7

PWM Channel Dead Time Update Register (ch_num = 7)
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DTUPD7 DTUPD7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTHUPD DTLUPD

DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only

DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only


SCUPUPD

PWM Sync Channels Update Period Update Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCUPUPD SCUPUPD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPRUPD

UPRUPD : Update Period Update
bits : 0 - 3 (4 bit)
access : write-only


IER2

PWM Interrupt Enable Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER2 IER2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRDY ENDTX TXBUFE UNRE CMPM0 CMPM1 CMPM2 CMPM3 CMPM4 CMPM5 CMPM6 CMPM7 CMPU0 CMPU1 CMPU2 CMPU3 CMPU4 CMPU5 CMPU6 CMPU7

WRDY : Write Ready for Synchronous Channels Update Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

ENDTX : PDC End of TX Buffer Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXBUFE : PDC TX Buffer Empty Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

UNRE : Synchronous Channels Update Underrun Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

CMPM0 : Comparison 0 Match Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

CMPM1 : Comparison 1 Match Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

CMPM2 : Comparison 2 Match Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

CMPM3 : Comparison 3 Match Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

CMPM4 : Comparison 4 Match Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

CMPM5 : Comparison 5 Match Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

CMPM6 : Comparison 6 Match Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

CMPM7 : Comparison 7 Match Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only

CMPU0 : Comparison 0 Update Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only

CMPU1 : Comparison 1 Update Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only

CMPU2 : Comparison 2 Update Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

CMPU3 : Comparison 3 Update Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only

CMPU4 : Comparison 4 Update Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only

CMPU5 : Comparison 5 Update Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only

CMPU6 : Comparison 6 Update Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only

CMPU7 : Comparison 7 Update Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only


IDR2

PWM Interrupt Disable Register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR2 IDR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRDY ENDTX TXBUFE UNRE CMPM0 CMPM1 CMPM2 CMPM3 CMPM4 CMPM5 CMPM6 CMPM7 CMPU0 CMPU1 CMPU2 CMPU3 CMPU4 CMPU5 CMPU6 CMPU7

WRDY : Write Ready for Synchronous Channels Update Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

ENDTX : PDC End of TX Buffer Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXBUFE : PDC TX Buffer Empty Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

UNRE : Synchronous Channels Update Underrun Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

CMPM0 : Comparison 0 Match Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

CMPM1 : Comparison 1 Match Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

CMPM2 : Comparison 2 Match Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

CMPM3 : Comparison 3 Match Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

CMPM4 : Comparison 4 Match Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

CMPM5 : Comparison 5 Match Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

CMPM6 : Comparison 6 Match Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

CMPM7 : Comparison 7 Match Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only

CMPU0 : Comparison 0 Update Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only

CMPU1 : Comparison 1 Update Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only

CMPU2 : Comparison 2 Update Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

CMPU3 : Comparison 3 Update Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only

CMPU4 : Comparison 4 Update Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only

CMPU5 : Comparison 5 Update Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only

CMPU6 : Comparison 6 Update Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only

CMPU7 : Comparison 7 Update Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only


IMR2

PWM Interrupt Mask Register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR2 IMR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRDY ENDTX TXBUFE UNRE CMPM0 CMPM1 CMPM2 CMPM3 CMPM4 CMPM5 CMPM6 CMPM7 CMPU0 CMPU1 CMPU2 CMPU3 CMPU4 CMPU5 CMPU6 CMPU7

WRDY : Write Ready for Synchronous Channels Update Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

ENDTX : PDC End of TX Buffer Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

TXBUFE : PDC TX Buffer Empty Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

UNRE : Synchronous Channels Update Underrun Error Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only

CMPM0 : Comparison 0 Match Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only

CMPM1 : Comparison 1 Match Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only

CMPM2 : Comparison 2 Match Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only

CMPM3 : Comparison 3 Match Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only

CMPM4 : Comparison 4 Match Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only

CMPM5 : Comparison 5 Match Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only

CMPM6 : Comparison 6 Match Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only

CMPM7 : Comparison 7 Match Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only

CMPU0 : Comparison 0 Update Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only

CMPU1 : Comparison 1 Update Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only

CMPU2 : Comparison 2 Update Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only

CMPU3 : Comparison 3 Update Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only

CMPU4 : Comparison 4 Update Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only

CMPU5 : Comparison 5 Update Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only

CMPU6 : Comparison 6 Update Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only

CMPU7 : Comparison 7 Update Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only


ENA

PWM Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ENA ENA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHID0 CHID1 CHID2 CHID3 CHID4 CHID5 CHID6 CHID7

CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : write-only

CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : write-only

CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : write-only

CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : write-only

CHID4 : Channel ID
bits : 4 - 4 (1 bit)
access : write-only

CHID5 : Channel ID
bits : 5 - 5 (1 bit)
access : write-only

CHID6 : Channel ID
bits : 6 - 6 (1 bit)
access : write-only

CHID7 : Channel ID
bits : 7 - 7 (1 bit)
access : write-only


ISR2

PWM Interrupt Status Register 2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR2 ISR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRDY ENDTX TXBUFE UNRE CMPM0 CMPM1 CMPM2 CMPM3 CMPM4 CMPM5 CMPM6 CMPM7 CMPU0 CMPU1 CMPU2 CMPU3 CMPU4 CMPU5 CMPU6 CMPU7

WRDY : Write Ready for Synchronous Channels Update
bits : 0 - 0 (1 bit)
access : read-only

ENDTX : PDC End of TX Buffer
bits : 1 - 1 (1 bit)
access : read-only

TXBUFE : PDC TX Buffer Empty
bits : 2 - 2 (1 bit)
access : read-only

UNRE : Synchronous Channels Update Underrun Error
bits : 3 - 3 (1 bit)
access : read-only

CMPM0 : Comparison 0 Match
bits : 8 - 8 (1 bit)
access : read-only

CMPM1 : Comparison 1 Match
bits : 9 - 9 (1 bit)
access : read-only

CMPM2 : Comparison 2 Match
bits : 10 - 10 (1 bit)
access : read-only

CMPM3 : Comparison 3 Match
bits : 11 - 11 (1 bit)
access : read-only

CMPM4 : Comparison 4 Match
bits : 12 - 12 (1 bit)
access : read-only

CMPM5 : Comparison 5 Match
bits : 13 - 13 (1 bit)
access : read-only

CMPM6 : Comparison 6 Match
bits : 14 - 14 (1 bit)
access : read-only

CMPM7 : Comparison 7 Match
bits : 15 - 15 (1 bit)
access : read-only

CMPU0 : Comparison 0 Update
bits : 16 - 16 (1 bit)
access : read-only

CMPU1 : Comparison 1 Update
bits : 17 - 17 (1 bit)
access : read-only

CMPU2 : Comparison 2 Update
bits : 18 - 18 (1 bit)
access : read-only

CMPU3 : Comparison 3 Update
bits : 19 - 19 (1 bit)
access : read-only

CMPU4 : Comparison 4 Update
bits : 20 - 20 (1 bit)
access : read-only

CMPU5 : Comparison 5 Update
bits : 21 - 21 (1 bit)
access : read-only

CMPU6 : Comparison 6 Update
bits : 22 - 22 (1 bit)
access : read-only

CMPU7 : Comparison 7 Update
bits : 23 - 23 (1 bit)
access : read-only


OOV

PWM Output Override Value Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OOV OOV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OOVH0 OOVH1 OOVH2 OOVH3 OOVH4 OOVH5 OOVH6 OOVH7 OOVL0 OOVL1 OOVL2 OOVL3 OOVL4 OOVL5 OOVL6 OOVL7

OOVH0 : Output Override Value for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : read-write

OOVH1 : Output Override Value for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : read-write

OOVH2 : Output Override Value for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : read-write

OOVH3 : Output Override Value for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : read-write

OOVH4 : Output Override Value for PWMH output of the channel 4
bits : 4 - 4 (1 bit)
access : read-write

OOVH5 : Output Override Value for PWMH output of the channel 5
bits : 5 - 5 (1 bit)
access : read-write

OOVH6 : Output Override Value for PWMH output of the channel 6
bits : 6 - 6 (1 bit)
access : read-write

OOVH7 : Output Override Value for PWMH output of the channel 7
bits : 7 - 7 (1 bit)
access : read-write

OOVL0 : Output Override Value for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : read-write

OOVL1 : Output Override Value for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : read-write

OOVL2 : Output Override Value for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : read-write

OOVL3 : Output Override Value for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : read-write

OOVL4 : Output Override Value for PWML output of the channel 4
bits : 20 - 20 (1 bit)
access : read-write

OOVL5 : Output Override Value for PWML output of the channel 5
bits : 21 - 21 (1 bit)
access : read-write

OOVL6 : Output Override Value for PWML output of the channel 6
bits : 22 - 22 (1 bit)
access : read-write

OOVL7 : Output Override Value for PWML output of the channel 7
bits : 23 - 23 (1 bit)
access : read-write


OS

PWM Output Selection Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OS OS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSH0 OSH1 OSH2 OSH3 OSH4 OSH5 OSH6 OSH7 OSL0 OSL1 OSL2 OSL3 OSL4 OSL5 OSL6 OSL7

OSH0 : Output Selection for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : read-write

OSH1 : Output Selection for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : read-write

OSH2 : Output Selection for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : read-write

OSH3 : Output Selection for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : read-write

OSH4 : Output Selection for PWMH output of the channel 4
bits : 4 - 4 (1 bit)
access : read-write

OSH5 : Output Selection for PWMH output of the channel 5
bits : 5 - 5 (1 bit)
access : read-write

OSH6 : Output Selection for PWMH output of the channel 6
bits : 6 - 6 (1 bit)
access : read-write

OSH7 : Output Selection for PWMH output of the channel 7
bits : 7 - 7 (1 bit)
access : read-write

OSL0 : Output Selection for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : read-write

OSL1 : Output Selection for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : read-write

OSL2 : Output Selection for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : read-write

OSL3 : Output Selection for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : read-write

OSL4 : Output Selection for PWML output of the channel 4
bits : 20 - 20 (1 bit)
access : read-write

OSL5 : Output Selection for PWML output of the channel 5
bits : 21 - 21 (1 bit)
access : read-write

OSL6 : Output Selection for PWML output of the channel 6
bits : 22 - 22 (1 bit)
access : read-write

OSL7 : Output Selection for PWML output of the channel 7
bits : 23 - 23 (1 bit)
access : read-write


OSS

PWM Output Selection Set Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OSS OSS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSSH0 OSSH1 OSSH2 OSSH3 OSSH4 OSSH5 OSSH6 OSSH7 OSSL0 OSSL1 OSSL2 OSSL3 OSSL4 OSSL5 OSSL6 OSSL7

OSSH0 : Output Selection Set for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : write-only

OSSH1 : Output Selection Set for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : write-only

OSSH2 : Output Selection Set for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : write-only

OSSH3 : Output Selection Set for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : write-only

OSSH4 : Output Selection Set for PWMH output of the channel 4
bits : 4 - 4 (1 bit)
access : write-only

OSSH5 : Output Selection Set for PWMH output of the channel 5
bits : 5 - 5 (1 bit)
access : write-only

OSSH6 : Output Selection Set for PWMH output of the channel 6
bits : 6 - 6 (1 bit)
access : write-only

OSSH7 : Output Selection Set for PWMH output of the channel 7
bits : 7 - 7 (1 bit)
access : write-only

OSSL0 : Output Selection Set for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : write-only

OSSL1 : Output Selection Set for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : write-only

OSSL2 : Output Selection Set for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : write-only

OSSL3 : Output Selection Set for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : write-only

OSSL4 : Output Selection Set for PWML output of the channel 4
bits : 20 - 20 (1 bit)
access : write-only

OSSL5 : Output Selection Set for PWML output of the channel 5
bits : 21 - 21 (1 bit)
access : write-only

OSSL6 : Output Selection Set for PWML output of the channel 6
bits : 22 - 22 (1 bit)
access : write-only

OSSL7 : Output Selection Set for PWML output of the channel 7
bits : 23 - 23 (1 bit)
access : write-only


OSC

PWM Output Selection Clear Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OSC OSC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSCH0 OSCH1 OSCH2 OSCH3 OSCH4 OSCH5 OSCH6 OSCH7 OSCL0 OSCL1 OSCL2 OSCL3 OSCL4 OSCL5 OSCL6 OSCL7

OSCH0 : Output Selection Clear for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : write-only

OSCH1 : Output Selection Clear for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : write-only

OSCH2 : Output Selection Clear for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : write-only

OSCH3 : Output Selection Clear for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : write-only

OSCH4 : Output Selection Clear for PWMH output of the channel 4
bits : 4 - 4 (1 bit)
access : write-only

OSCH5 : Output Selection Clear for PWMH output of the channel 5
bits : 5 - 5 (1 bit)
access : write-only

OSCH6 : Output Selection Clear for PWMH output of the channel 6
bits : 6 - 6 (1 bit)
access : write-only

OSCH7 : Output Selection Clear for PWMH output of the channel 7
bits : 7 - 7 (1 bit)
access : write-only

OSCL0 : Output Selection Clear for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : write-only

OSCL1 : Output Selection Clear for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : write-only

OSCL2 : Output Selection Clear for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : write-only

OSCL3 : Output Selection Clear for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : write-only

OSCL4 : Output Selection Clear for PWML output of the channel 4
bits : 20 - 20 (1 bit)
access : write-only

OSCL5 : Output Selection Clear for PWML output of the channel 5
bits : 21 - 21 (1 bit)
access : write-only

OSCL6 : Output Selection Clear for PWML output of the channel 6
bits : 22 - 22 (1 bit)
access : write-only

OSCL7 : Output Selection Clear for PWML output of the channel 7
bits : 23 - 23 (1 bit)
access : write-only


OSSUPD

PWM Output Selection Set Update Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OSSUPD OSSUPD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSSUPH0 OSSUPH1 OSSUPH2 OSSUPH3 OSSUPH4 OSSUPH5 OSSUPH6 OSSUPH7 OSSUPL0 OSSUPL1 OSSUPL2 OSSUPL3 OSSUPL4 OSSUPL5 OSSUPL6 OSSUPL7

OSSUPH0 : Output Selection Set for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : write-only

OSSUPH1 : Output Selection Set for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : write-only

OSSUPH2 : Output Selection Set for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : write-only

OSSUPH3 : Output Selection Set for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : write-only

OSSUPH4 : Output Selection Set for PWMH output of the channel 4
bits : 4 - 4 (1 bit)
access : write-only

OSSUPH5 : Output Selection Set for PWMH output of the channel 5
bits : 5 - 5 (1 bit)
access : write-only

OSSUPH6 : Output Selection Set for PWMH output of the channel 6
bits : 6 - 6 (1 bit)
access : write-only

OSSUPH7 : Output Selection Set for PWMH output of the channel 7
bits : 7 - 7 (1 bit)
access : write-only

OSSUPL0 : Output Selection Set for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : write-only

OSSUPL1 : Output Selection Set for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : write-only

OSSUPL2 : Output Selection Set for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : write-only

OSSUPL3 : Output Selection Set for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : write-only

OSSUPL4 : Output Selection Set for PWML output of the channel 4
bits : 20 - 20 (1 bit)
access : write-only

OSSUPL5 : Output Selection Set for PWML output of the channel 5
bits : 21 - 21 (1 bit)
access : write-only

OSSUPL6 : Output Selection Set for PWML output of the channel 6
bits : 22 - 22 (1 bit)
access : write-only

OSSUPL7 : Output Selection Set for PWML output of the channel 7
bits : 23 - 23 (1 bit)
access : write-only


OSCUPD

PWM Output Selection Clear Update Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OSCUPD OSCUPD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSCUPH0 OSCUPH1 OSCUPH2 OSCUPH3 OSCUPH4 OSCUPH5 OSCUPH6 OSCUPH7 OSCUPL0 OSCUPL1 OSCUPL2 OSCUPL3 OSCUPL4 OSCUPL5 OSCUPL6 OSCUPL7

OSCUPH0 : Output Selection Clear for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : write-only

OSCUPH1 : Output Selection Clear for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : write-only

OSCUPH2 : Output Selection Clear for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : write-only

OSCUPH3 : Output Selection Clear for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : write-only

OSCUPH4 : Output Selection Clear for PWMH output of the channel 4
bits : 4 - 4 (1 bit)
access : write-only

OSCUPH5 : Output Selection Clear for PWMH output of the channel 5
bits : 5 - 5 (1 bit)
access : write-only

OSCUPH6 : Output Selection Clear for PWMH output of the channel 6
bits : 6 - 6 (1 bit)
access : write-only

OSCUPH7 : Output Selection Clear for PWMH output of the channel 7
bits : 7 - 7 (1 bit)
access : write-only

OSCUPL0 : Output Selection Clear for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : write-only

OSCUPL1 : Output Selection Clear for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : write-only

OSCUPL2 : Output Selection Clear for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : write-only

OSCUPL3 : Output Selection Clear for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : write-only

OSCUPL4 : Output Selection Clear for PWML output of the channel 4
bits : 20 - 20 (1 bit)
access : write-only

OSCUPL5 : Output Selection Clear for PWML output of the channel 5
bits : 21 - 21 (1 bit)
access : write-only

OSCUPL6 : Output Selection Clear for PWML output of the channel 6
bits : 22 - 22 (1 bit)
access : write-only

OSCUPL7 : Output Selection Clear for PWML output of the channel 7
bits : 23 - 23 (1 bit)
access : write-only


FMR

PWM Fault Mode Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMR FMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPOL FMOD FFIL

FPOL : Fault Polarity (fault input bit varies from 0 to 5)
bits : 0 - 7 (8 bit)
access : read-write

FMOD : Fault Activation Mode (fault input bit varies from 0 to 5)
bits : 8 - 15 (8 bit)
access : read-write

FFIL : Fault Filtering (fault input bit varies from 0 to 5)
bits : 16 - 23 (8 bit)
access : read-write


FSR

PWM Fault Status Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FSR FSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIV FS

FIV : Fault Input Value (fault input bit varies from 0 to 5)
bits : 0 - 7 (8 bit)
access : read-only

FS : Fault Status (fault input bit varies from 0 to 5)
bits : 8 - 15 (8 bit)
access : read-only


FCR

PWM Fault Clear Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FCR FCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCLR

FCLR : Fault Clear (fault input bit varies from 0 to 5)
bits : 0 - 7 (8 bit)
access : write-only


FPV

PWM Fault Protection Value Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPV FPV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPVH0 FPVH1 FPVH2 FPVH3 FPVH4 FPVH5 FPVH6 FPVH7 FPVL0 FPVL1 FPVL2 FPVL3 FPVL4 FPVL5 FPVL6 FPVL7

FPVH0 : Fault Protection Value for PWMH output on channel 0
bits : 0 - 0 (1 bit)
access : read-write

FPVH1 : Fault Protection Value for PWMH output on channel 1
bits : 1 - 1 (1 bit)
access : read-write

FPVH2 : Fault Protection Value for PWMH output on channel 2
bits : 2 - 2 (1 bit)
access : read-write

FPVH3 : Fault Protection Value for PWMH output on channel 3
bits : 3 - 3 (1 bit)
access : read-write

FPVH4 : Fault Protection Value for PWMH output on channel 4
bits : 4 - 4 (1 bit)
access : read-write

FPVH5 : Fault Protection Value for PWMH output on channel 5
bits : 5 - 5 (1 bit)
access : read-write

FPVH6 : Fault Protection Value for PWMH output on channel 6
bits : 6 - 6 (1 bit)
access : read-write

FPVH7 : Fault Protection Value for PWMH output on channel 7
bits : 7 - 7 (1 bit)
access : read-write

FPVL0 : Fault Protection Value for PWML output on channel 0
bits : 16 - 16 (1 bit)
access : read-write

FPVL1 : Fault Protection Value for PWML output on channel 1
bits : 17 - 17 (1 bit)
access : read-write

FPVL2 : Fault Protection Value for PWML output on channel 2
bits : 18 - 18 (1 bit)
access : read-write

FPVL3 : Fault Protection Value for PWML output on channel 3
bits : 19 - 19 (1 bit)
access : read-write

FPVL4 : Fault Protection Value for PWML output on channel 4
bits : 20 - 20 (1 bit)
access : read-write

FPVL5 : Fault Protection Value for PWML output on channel 5
bits : 21 - 21 (1 bit)
access : read-write

FPVL6 : Fault Protection Value for PWML output on channel 6
bits : 22 - 22 (1 bit)
access : read-write

FPVL7 : Fault Protection Value for PWML output on channel 7
bits : 23 - 23 (1 bit)
access : read-write


FPE1

PWM Fault Protection Enable Register 1
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPE1 FPE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPE0 FPE1 FPE2 FPE3

FPE0 : Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5)
bits : 0 - 7 (8 bit)
access : read-write

FPE1 : Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5)
bits : 8 - 15 (8 bit)
access : read-write

FPE2 : Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5)
bits : 16 - 23 (8 bit)
access : read-write

FPE3 : Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5)
bits : 24 - 31 (8 bit)
access : read-write


FPE2

PWM Fault Protection Enable Register 2
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPE2 FPE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPE4 FPE5 FPE6 FPE7

FPE4 : Fault Protection Enable for channel 4 (fault input bit varies from 0 to 5)
bits : 0 - 7 (8 bit)
access : read-write

FPE5 : Fault Protection Enable for channel 5 (fault input bit varies from 0 to 5)
bits : 8 - 15 (8 bit)
access : read-write

FPE6 : Fault Protection Enable for channel 6 (fault input bit varies from 0 to 5)
bits : 16 - 23 (8 bit)
access : read-write

FPE7 : Fault Protection Enable for channel 7 (fault input bit varies from 0 to 5)
bits : 24 - 31 (8 bit)
access : read-write


ELMR0

PWM Event Line 0 Mode Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

ELMR0 ELMR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSEL0 CSEL1 CSEL2 CSEL3 CSEL4 CSEL5 CSEL6 CSEL7

CSEL0 : Comparison 0 Selection
bits : 0 - 0 (1 bit)
access : read-write

CSEL1 : Comparison 1 Selection
bits : 1 - 1 (1 bit)
access : read-write

CSEL2 : Comparison 2 Selection
bits : 2 - 2 (1 bit)
access : read-write

CSEL3 : Comparison 3 Selection
bits : 3 - 3 (1 bit)
access : read-write

CSEL4 : Comparison 4 Selection
bits : 4 - 4 (1 bit)
access : read-write

CSEL5 : Comparison 5 Selection
bits : 5 - 5 (1 bit)
access : read-write

CSEL6 : Comparison 6 Selection
bits : 6 - 6 (1 bit)
access : read-write

CSEL7 : Comparison 7 Selection
bits : 7 - 7 (1 bit)
access : read-write


DIS

PWM Disable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIS DIS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHID0 CHID1 CHID2 CHID3 CHID4 CHID5 CHID6 CHID7

CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : write-only

CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : write-only

CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : write-only

CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : write-only

CHID4 : Channel ID
bits : 4 - 4 (1 bit)
access : write-only

CHID5 : Channel ID
bits : 5 - 5 (1 bit)
access : write-only

CHID6 : Channel ID
bits : 6 - 6 (1 bit)
access : write-only

CHID7 : Channel ID
bits : 7 - 7 (1 bit)
access : write-only


ELMR1

PWM Event Line 0 Mode Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

ELMR1 ELMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSEL0 CSEL1 CSEL2 CSEL3 CSEL4 CSEL5 CSEL6 CSEL7

CSEL0 : Comparison 0 Selection
bits : 0 - 0 (1 bit)
access : read-write

CSEL1 : Comparison 1 Selection
bits : 1 - 1 (1 bit)
access : read-write

CSEL2 : Comparison 2 Selection
bits : 2 - 2 (1 bit)
access : read-write

CSEL3 : Comparison 3 Selection
bits : 3 - 3 (1 bit)
access : read-write

CSEL4 : Comparison 4 Selection
bits : 4 - 4 (1 bit)
access : read-write

CSEL5 : Comparison 5 Selection
bits : 5 - 5 (1 bit)
access : read-write

CSEL6 : Comparison 6 Selection
bits : 6 - 6 (1 bit)
access : read-write

CSEL7 : Comparison 7 Selection
bits : 7 - 7 (1 bit)
access : read-write


SMMR

PWM Stepper Motor Mode Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMMR SMMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GCEN0 GCEN1 GCEN2 GCEN3 DOWN0 DOWN1 DOWN2 DOWN3

GCEN0 : Gray Count ENable
bits : 0 - 0 (1 bit)
access : read-write

GCEN1 : Gray Count ENable
bits : 1 - 1 (1 bit)
access : read-write

GCEN2 : Gray Count ENable
bits : 2 - 2 (1 bit)
access : read-write

GCEN3 : Gray Count ENable
bits : 3 - 3 (1 bit)
access : read-write

DOWN0 : DOWN Count
bits : 16 - 16 (1 bit)
access : read-write

DOWN1 : DOWN Count
bits : 17 - 17 (1 bit)
access : read-write

DOWN2 : DOWN Count
bits : 18 - 18 (1 bit)
access : read-write

DOWN3 : DOWN Count
bits : 19 - 19 (1 bit)
access : read-write


SR

PWM Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHID0 CHID1 CHID2 CHID3 CHID4 CHID5 CHID6 CHID7

CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : read-only

CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : read-only

CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : read-only

CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : read-only

CHID4 : Channel ID
bits : 4 - 4 (1 bit)
access : read-only

CHID5 : Channel ID
bits : 5 - 5 (1 bit)
access : read-only

CHID6 : Channel ID
bits : 6 - 6 (1 bit)
access : read-only

CHID7 : Channel ID
bits : 7 - 7 (1 bit)
access : read-only


WPCR

PWM Write Protect Control Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

WPCR WPCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPCMD WPRG0 WPRG1 WPRG2 WPRG3 WPRG4 WPRG5 WPKEY

WPCMD : Write Protect Command
bits : 0 - 1 (2 bit)
access : write-only

WPRG0 : Write Protect Register Group 0
bits : 2 - 2 (1 bit)
access : write-only

WPRG1 : Write Protect Register Group 1
bits : 3 - 3 (1 bit)
access : write-only

WPRG2 : Write Protect Register Group 2
bits : 4 - 4 (1 bit)
access : write-only

WPRG3 : Write Protect Register Group 3
bits : 5 - 5 (1 bit)
access : write-only

WPRG4 : Write Protect Register Group 4
bits : 6 - 6 (1 bit)
access : write-only

WPRG5 : Write Protect Register Group 5
bits : 7 - 7 (1 bit)
access : write-only

WPKEY : Write Protect Key
bits : 8 - 31 (24 bit)
access : write-only


WPSR

PWM Write Protect Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPSWS0 WPSWS1 WPSWS2 WPSWS3 WPSWS4 WPSWS5 WPVS WPHWS0 WPHWS1 WPHWS2 WPHWS3 WPHWS4 WPHWS5 WPVSRC

WPSWS0 : Write Protect SW Status
bits : 0 - 0 (1 bit)
access : read-only

WPSWS1 : Write Protect SW Status
bits : 1 - 1 (1 bit)
access : read-only

WPSWS2 : Write Protect SW Status
bits : 2 - 2 (1 bit)
access : read-only

WPSWS3 : Write Protect SW Status
bits : 3 - 3 (1 bit)
access : read-only

WPSWS4 : Write Protect SW Status
bits : 4 - 4 (1 bit)
access : read-only

WPSWS5 : Write Protect SW Status
bits : 5 - 5 (1 bit)
access : read-only

WPVS : Write Protect Violation Status
bits : 7 - 7 (1 bit)
access : read-only

WPHWS0 : Write Protect HW Status
bits : 8 - 8 (1 bit)
access : read-only

WPHWS1 : Write Protect HW Status
bits : 9 - 9 (1 bit)
access : read-only

WPHWS2 : Write Protect HW Status
bits : 10 - 10 (1 bit)
access : read-only

WPHWS3 : Write Protect HW Status
bits : 11 - 11 (1 bit)
access : read-only

WPHWS4 : Write Protect HW Status
bits : 12 - 12 (1 bit)
access : read-only

WPHWS5 : Write Protect HW Status
bits : 13 - 13 (1 bit)
access : read-only

WPVSRC : Write Protect Violation Source
bits : 16 - 31 (16 bit)
access : read-only


ELMR[0]

PWM Event Line 0 Mode Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ELMR[0] ELMR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSEL0 CSEL1 CSEL2 CSEL3 CSEL4 CSEL5 CSEL6 CSEL7

CSEL0 : Comparison 0 Selection
bits : 0 - 0 (1 bit)
access : read-write

CSEL1 : Comparison 1 Selection
bits : 1 - 1 (1 bit)
access : read-write

CSEL2 : Comparison 2 Selection
bits : 2 - 2 (1 bit)
access : read-write

CSEL3 : Comparison 3 Selection
bits : 3 - 3 (1 bit)
access : read-write

CSEL4 : Comparison 4 Selection
bits : 4 - 4 (1 bit)
access : read-write

CSEL5 : Comparison 5 Selection
bits : 5 - 5 (1 bit)
access : read-write

CSEL6 : Comparison 6 Selection
bits : 6 - 6 (1 bit)
access : read-write

CSEL7 : Comparison 7 Selection
bits : 7 - 7 (1 bit)
access : read-write



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