\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
DMA Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCPRSSETEN : Synchronization PRS Set Enable
bits : 0 - 7 (8 bit)
access : read-write
SYNCPRSCLREN : Synchronization PRS Clear Enable
bits : 8 - 15 (8 bit)
access : read-write
NUMFIXED : Number of Fixed Priority Channels
bits : 24 - 26 (3 bit)
access : read-write
Channel Peripheral Request Select Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write
SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRS
Peripheral Reflex System
0x00000008 : ADC0
Analog to Digital Converter 0
0x0000000A : VDAC0
Digital to Analog Converter 0
0x0000000C : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x0000000D : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000000E : USART2
Universal Synchronous/Asynchronous Receiver/Transmitter 2
0x0000000F : USART3
Universal Synchronous/Asynchronous Receiver/Transmitter 3
0x00000012 : UART0
Universal Asynchronous Receiver/Transmitter 0
0x00000014 : LEUART0
Low Energy UART 0
0x00000016 : I2C0
I2C 0
0x00000017 : I2C1
I2C 1
0x00000019 : TIMER0
Timer 0
0x0000001A : TIMER1
Timer 1
0x00000020 : WTIMER0
Wide Timer 0
0x00000021 : WTIMER1
Wide Timer 1
0x00000030 : MSC
Memory System Controller
0x00000031 : CRYPTO0
Advanced Encryption Standard Accelerator
0x0000003D : CSEN
Capacitive touch sense module
0x0000003E : LESENSE
Low Energy Sensor Interface
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
One arbitration slot selected
0x00000001 : TWO
Two arbitration slots selected
0x00000002 : FOUR
Four arbitration slots selected
0x00000003 : EIGHT
Eight arbitration slots selected
End of enumeration elements list.
SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write
DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write
Channel Loop Counter Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write
Channel Descriptor Control Word Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0x00000000 : TRANSFER
DMA transfer structure type selected.
0x00000001 : SYNCHRONIZE
Synchronization structure type selected.
0x00000002 : WRITE
Write immediate value structure type selected.
End of enumeration elements list.
STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : write-only
XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write
BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write
BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x00000000 : UNIT1
One unit transfer per arbitration
0x00000001 : UNIT2
Two unit transfers per arbitration
0x00000002 : UNIT3
Three unit transfers per arbitration
0x00000003 : UNIT4
Four unit transfers per arbitration
0x00000004 : UNIT6
Six unit transfers per arbitration
0x00000005 : UNIT8
Eight unit transfers per arbitration
0x00000007 : UNIT16
Sixteen unit transfers per arbitration
0x00000009 : UNIT32
32 unit transfers per arbitration
0x0000000A : UNIT64
64 unit transfers per arbitration
0x0000000B : UNIT128
128 unit transfers per arbitration
0x0000000C : UNIT256
256 unit transfers per arbitration
0x0000000D : UNIT512
512 unit transfers per arbitration
0x0000000E : UNIT1024
1024 unit transfers per arbitration
0x0000000F : ALL
Transfer all units as specified by the XFRCNT field
End of enumeration elements list.
DONEIFSEN : DMA Operation Done Interrupt Flag Set Enable
bits : 20 - 20 (1 bit)
access : read-write
REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write
DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write
IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write
SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Increment source address by one unit data size after each read
0x00000001 : TWO
Increment source address by two unit data sizes after each read
0x00000002 : FOUR
Increment source address by four unit data sizes after each read
0x00000003 : NONE
Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
End of enumeration elements list.
SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x00000000 : BYTE
Each unit transfer is a byte
0x00000001 : HALFWORD
Each unit transfer is a half-word
0x00000002 : WORD
Each unit transfer is a word
End of enumeration elements list.
DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Increment destination address by one unit data size after each write
0x00000001 : TWO
Increment destination address by two unit data sizes after each write
0x00000002 : FOUR
Increment destination address by four unit data sizes after each write
0x00000003 : NONE
Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.
End of enumeration elements list.
SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only
DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only
Channel Descriptor Source Data Address Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Descriptor Destination Data Address Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Descriptor Link Structure Address Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only
LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write
LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Peripheral Request Select Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write
SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRS
Peripheral Reflex System
0x00000008 : ADC0
Analog to Digital Converter 0
0x0000000A : VDAC0
Digital to Analog Converter 0
0x0000000C : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x0000000D : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000000E : USART2
Universal Synchronous/Asynchronous Receiver/Transmitter 2
0x0000000F : USART3
Universal Synchronous/Asynchronous Receiver/Transmitter 3
0x00000012 : UART0
Universal Asynchronous Receiver/Transmitter 0
0x00000014 : LEUART0
Low Energy UART 0
0x00000016 : I2C0
I2C 0
0x00000017 : I2C1
I2C 1
0x00000019 : TIMER0
Timer 0
0x0000001A : TIMER1
Timer 1
0x00000020 : WTIMER0
Wide Timer 0
0x00000021 : WTIMER1
Wide Timer 1
0x00000030 : MSC
Memory System Controller
0x00000031 : CRYPTO0
Advanced Encryption Standard Accelerator
0x0000003D : CSEN
Capacitive touch sense module
0x0000003E : LESENSE
Low Energy Sensor Interface
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
One arbitration slot selected
0x00000001 : TWO
Two arbitration slots selected
0x00000002 : FOUR
Four arbitration slots selected
0x00000003 : EIGHT
Eight arbitration slots selected
End of enumeration elements list.
SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write
DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write
Channel Loop Counter Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write
Channel Descriptor Control Word Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0x00000000 : TRANSFER
DMA transfer structure type selected.
0x00000001 : SYNCHRONIZE
Synchronization structure type selected.
0x00000002 : WRITE
Write immediate value structure type selected.
End of enumeration elements list.
STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : write-only
XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write
BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write
BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x00000000 : UNIT1
One unit transfer per arbitration
0x00000001 : UNIT2
Two unit transfers per arbitration
0x00000002 : UNIT3
Three unit transfers per arbitration
0x00000003 : UNIT4
Four unit transfers per arbitration
0x00000004 : UNIT6
Six unit transfers per arbitration
0x00000005 : UNIT8
Eight unit transfers per arbitration
0x00000007 : UNIT16
Sixteen unit transfers per arbitration
0x00000009 : UNIT32
32 unit transfers per arbitration
0x0000000A : UNIT64
64 unit transfers per arbitration
0x0000000B : UNIT128
128 unit transfers per arbitration
0x0000000C : UNIT256
256 unit transfers per arbitration
0x0000000D : UNIT512
512 unit transfers per arbitration
0x0000000E : UNIT1024
1024 unit transfers per arbitration
0x0000000F : ALL
Transfer all units as specified by the XFRCNT field
End of enumeration elements list.
DONEIFSEN : DMA Operation Done Interrupt Flag Set Enable
bits : 20 - 20 (1 bit)
access : read-write
REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write
DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write
IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write
SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Increment source address by one unit data size after each read
0x00000001 : TWO
Increment source address by two unit data sizes after each read
0x00000002 : FOUR
Increment source address by four unit data sizes after each read
0x00000003 : NONE
Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
End of enumeration elements list.
SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x00000000 : BYTE
Each unit transfer is a byte
0x00000001 : HALFWORD
Each unit transfer is a half-word
0x00000002 : WORD
Each unit transfer is a word
End of enumeration elements list.
DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Increment destination address by one unit data size after each write
0x00000001 : TWO
Increment destination address by two unit data sizes after each write
0x00000002 : FOUR
Increment destination address by four unit data sizes after each write
0x00000003 : NONE
Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.
End of enumeration elements list.
SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only
DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only
Channel Descriptor Source Data Address Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Descriptor Destination Data Address Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Descriptor Link Structure Address Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only
LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write
LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Peripheral Request Select Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write
SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRS
Peripheral Reflex System
0x00000008 : ADC0
Analog to Digital Converter 0
0x0000000A : VDAC0
Digital to Analog Converter 0
0x0000000C : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x0000000D : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000000E : USART2
Universal Synchronous/Asynchronous Receiver/Transmitter 2
0x0000000F : USART3
Universal Synchronous/Asynchronous Receiver/Transmitter 3
0x00000012 : UART0
Universal Asynchronous Receiver/Transmitter 0
0x00000014 : LEUART0
Low Energy UART 0
0x00000016 : I2C0
I2C 0
0x00000017 : I2C1
I2C 1
0x00000019 : TIMER0
Timer 0
0x0000001A : TIMER1
Timer 1
0x00000020 : WTIMER0
Wide Timer 0
0x00000021 : WTIMER1
Wide Timer 1
0x00000030 : MSC
Memory System Controller
0x00000031 : CRYPTO0
Advanced Encryption Standard Accelerator
0x0000003D : CSEN
Capacitive touch sense module
0x0000003E : LESENSE
Low Energy Sensor Interface
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
One arbitration slot selected
0x00000001 : TWO
Two arbitration slots selected
0x00000002 : FOUR
Four arbitration slots selected
0x00000003 : EIGHT
Eight arbitration slots selected
End of enumeration elements list.
SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write
DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write
Channel Loop Counter Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write
Channel Descriptor Control Word Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0x00000000 : TRANSFER
DMA transfer structure type selected.
0x00000001 : SYNCHRONIZE
Synchronization structure type selected.
0x00000002 : WRITE
Write immediate value structure type selected.
End of enumeration elements list.
STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : write-only
XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write
BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write
BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x00000000 : UNIT1
One unit transfer per arbitration
0x00000001 : UNIT2
Two unit transfers per arbitration
0x00000002 : UNIT3
Three unit transfers per arbitration
0x00000003 : UNIT4
Four unit transfers per arbitration
0x00000004 : UNIT6
Six unit transfers per arbitration
0x00000005 : UNIT8
Eight unit transfers per arbitration
0x00000007 : UNIT16
Sixteen unit transfers per arbitration
0x00000009 : UNIT32
32 unit transfers per arbitration
0x0000000A : UNIT64
64 unit transfers per arbitration
0x0000000B : UNIT128
128 unit transfers per arbitration
0x0000000C : UNIT256
256 unit transfers per arbitration
0x0000000D : UNIT512
512 unit transfers per arbitration
0x0000000E : UNIT1024
1024 unit transfers per arbitration
0x0000000F : ALL
Transfer all units as specified by the XFRCNT field
End of enumeration elements list.
DONEIFSEN : DMA Operation Done Interrupt Flag Set Enable
bits : 20 - 20 (1 bit)
access : read-write
REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write
DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write
IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write
SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Increment source address by one unit data size after each read
0x00000001 : TWO
Increment source address by two unit data sizes after each read
0x00000002 : FOUR
Increment source address by four unit data sizes after each read
0x00000003 : NONE
Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
End of enumeration elements list.
SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x00000000 : BYTE
Each unit transfer is a byte
0x00000001 : HALFWORD
Each unit transfer is a half-word
0x00000002 : WORD
Each unit transfer is a word
End of enumeration elements list.
DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Increment destination address by one unit data size after each write
0x00000001 : TWO
Increment destination address by two unit data sizes after each write
0x00000002 : FOUR
Increment destination address by four unit data sizes after each write
0x00000003 : NONE
Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.
End of enumeration elements list.
SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only
DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only
Channel Descriptor Source Data Address Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Descriptor Destination Data Address Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Descriptor Link Structure Address Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only
LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write
LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Peripheral Request Select Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write
SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRS
Peripheral Reflex System
0x00000008 : ADC0
Analog to Digital Converter 0
0x0000000A : VDAC0
Digital to Analog Converter 0
0x0000000C : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x0000000D : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000000E : USART2
Universal Synchronous/Asynchronous Receiver/Transmitter 2
0x0000000F : USART3
Universal Synchronous/Asynchronous Receiver/Transmitter 3
0x00000012 : UART0
Universal Asynchronous Receiver/Transmitter 0
0x00000014 : LEUART0
Low Energy UART 0
0x00000016 : I2C0
I2C 0
0x00000017 : I2C1
I2C 1
0x00000019 : TIMER0
Timer 0
0x0000001A : TIMER1
Timer 1
0x00000020 : WTIMER0
Wide Timer 0
0x00000021 : WTIMER1
Wide Timer 1
0x00000030 : MSC
Memory System Controller
0x00000031 : CRYPTO0
Advanced Encryption Standard Accelerator
0x0000003D : CSEN
Capacitive touch sense module
0x0000003E : LESENSE
Low Energy Sensor Interface
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
One arbitration slot selected
0x00000001 : TWO
Two arbitration slots selected
0x00000002 : FOUR
Four arbitration slots selected
0x00000003 : EIGHT
Eight arbitration slots selected
End of enumeration elements list.
SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write
DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write
Channel Loop Counter Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write
Channel Descriptor Control Word Register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0x00000000 : TRANSFER
DMA transfer structure type selected.
0x00000001 : SYNCHRONIZE
Synchronization structure type selected.
0x00000002 : WRITE
Write immediate value structure type selected.
End of enumeration elements list.
STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : write-only
XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write
BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write
BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x00000000 : UNIT1
One unit transfer per arbitration
0x00000001 : UNIT2
Two unit transfers per arbitration
0x00000002 : UNIT3
Three unit transfers per arbitration
0x00000003 : UNIT4
Four unit transfers per arbitration
0x00000004 : UNIT6
Six unit transfers per arbitration
0x00000005 : UNIT8
Eight unit transfers per arbitration
0x00000007 : UNIT16
Sixteen unit transfers per arbitration
0x00000009 : UNIT32
32 unit transfers per arbitration
0x0000000A : UNIT64
64 unit transfers per arbitration
0x0000000B : UNIT128
128 unit transfers per arbitration
0x0000000C : UNIT256
256 unit transfers per arbitration
0x0000000D : UNIT512
512 unit transfers per arbitration
0x0000000E : UNIT1024
1024 unit transfers per arbitration
0x0000000F : ALL
Transfer all units as specified by the XFRCNT field
End of enumeration elements list.
DONEIFSEN : DMA Operation Done Interrupt Flag Set Enable
bits : 20 - 20 (1 bit)
access : read-write
REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write
DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write
IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write
SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Increment source address by one unit data size after each read
0x00000001 : TWO
Increment source address by two unit data sizes after each read
0x00000002 : FOUR
Increment source address by four unit data sizes after each read
0x00000003 : NONE
Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
End of enumeration elements list.
SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x00000000 : BYTE
Each unit transfer is a byte
0x00000001 : HALFWORD
Each unit transfer is a half-word
0x00000002 : WORD
Each unit transfer is a word
End of enumeration elements list.
DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Increment destination address by one unit data size after each write
0x00000001 : TWO
Increment destination address by two unit data sizes after each write
0x00000002 : FOUR
Increment destination address by four unit data sizes after each write
0x00000003 : NONE
Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.
End of enumeration elements list.
SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only
DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only
Channel Descriptor Source Data Address Register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Descriptor Destination Data Address Register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Descriptor Link Structure Address Register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only
LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write
LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Peripheral Request Select Register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write
SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRS
Peripheral Reflex System
0x00000008 : ADC0
Analog to Digital Converter 0
0x0000000A : VDAC0
Digital to Analog Converter 0
0x0000000C : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x0000000D : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000000E : USART2
Universal Synchronous/Asynchronous Receiver/Transmitter 2
0x0000000F : USART3
Universal Synchronous/Asynchronous Receiver/Transmitter 3
0x00000012 : UART0
Universal Asynchronous Receiver/Transmitter 0
0x00000014 : LEUART0
Low Energy UART 0
0x00000016 : I2C0
I2C 0
0x00000017 : I2C1
I2C 1
0x00000019 : TIMER0
Timer 0
0x0000001A : TIMER1
Timer 1
0x00000020 : WTIMER0
Wide Timer 0
0x00000021 : WTIMER1
Wide Timer 1
0x00000030 : MSC
Memory System Controller
0x00000031 : CRYPTO0
Advanced Encryption Standard Accelerator
0x0000003D : CSEN
Capacitive touch sense module
0x0000003E : LESENSE
Low Energy Sensor Interface
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
One arbitration slot selected
0x00000001 : TWO
Two arbitration slots selected
0x00000002 : FOUR
Four arbitration slots selected
0x00000003 : EIGHT
Eight arbitration slots selected
End of enumeration elements list.
SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write
DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write
Channel Loop Counter Register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write
Channel Descriptor Control Word Register
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0x00000000 : TRANSFER
DMA transfer structure type selected.
0x00000001 : SYNCHRONIZE
Synchronization structure type selected.
0x00000002 : WRITE
Write immediate value structure type selected.
End of enumeration elements list.
STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : write-only
XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write
BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write
BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x00000000 : UNIT1
One unit transfer per arbitration
0x00000001 : UNIT2
Two unit transfers per arbitration
0x00000002 : UNIT3
Three unit transfers per arbitration
0x00000003 : UNIT4
Four unit transfers per arbitration
0x00000004 : UNIT6
Six unit transfers per arbitration
0x00000005 : UNIT8
Eight unit transfers per arbitration
0x00000007 : UNIT16
Sixteen unit transfers per arbitration
0x00000009 : UNIT32
32 unit transfers per arbitration
0x0000000A : UNIT64
64 unit transfers per arbitration
0x0000000B : UNIT128
128 unit transfers per arbitration
0x0000000C : UNIT256
256 unit transfers per arbitration
0x0000000D : UNIT512
512 unit transfers per arbitration
0x0000000E : UNIT1024
1024 unit transfers per arbitration
0x0000000F : ALL
Transfer all units as specified by the XFRCNT field
End of enumeration elements list.
DONEIFSEN : DMA Operation Done Interrupt Flag Set Enable
bits : 20 - 20 (1 bit)
access : read-write
REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write
DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write
IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write
SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Increment source address by one unit data size after each read
0x00000001 : TWO
Increment source address by two unit data sizes after each read
0x00000002 : FOUR
Increment source address by four unit data sizes after each read
0x00000003 : NONE
Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
End of enumeration elements list.
SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x00000000 : BYTE
Each unit transfer is a byte
0x00000001 : HALFWORD
Each unit transfer is a half-word
0x00000002 : WORD
Each unit transfer is a word
End of enumeration elements list.
DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Increment destination address by one unit data size after each write
0x00000001 : TWO
Increment destination address by two unit data sizes after each write
0x00000002 : FOUR
Increment destination address by four unit data sizes after each write
0x00000003 : NONE
Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.
End of enumeration elements list.
SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only
DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only
Channel Descriptor Source Data Address Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Descriptor Destination Data Address Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Descriptor Link Structure Address Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only
LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write
LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write
DMA Channel Enable Register (Single-Cycle RMW)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enables
bits : 0 - 7 (8 bit)
access : read-write
DMA Channel Busy Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : Channels Busy
bits : 0 - 7 (8 bit)
access : read-only
DMA Channel Linking Done Register (Single-Cycle RMW)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHDONE : DMA Channel Linking or Done
bits : 0 - 7 (8 bit)
access : read-write
DMA Channel Debug Halt Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGHALT : DMA Debug Halt
bits : 0 - 7 (8 bit)
access : read-write
DMA Channel Software Transfer Request Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWREQ : Software Transfer Requests
bits : 0 - 7 (8 bit)
access : write-only
DMA Channel Request Disable Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQDIS : DMA Request Disables
bits : 0 - 7 (8 bit)
access : read-write
DMA Channel Requests Pending Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REQPEND : DMA Requests Pending
bits : 0 - 7 (8 bit)
access : read-only
DMA Channel Link Load Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LINKLOAD : DMA Link Loads
bits : 0 - 7 (8 bit)
access : write-only
DMA Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ANYBUSY : Any DMA Channel Busy
bits : 0 - 0 (1 bit)
access : read-only
ANYREQ : Any DMA Channel Request Pending
bits : 1 - 1 (1 bit)
access : read-only
CHGRANT : Granted Channel Number
bits : 3 - 5 (3 bit)
access : read-only
CHERROR : Errant Channel Number
bits : 8 - 10 (3 bit)
access : read-only
FIFOLEVEL : FIFO Level
bits : 16 - 20 (5 bit)
access : read-only
CHNUM : Number of Channels
bits : 24 - 28 (5 bit)
access : read-only
DMA Channel Request Clear Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
REQCLEAR : DMA Request Clear
bits : 0 - 7 (8 bit)
access : write-only
Interrupt Flag Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DONE : DMA Structure Operation Done Interrupt Flag
bits : 0 - 7 (8 bit)
access : read-only
ERROR : Transfer Error Interrupt Flag
bits : 31 - 31 (1 bit)
access : read-only
Interrupt Flag Set Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DONE : Set DONE Interrupt Flag
bits : 0 - 7 (8 bit)
access : write-only
ERROR : Set ERROR Interrupt Flag
bits : 31 - 31 (1 bit)
access : write-only
Interrupt Flag Clear Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DONE : Clear DONE Interrupt Flag
bits : 0 - 7 (8 bit)
access : write-only
ERROR : Clear ERROR Interrupt Flag
bits : 31 - 31 (1 bit)
access : write-only
Interrupt Enable Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DONE : DONE Interrupt Enable
bits : 0 - 7 (8 bit)
access : read-write
ERROR : ERROR Interrupt Enable
bits : 31 - 31 (1 bit)
access : read-write
DMA Synchronization Trigger Register (Single-Cycle RMW)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCTRIG : Synchronization Trigger
bits : 0 - 7 (8 bit)
access : read-write
Channel Peripheral Request Select Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write
SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRS
Peripheral Reflex System
0x00000008 : ADC0
Analog to Digital Converter 0
0x0000000A : VDAC0
Digital to Analog Converter 0
0x0000000C : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x0000000D : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000000E : USART2
Universal Synchronous/Asynchronous Receiver/Transmitter 2
0x0000000F : USART3
Universal Synchronous/Asynchronous Receiver/Transmitter 3
0x00000012 : UART0
Universal Asynchronous Receiver/Transmitter 0
0x00000014 : LEUART0
Low Energy UART 0
0x00000016 : I2C0
I2C 0
0x00000017 : I2C1
I2C 1
0x00000019 : TIMER0
Timer 0
0x0000001A : TIMER1
Timer 1
0x00000020 : WTIMER0
Wide Timer 0
0x00000021 : WTIMER1
Wide Timer 1
0x00000030 : MSC
Memory System Controller
0x00000031 : CRYPTO0
Advanced Encryption Standard Accelerator
0x0000003D : CSEN
Capacitive touch sense module
0x0000003E : LESENSE
Low Energy Sensor Interface
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
One arbitration slot selected
0x00000001 : TWO
Two arbitration slots selected
0x00000002 : FOUR
Four arbitration slots selected
0x00000003 : EIGHT
Eight arbitration slots selected
End of enumeration elements list.
SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write
DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write
Channel Loop Counter Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write
Channel Descriptor Control Word Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0x00000000 : TRANSFER
DMA transfer structure type selected.
0x00000001 : SYNCHRONIZE
Synchronization structure type selected.
0x00000002 : WRITE
Write immediate value structure type selected.
End of enumeration elements list.
STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : write-only
XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write
BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write
BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x00000000 : UNIT1
One unit transfer per arbitration
0x00000001 : UNIT2
Two unit transfers per arbitration
0x00000002 : UNIT3
Three unit transfers per arbitration
0x00000003 : UNIT4
Four unit transfers per arbitration
0x00000004 : UNIT6
Six unit transfers per arbitration
0x00000005 : UNIT8
Eight unit transfers per arbitration
0x00000007 : UNIT16
Sixteen unit transfers per arbitration
0x00000009 : UNIT32
32 unit transfers per arbitration
0x0000000A : UNIT64
64 unit transfers per arbitration
0x0000000B : UNIT128
128 unit transfers per arbitration
0x0000000C : UNIT256
256 unit transfers per arbitration
0x0000000D : UNIT512
512 unit transfers per arbitration
0x0000000E : UNIT1024
1024 unit transfers per arbitration
0x0000000F : ALL
Transfer all units as specified by the XFRCNT field
End of enumeration elements list.
DONEIFSEN : DMA Operation Done Interrupt Flag Set Enable
bits : 20 - 20 (1 bit)
access : read-write
REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write
DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write
IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write
SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Increment source address by one unit data size after each read
0x00000001 : TWO
Increment source address by two unit data sizes after each read
0x00000002 : FOUR
Increment source address by four unit data sizes after each read
0x00000003 : NONE
Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
End of enumeration elements list.
SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x00000000 : BYTE
Each unit transfer is a byte
0x00000001 : HALFWORD
Each unit transfer is a half-word
0x00000002 : WORD
Each unit transfer is a word
End of enumeration elements list.
DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Increment destination address by one unit data size after each write
0x00000001 : TWO
Increment destination address by two unit data sizes after each write
0x00000002 : FOUR
Increment destination address by four unit data sizes after each write
0x00000003 : NONE
Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.
End of enumeration elements list.
SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only
DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only
Channel Descriptor Source Data Address Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Descriptor Destination Data Address Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Descriptor Link Structure Address Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only
LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write
LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Peripheral Request Select Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write
SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRS
Peripheral Reflex System
0x00000008 : ADC0
Analog to Digital Converter 0
0x0000000A : VDAC0
Digital to Analog Converter 0
0x0000000C : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x0000000D : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000000E : USART2
Universal Synchronous/Asynchronous Receiver/Transmitter 2
0x0000000F : USART3
Universal Synchronous/Asynchronous Receiver/Transmitter 3
0x00000012 : UART0
Universal Asynchronous Receiver/Transmitter 0
0x00000014 : LEUART0
Low Energy UART 0
0x00000016 : I2C0
I2C 0
0x00000017 : I2C1
I2C 1
0x00000019 : TIMER0
Timer 0
0x0000001A : TIMER1
Timer 1
0x00000020 : WTIMER0
Wide Timer 0
0x00000021 : WTIMER1
Wide Timer 1
0x00000030 : MSC
Memory System Controller
0x00000031 : CRYPTO0
Advanced Encryption Standard Accelerator
0x0000003D : CSEN
Capacitive touch sense module
0x0000003E : LESENSE
Low Energy Sensor Interface
End of enumeration elements list.
Channel Configuration Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
One arbitration slot selected
0x00000001 : TWO
Two arbitration slots selected
0x00000002 : FOUR
Four arbitration slots selected
0x00000003 : EIGHT
Eight arbitration slots selected
End of enumeration elements list.
SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write
DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write
Channel Loop Counter Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write
Channel Descriptor Control Word Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0x00000000 : TRANSFER
DMA transfer structure type selected.
0x00000001 : SYNCHRONIZE
Synchronization structure type selected.
0x00000002 : WRITE
Write immediate value structure type selected.
End of enumeration elements list.
STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : write-only
XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write
BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write
BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x00000000 : UNIT1
One unit transfer per arbitration
0x00000001 : UNIT2
Two unit transfers per arbitration
0x00000002 : UNIT3
Three unit transfers per arbitration
0x00000003 : UNIT4
Four unit transfers per arbitration
0x00000004 : UNIT6
Six unit transfers per arbitration
0x00000005 : UNIT8
Eight unit transfers per arbitration
0x00000007 : UNIT16
Sixteen unit transfers per arbitration
0x00000009 : UNIT32
32 unit transfers per arbitration
0x0000000A : UNIT64
64 unit transfers per arbitration
0x0000000B : UNIT128
128 unit transfers per arbitration
0x0000000C : UNIT256
256 unit transfers per arbitration
0x0000000D : UNIT512
512 unit transfers per arbitration
0x0000000E : UNIT1024
1024 unit transfers per arbitration
0x0000000F : ALL
Transfer all units as specified by the XFRCNT field
End of enumeration elements list.
DONEIFSEN : DMA Operation Done Interrupt Flag Set Enable
bits : 20 - 20 (1 bit)
access : read-write
REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write
DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write
IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write
SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Increment source address by one unit data size after each read
0x00000001 : TWO
Increment source address by two unit data sizes after each read
0x00000002 : FOUR
Increment source address by four unit data sizes after each read
0x00000003 : NONE
Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
End of enumeration elements list.
SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x00000000 : BYTE
Each unit transfer is a byte
0x00000001 : HALFWORD
Each unit transfer is a half-word
0x00000002 : WORD
Each unit transfer is a word
End of enumeration elements list.
DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Increment destination address by one unit data size after each write
0x00000001 : TWO
Increment destination address by two unit data sizes after each write
0x00000002 : FOUR
Increment destination address by four unit data sizes after each write
0x00000003 : NONE
Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.
End of enumeration elements list.
SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only
DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only
Channel Descriptor Source Data Address Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Descriptor Destination Data Address Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Descriptor Link Structure Address Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only
LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write
LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Peripheral Request Select Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write
SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : NONE
No source selected
0x00000001 : PRS
Peripheral Reflex System
0x00000008 : ADC0
Analog to Digital Converter 0
0x0000000A : VDAC0
Digital to Analog Converter 0
0x0000000C : USART0
Universal Synchronous/Asynchronous Receiver/Transmitter 0
0x0000000D : USART1
Universal Synchronous/Asynchronous Receiver/Transmitter 1
0x0000000E : USART2
Universal Synchronous/Asynchronous Receiver/Transmitter 2
0x0000000F : USART3
Universal Synchronous/Asynchronous Receiver/Transmitter 3
0x00000012 : UART0
Universal Asynchronous Receiver/Transmitter 0
0x00000014 : LEUART0
Low Energy UART 0
0x00000016 : I2C0
I2C 0
0x00000017 : I2C1
I2C 1
0x00000019 : TIMER0
Timer 0
0x0000001A : TIMER1
Timer 1
0x00000020 : WTIMER0
Wide Timer 0
0x00000021 : WTIMER1
Wide Timer 1
0x00000030 : MSC
Memory System Controller
0x00000031 : CRYPTO0
Advanced Encryption Standard Accelerator
0x0000003D : CSEN
Capacitive touch sense module
0x0000003E : LESENSE
Low Energy Sensor Interface
End of enumeration elements list.
Channel Configuration Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
One arbitration slot selected
0x00000001 : TWO
Two arbitration slots selected
0x00000002 : FOUR
Four arbitration slots selected
0x00000003 : EIGHT
Eight arbitration slots selected
End of enumeration elements list.
SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write
DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write
Channel Loop Counter Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write
Channel Descriptor Control Word Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0x00000000 : TRANSFER
DMA transfer structure type selected.
0x00000001 : SYNCHRONIZE
Synchronization structure type selected.
0x00000002 : WRITE
Write immediate value structure type selected.
End of enumeration elements list.
STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : write-only
XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write
BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write
BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x00000000 : UNIT1
One unit transfer per arbitration
0x00000001 : UNIT2
Two unit transfers per arbitration
0x00000002 : UNIT3
Three unit transfers per arbitration
0x00000003 : UNIT4
Four unit transfers per arbitration
0x00000004 : UNIT6
Six unit transfers per arbitration
0x00000005 : UNIT8
Eight unit transfers per arbitration
0x00000007 : UNIT16
Sixteen unit transfers per arbitration
0x00000009 : UNIT32
32 unit transfers per arbitration
0x0000000A : UNIT64
64 unit transfers per arbitration
0x0000000B : UNIT128
128 unit transfers per arbitration
0x0000000C : UNIT256
256 unit transfers per arbitration
0x0000000D : UNIT512
512 unit transfers per arbitration
0x0000000E : UNIT1024
1024 unit transfers per arbitration
0x0000000F : ALL
Transfer all units as specified by the XFRCNT field
End of enumeration elements list.
DONEIFSEN : DMA Operation Done Interrupt Flag Set Enable
bits : 20 - 20 (1 bit)
access : read-write
REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write
DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write
IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write
SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Increment source address by one unit data size after each read
0x00000001 : TWO
Increment source address by two unit data sizes after each read
0x00000002 : FOUR
Increment source address by four unit data sizes after each read
0x00000003 : NONE
Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
End of enumeration elements list.
SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x00000000 : BYTE
Each unit transfer is a byte
0x00000001 : HALFWORD
Each unit transfer is a half-word
0x00000002 : WORD
Each unit transfer is a word
End of enumeration elements list.
DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONE
Increment destination address by one unit data size after each write
0x00000001 : TWO
Increment destination address by two unit data sizes after each write
0x00000002 : FOUR
Increment destination address by four unit data sizes after each write
0x00000003 : NONE
Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.
End of enumeration elements list.
SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only
DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only
Channel Descriptor Source Data Address Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Descriptor Destination Data Address Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Descriptor Link Structure Address Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only
LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write
LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write
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