Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
Supply Controller Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
VROFF : Voltage Regulator Off
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
0 : NO_EFFECT
no effect.
1 : STOP_VREG
if KEY is correct, asserts vddcore_nreset and stops the voltage regulator.
End of enumeration elements list.
XTALSEL : Crystal Oscillator Select
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
0 : NO_EFFECT
no effect.
1 : CRYSTAL_SEL
if KEY is correct, switches the slow clock on the crystal oscillator output.
End of enumeration elements list.
KEY : Password
bits : 24 - 31 (8 bit)
access : write-only
Supply Controller Wake Up Inputs Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKUPEN0 : Wake Up Input Enable 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
the corresponding wake-up input has no wake up effect.
1 : ENABLE
the corresponding wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPEN1 : Wake Up Input Enable 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
the corresponding wake-up input has no wake up effect.
1 : ENABLE
the corresponding wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPEN2 : Wake Up Input Enable 2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
the corresponding wake-up input has no wake up effect.
1 : ENABLE
the corresponding wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPEN3 : Wake Up Input Enable 3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
the corresponding wake-up input has no wake up effect.
1 : ENABLE
the corresponding wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPEN4 : Wake Up Input Enable 4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
the corresponding wake-up input has no wake up effect.
1 : ENABLE
the corresponding wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPEN5 : Wake Up Input Enable 5
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
the corresponding wake-up input has no wake up effect.
1 : ENABLE
the corresponding wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPEN6 : Wake Up Input Enable 6
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
the corresponding wake-up input has no wake up effect.
1 : ENABLE
the corresponding wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPEN7 : Wake Up Input Enable 7
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
the corresponding wake-up input has no wake up effect.
1 : ENABLE
the corresponding wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPEN8 : Wake Up Input Enable 8
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
the corresponding wake-up input has no wake up effect.
1 : ENABLE
the corresponding wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPEN9 : Wake Up Input Enable 9
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
the corresponding wake-up input has no wake up effect.
1 : ENABLE
the corresponding wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPEN10 : Wake Up Input Enable 10
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
the corresponding wake-up input has no wake up effect.
1 : ENABLE
the corresponding wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPEN11 : Wake Up Input Enable 11
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
the corresponding wake-up input has no wake up effect.
1 : ENABLE
the corresponding wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPEN12 : Wake Up Input Enable 12
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
the corresponding wake-up input has no wake up effect.
1 : ENABLE
the corresponding wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPEN13 : Wake Up Input Enable 13
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
the corresponding wake-up input has no wake up effect.
1 : ENABLE
the corresponding wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPEN14 : Wake Up Input Enable 14
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
the corresponding wake-up input has no wake up effect.
1 : ENABLE
the corresponding wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPEN15 : Wake Up Input Enable 15
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
the corresponding wake-up input has no wake up effect.
1 : ENABLE
the corresponding wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPT0 : Wake Up Input Type 0
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : HIGH_TO_LOW
a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
1 : LOW_TO_HIGH
a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPT1 : Wake Up Input Type 1
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : HIGH_TO_LOW
a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
1 : LOW_TO_HIGH
a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPT2 : Wake Up Input Type 2
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : HIGH_TO_LOW
a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
1 : LOW_TO_HIGH
a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPT3 : Wake Up Input Type 3
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : HIGH_TO_LOW
a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
1 : LOW_TO_HIGH
a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPT4 : Wake Up Input Type 4
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : HIGH_TO_LOW
a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
1 : LOW_TO_HIGH
a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPT5 : Wake Up Input Type 5
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : HIGH_TO_LOW
a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
1 : LOW_TO_HIGH
a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPT6 : Wake Up Input Type 6
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : HIGH_TO_LOW
a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
1 : LOW_TO_HIGH
a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPT7 : Wake Up Input Type 7
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : HIGH_TO_LOW
a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
1 : LOW_TO_HIGH
a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPT8 : Wake Up Input Type 8
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : HIGH_TO_LOW
a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
1 : LOW_TO_HIGH
a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPT9 : Wake Up Input Type 9
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : HIGH_TO_LOW
a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
1 : LOW_TO_HIGH
a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPT10 : Wake Up Input Type 10
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : HIGH_TO_LOW
a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
1 : LOW_TO_HIGH
a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPT11 : Wake Up Input Type 11
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : HIGH_TO_LOW
a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
1 : LOW_TO_HIGH
a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPT12 : Wake Up Input Type 12
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : HIGH_TO_LOW
a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
1 : LOW_TO_HIGH
a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPT13 : Wake Up Input Type 13
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : HIGH_TO_LOW
a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
1 : LOW_TO_HIGH
a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPT14 : Wake Up Input Type 14
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : HIGH_TO_LOW
a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
1 : LOW_TO_HIGH
a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
WKUPT15 : Wake Up Input Type 15
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : HIGH_TO_LOW
a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
1 : LOW_TO_HIGH
a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
End of enumeration elements list.
Supply Controller Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WKUPS : WKUP Wake Up Status
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : NO
no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
1 : PRESENT
at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
End of enumeration elements list.
SMWS : Supply Monitor Detection Wake Up Status
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : NO
no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR.
1 : PRESENT
at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR.
End of enumeration elements list.
BODRSTS : Brownout Detector Reset Status
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : NO
no core brownout rising edge event has been detected since the last read of the SUPC_SR.
1 : PRESENT
at least one brownout output rising edge event has been detected since the last read of the SUPC_SR.
End of enumeration elements list.
SMRSTS : Supply Monitor Reset Status
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : NO
no supply monitor detection has generated a core reset since the last read of the SUPC_SR.
1 : PRESENT
at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR.
End of enumeration elements list.
SMS : Supply Monitor Status
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : NO
no supply monitor detection since the last read of SUPC_SR.
1 : PRESENT
at least one supply monitor detection since the last read of SUPC_SR.
End of enumeration elements list.
SMOS : Supply Monitor Output Status
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : HIGH
the supply monitor detected VDDIO higher than its threshold at its last measurement.
1 : LOW
the supply monitor detected VDDIO lower than its threshold at its last measurement.
End of enumeration elements list.
OSCSEL : 32-kHz Oscillator Selection Status
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : RC
the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator.
1 : CRYST
the slow clock, SLCK is generated by the 32-kHz crystal oscillator.
End of enumeration elements list.
WKUPIS0 : WKUP Input Status 0
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : DIS
the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 : EN
the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
End of enumeration elements list.
WKUPIS1 : WKUP Input Status 1
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : DIS
the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 : EN
the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
End of enumeration elements list.
WKUPIS2 : WKUP Input Status 2
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : DIS
the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 : EN
the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
End of enumeration elements list.
WKUPIS3 : WKUP Input Status 3
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : DIS
the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 : EN
the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
End of enumeration elements list.
WKUPIS4 : WKUP Input Status 4
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : DIS
the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 : EN
the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
End of enumeration elements list.
WKUPIS5 : WKUP Input Status 5
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : DIS
the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 : EN
the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
End of enumeration elements list.
WKUPIS6 : WKUP Input Status 6
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : DIS
the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 : EN
the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
End of enumeration elements list.
WKUPIS7 : WKUP Input Status 7
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : DIS
the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 : EN
the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
End of enumeration elements list.
WKUPIS8 : WKUP Input Status 8
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : DIS
the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 : EN
the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
End of enumeration elements list.
WKUPIS9 : WKUP Input Status 9
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : DIS
the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 : EN
the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
End of enumeration elements list.
WKUPIS10 : WKUP Input Status 10
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : DIS
the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 : EN
the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
End of enumeration elements list.
WKUPIS11 : WKUP Input Status 11
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : DIS
the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 : EN
the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
End of enumeration elements list.
WKUPIS12 : WKUP Input Status 12
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : DIS
the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 : EN
the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
End of enumeration elements list.
WKUPIS13 : WKUP Input Status 13
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : DIS
the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 : EN
the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
End of enumeration elements list.
WKUPIS14 : WKUP Input Status 14
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : DIS
the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 : EN
the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
End of enumeration elements list.
WKUPIS15 : WKUP Input Status 15
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : DIS
the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 : EN
the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
End of enumeration elements list.
Supply Controller Supply Monitor Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMTH : Supply Monitor Threshold
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : 1_9V
1.9 V
0x1 : 2_0V
2.0 V
0x2 : 2_1V
2.1 V
0x3 : 2_2V
2.2 V
0x4 : 2_3V
2.3 V
0x5 : 2_4V
2.4 V
0x6 : 2_5V
2.5 V
0x7 : 2_6V
2.6 V
0x8 : 2_7V
2.7 V
0x9 : 2_8V
2.8 V
0xA : 2_9V
2.9 V
0xB : 3_0V
3.0 V
0xC : 3_1V
3.1 V
0xD : 3_2V
3.2 V
0xE : 3_3V
3.3 V
0xF : 3_4V
3.4 V
End of enumeration elements list.
SMSMPL : Supply Monitor Sampling Period
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : SMD
Supply Monitor disabled
0x1 : CSM
Continuous Supply Monitor
0x2 : 32SLCK
Supply Monitor enabled one SLCK period every 32 SLCK periods
0x3 : 256SLCK
Supply Monitor enabled one SLCK period every 256 SLCK periods
0x4 : 2048SLCK
Supply Monitor enabled one SLCK period every 2,048 SLCK periods
End of enumeration elements list.
SMRSTEN : Supply Monitor Reset Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ENABLE
the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs.
1 : ENABLE
the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.
End of enumeration elements list.
SMIEN : Supply Monitor Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ENABLE
the SUPC interrupt signal is not affected when a supply monitor detection occurs.
1 : ENABLE
the SUPC interrupt signal is asserted when a supply monitor detection occurs.
End of enumeration elements list.
Supply Controller Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODRSTEN : Brownout Detector Reset Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ENABLE
the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs.
1 : ENABLE
the core reset signal, vddcore_nreset is asserted when a brownout detection occurs.
End of enumeration elements list.
BODDIS : Brownout Detector Disable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : ENABLE
the core brownout detector is enabled.
1 : DISABLE
the core brownout detector is disabled.
End of enumeration elements list.
ONREG : Voltage Regulator enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : ONREG_UNUSED
Voltage Regulator is not used
1 : ONREG_USED
Voltage Regulator is used
End of enumeration elements list.
OSCBYPASS : Oscillator Bypass
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NO_EFFECT
no effect. Clock selection depends on XTALSEL value.
1 : BYPASS
the 32-KHz XTAL oscillator is selected and is put in bypass mode.
End of enumeration elements list.
KEY : Password Key
bits : 24 - 31 (8 bit)
access : read-write
Supply Controller Wake Up Mode Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMEN : Supply Monitor Wake Up Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ENABLE
the supply monitor detection has no wake up effect.
1 : ENABLE
the supply monitor detection forces the wake up of the core power supply.
End of enumeration elements list.
RTTEN : Real Time Timer Wake Up Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ENABLE
the RTT alarm signal has no wake up effect.
1 : ENABLE
the RTT alarm signal forces the wake up of the core power supply.
End of enumeration elements list.
RTCEN : Real Time Clock Wake Up Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ENABLE
the RTC alarm signal has no wake up effect.
1 : ENABLE
the RTC alarm signal forces the wake up of the core power supply.
End of enumeration elements list.
WKUPDBC : Wake Up Inputs Debouncer Period
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : IMMEDIATE
Immediate, no debouncing, detected active at least on one Slow Clock edge.
0x1 : 3_SCLK
WKUPx shall be in its active state for at least 3 SLCK periods
0x2 : 32_SCLK
WKUPx shall be in its active state for at least 32 SLCK periods
0x3 : 512_SCLK
WKUPx shall be in its active state for at least 512 SLCK periods
0x4 : 4096_SCLK
WKUPx shall be in its active state for at least 4,096 SLCK periods
0x5 : 32768_SCLK
WKUPx shall be in its active state for at least 32,768 SLCK periods
End of enumeration elements list.
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