\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only
Interrupt Disable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY : Transmission Ready Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
ENDTX : End of PDC Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
TXBUFE : Buffer Empty Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
Transmit Pointer Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPTR : Transmit Counter Register
bits : 0 - 31 (32 bit)
access : read-write
Transmit Counter Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCTR : Transmit Counter Register
bits : 0 - 15 (16 bit)
access : read-write
Transmit Next Pointer Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNPTR : Transmit Next Pointer
bits : 0 - 31 (32 bit)
access : read-write
Transmit Next Counter Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNCTR : Transmit Counter Next
bits : 0 - 15 (16 bit)
access : read-write
Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only
RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only
TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only
Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only
Interrupt Mask Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY : Transmission Ready Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
ENDTX : End of PDC Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
TXBUFE : Buffer Empty Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY : Transmission Ready Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only
ENDTX : End of PDC Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only
TXBUFE : Buffer Empty Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGEN : Trigger Enable
bits : 0 - 0 (1 bit)
access : read-write
TRGSEL : Trigger Selection
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
0x0 : TRGSEL0
External trigger
0x1 : TRGSEL1
TIO Output of the Timer Counter Channel 0
0x2 : TRGSEL2
TIO Output of the Timer Counter Channel 1
0x3 : TRGSEL3
TIO Output of the Timer Counter Channel 2
End of enumeration elements list.
DACEN : DAC enable
bits : 4 - 4 (1 bit)
access : read-write
WORD : Word Transfer
bits : 5 - 5 (1 bit)
access : read-write
STARTUP : Startup Time Selection
bits : 8 - 15 (8 bit)
access : read-write
CLKDIV : DAC Clock Divider for Internal Trigger
bits : 16 - 31 (16 bit)
access : read-write
Conversion Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Convert
bits : 0 - 31 (32 bit)
access : write-only
Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY : Transmission Ready Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
ENDTX : End of PDC Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
TXBUFE : Buffer Empty Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
Write Protect Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protect KEY
bits : 8 - 31 (24 bit)
access : read-write
Write Protect Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPROTERR : Write protection error
bits : 0 - 0 (1 bit)
access : read-only
WPROTADDR : Write protection error address
bits : 8 - 15 (8 bit)
access : read-only
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