\n
address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
Master Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Master Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Slave Configuration Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
System I/O Configuration register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSIO4 : PB4 or TDI Assignment
bits : 4 - 4 (1 bit)
access : read-write
SYSIO5 : PB5 or TDO/TRACESWO Assignment
bits : 5 - 5 (1 bit)
access : read-write
SYSIO6 : PB6 or TMS/SWDIO Assignment
bits : 6 - 6 (1 bit)
access : read-write
SYSIO7 : PB7 or TCK/SWCLK Assignment
bits : 7 - 7 (1 bit)
access : read-write
SYSIO12 : PB12 or ERASE Assignment
bits : 12 - 12 (1 bit)
access : read-write
Slave Configuration Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
Write Protect Mode Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protect ENable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protect KEY (Write-only)
bits : 8 - 31 (24 bit)
access : read-write
Write Protect Status Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protect Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protect Violation Source
bits : 8 - 23 (16 bit)
access : read-only
Master Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Master Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Slave Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
Slave Configuration Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
Slave Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
Slave Configuration Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
Master Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Slave Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
Priority Register A for Slave 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
Priority Register A for Slave 1
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
Priority Register A for Slave 2
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
Priority Register A for Slave 3
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
Master Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Slave Configuration Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
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