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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

SEQR[0]

CHER

RPR

RCR

RNPR

RNCR

PTCR

PTSR

CHDR

CDR[2]

CHSR

CDR[3]

SEQR[1]

LCDR

CDR[4]

IER

CDR[5]

IDR

IMR

CDR[6]

ISR

CDR[7]

CDR[8]

OVER

MR

EMR

CDR[9]

CWR

CGR

CDR[10]

COR

CDR0

CDR[11]

CDR1

CDR2

CDR[12]

CDR3

CDR4

CDR[13]

CDR5

CDR6

CDR[14]

CDR7

CDR8

CDR9

CDR10

CDR11

SEQR0

CDR12

CDR13

CDR14

ACR

CDR[0]

SEQR1

WPMR

WPSR

CDR[1]


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST START

SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only

START : Start Conversion
bits : 1 - 1 (1 bit)
access : write-only


SEQR[0]

Channel Sequence Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQR[0] SEQR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CHER

Channel Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHER CHER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15

CH0 : Channel 0 Enable
bits : 0 - 0 (1 bit)
access : write-only

CH1 : Channel 1 Enable
bits : 1 - 1 (1 bit)
access : write-only

CH2 : Channel 2 Enable
bits : 2 - 2 (1 bit)
access : write-only

CH3 : Channel 3 Enable
bits : 3 - 3 (1 bit)
access : write-only

CH4 : Channel 4 Enable
bits : 4 - 4 (1 bit)
access : write-only

CH5 : Channel 5 Enable
bits : 5 - 5 (1 bit)
access : write-only

CH6 : Channel 6 Enable
bits : 6 - 6 (1 bit)
access : write-only

CH7 : Channel 7 Enable
bits : 7 - 7 (1 bit)
access : write-only

CH8 : Channel 8 Enable
bits : 8 - 8 (1 bit)
access : write-only

CH9 : Channel 9 Enable
bits : 9 - 9 (1 bit)
access : write-only

CH10 : Channel 10 Enable
bits : 10 - 10 (1 bit)
access : write-only

CH11 : Channel 11 Enable
bits : 11 - 11 (1 bit)
access : write-only

CH12 : Channel 12 Enable
bits : 12 - 12 (1 bit)
access : write-only

CH13 : Channel 13 Enable
bits : 13 - 13 (1 bit)
access : write-only

CH14 : Channel 14 Enable
bits : 14 - 14 (1 bit)
access : write-only

CH15 : Channel 15 Enable
bits : 15 - 15 (1 bit)
access : write-only


RPR

Receive Pointer Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPR RPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPTR

RXPTR : Receive Pointer Register
bits : 0 - 31 (32 bit)
access : read-write


RCR

Receive Counter Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCTR

RXCTR : Receive Counter Register
bits : 0 - 15 (16 bit)
access : read-write


RNPR

Receive Next Pointer Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNPR RNPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNPTR

RXNPTR : Receive Next Pointer
bits : 0 - 31 (32 bit)
access : read-write


RNCR

Receive Next Counter Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNCR RNCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNCTR

RXNCTR : Receive Next Counter
bits : 0 - 15 (16 bit)
access : read-write


PTCR

Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PTCR PTCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN RXTDIS TXTEN TXTDIS

RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only

RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only

TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only

TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only


PTSR

Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PTSR PTSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN TXTEN

RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only

TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only


CHDR

Channel Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHDR CHDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15

CH0 : Channel 0 Disable
bits : 0 - 0 (1 bit)
access : write-only

CH1 : Channel 1 Disable
bits : 1 - 1 (1 bit)
access : write-only

CH2 : Channel 2 Disable
bits : 2 - 2 (1 bit)
access : write-only

CH3 : Channel 3 Disable
bits : 3 - 3 (1 bit)
access : write-only

CH4 : Channel 4 Disable
bits : 4 - 4 (1 bit)
access : write-only

CH5 : Channel 5 Disable
bits : 5 - 5 (1 bit)
access : write-only

CH6 : Channel 6 Disable
bits : 6 - 6 (1 bit)
access : write-only

CH7 : Channel 7 Disable
bits : 7 - 7 (1 bit)
access : write-only

CH8 : Channel 8 Disable
bits : 8 - 8 (1 bit)
access : write-only

CH9 : Channel 9 Disable
bits : 9 - 9 (1 bit)
access : write-only

CH10 : Channel 10 Disable
bits : 10 - 10 (1 bit)
access : write-only

CH11 : Channel 11 Disable
bits : 11 - 11 (1 bit)
access : write-only

CH12 : Channel 12 Disable
bits : 12 - 12 (1 bit)
access : write-only

CH13 : Channel 13 Disable
bits : 13 - 13 (1 bit)
access : write-only

CH14 : Channel 14 Disable
bits : 14 - 14 (1 bit)
access : write-only

CH15 : Channel 15 Disable
bits : 15 - 15 (1 bit)
access : write-only


CDR[2]

Channel Data Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[2] CDR[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CHSR

Channel Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSR CHSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15

CH0 : Channel 0 Status
bits : 0 - 0 (1 bit)
access : read-only

CH1 : Channel 1 Status
bits : 1 - 1 (1 bit)
access : read-only

CH2 : Channel 2 Status
bits : 2 - 2 (1 bit)
access : read-only

CH3 : Channel 3 Status
bits : 3 - 3 (1 bit)
access : read-only

CH4 : Channel 4 Status
bits : 4 - 4 (1 bit)
access : read-only

CH5 : Channel 5 Status
bits : 5 - 5 (1 bit)
access : read-only

CH6 : Channel 6 Status
bits : 6 - 6 (1 bit)
access : read-only

CH7 : Channel 7 Status
bits : 7 - 7 (1 bit)
access : read-only

CH8 : Channel 8 Status
bits : 8 - 8 (1 bit)
access : read-only

CH9 : Channel 9 Status
bits : 9 - 9 (1 bit)
access : read-only

CH10 : Channel 10 Status
bits : 10 - 10 (1 bit)
access : read-only

CH11 : Channel 11 Status
bits : 11 - 11 (1 bit)
access : read-only

CH12 : Channel 12 Status
bits : 12 - 12 (1 bit)
access : read-only

CH13 : Channel 13 Status
bits : 13 - 13 (1 bit)
access : read-only

CH14 : Channel 14 Status
bits : 14 - 14 (1 bit)
access : read-only

CH15 : Channel 15 Status
bits : 15 - 15 (1 bit)
access : read-only


CDR[3]

Channel Data Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[3] CDR[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


SEQR[1]

Channel Sequence Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQR[1] SEQR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LCDR

Last Converted Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LCDR LCDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDATA CHNB

LDATA : Last Data Converted
bits : 0 - 11 (12 bit)
access : read-only

CHNB : Channel Number
bits : 12 - 15 (4 bit)
access : read-only


CDR[4]

Channel Data Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[4] CDR[4] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


IER

Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOC0 EOC1 EOC2 EOC3 EOC4 EOC5 EOC6 EOC7 EOC8 EOC9 EOC10 EOC11 EOC12 EOC13 EOC14 EOC15 DRDY GOVRE COMPE ENDRX RXBUFF

EOC0 : End of Conversion Interrupt Enable 0
bits : 0 - 0 (1 bit)
access : write-only

EOC1 : End of Conversion Interrupt Enable 1
bits : 1 - 1 (1 bit)
access : write-only

EOC2 : End of Conversion Interrupt Enable 2
bits : 2 - 2 (1 bit)
access : write-only

EOC3 : End of Conversion Interrupt Enable 3
bits : 3 - 3 (1 bit)
access : write-only

EOC4 : End of Conversion Interrupt Enable 4
bits : 4 - 4 (1 bit)
access : write-only

EOC5 : End of Conversion Interrupt Enable 5
bits : 5 - 5 (1 bit)
access : write-only

EOC6 : End of Conversion Interrupt Enable 6
bits : 6 - 6 (1 bit)
access : write-only

EOC7 : End of Conversion Interrupt Enable 7
bits : 7 - 7 (1 bit)
access : write-only

EOC8 : End of Conversion Interrupt Enable 8
bits : 8 - 8 (1 bit)
access : write-only

EOC9 : End of Conversion Interrupt Enable 9
bits : 9 - 9 (1 bit)
access : write-only

EOC10 : End of Conversion Interrupt Enable 10
bits : 10 - 10 (1 bit)
access : write-only

EOC11 : End of Conversion Interrupt Enable 11
bits : 11 - 11 (1 bit)
access : write-only

EOC12 : End of Conversion Interrupt Enable 12
bits : 12 - 12 (1 bit)
access : write-only

EOC13 : End of Conversion Interrupt Enable 13
bits : 13 - 13 (1 bit)
access : write-only

EOC14 : End of Conversion Interrupt Enable 14
bits : 14 - 14 (1 bit)
access : write-only

EOC15 : End of Conversion Interrupt Enable 15
bits : 15 - 15 (1 bit)
access : write-only

DRDY : Data Ready Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only

GOVRE : General Overrun Error Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only

COMPE : Comparison Event Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only

ENDRX : End of Receive Buffer Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only

RXBUFF : Receive Buffer Full Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only


CDR[5]

Channel Data Register
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[5] CDR[5] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


IDR

Interrupt Disable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOC0 EOC1 EOC2 EOC3 EOC4 EOC5 EOC6 EOC7 EOC8 EOC9 EOC10 EOC11 EOC12 EOC13 EOC14 EOC15 DRDY GOVRE COMPE ENDRX RXBUFF

EOC0 : End of Conversion Interrupt Disable 0
bits : 0 - 0 (1 bit)
access : write-only

EOC1 : End of Conversion Interrupt Disable 1
bits : 1 - 1 (1 bit)
access : write-only

EOC2 : End of Conversion Interrupt Disable 2
bits : 2 - 2 (1 bit)
access : write-only

EOC3 : End of Conversion Interrupt Disable 3
bits : 3 - 3 (1 bit)
access : write-only

EOC4 : End of Conversion Interrupt Disable 4
bits : 4 - 4 (1 bit)
access : write-only

EOC5 : End of Conversion Interrupt Disable 5
bits : 5 - 5 (1 bit)
access : write-only

EOC6 : End of Conversion Interrupt Disable 6
bits : 6 - 6 (1 bit)
access : write-only

EOC7 : End of Conversion Interrupt Disable 7
bits : 7 - 7 (1 bit)
access : write-only

EOC8 : End of Conversion Interrupt Disable 8
bits : 8 - 8 (1 bit)
access : write-only

EOC9 : End of Conversion Interrupt Disable 9
bits : 9 - 9 (1 bit)
access : write-only

EOC10 : End of Conversion Interrupt Disable 10
bits : 10 - 10 (1 bit)
access : write-only

EOC11 : End of Conversion Interrupt Disable 11
bits : 11 - 11 (1 bit)
access : write-only

EOC12 : End of Conversion Interrupt Disable 12
bits : 12 - 12 (1 bit)
access : write-only

EOC13 : End of Conversion Interrupt Disable 13
bits : 13 - 13 (1 bit)
access : write-only

EOC14 : End of Conversion Interrupt Disable 14
bits : 14 - 14 (1 bit)
access : write-only

EOC15 : End of Conversion Interrupt Disable 15
bits : 15 - 15 (1 bit)
access : write-only

DRDY : Data Ready Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only

GOVRE : General Overrun Error Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only

COMPE : Comparison Event Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only

ENDRX : End of Receive Buffer Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only

RXBUFF : Receive Buffer Full Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only


IMR

Interrupt Mask Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOC0 EOC1 EOC2 EOC3 EOC4 EOC5 EOC6 EOC7 EOC8 EOC9 EOC10 EOC11 EOC12 EOC13 EOC14 EOC15 DRDY GOVRE COMPE ENDRX RXBUFF

EOC0 : End of Conversion Interrupt Mask 0
bits : 0 - 0 (1 bit)
access : read-only

EOC1 : End of Conversion Interrupt Mask 1
bits : 1 - 1 (1 bit)
access : read-only

EOC2 : End of Conversion Interrupt Mask 2
bits : 2 - 2 (1 bit)
access : read-only

EOC3 : End of Conversion Interrupt Mask 3
bits : 3 - 3 (1 bit)
access : read-only

EOC4 : End of Conversion Interrupt Mask 4
bits : 4 - 4 (1 bit)
access : read-only

EOC5 : End of Conversion Interrupt Mask 5
bits : 5 - 5 (1 bit)
access : read-only

EOC6 : End of Conversion Interrupt Mask 6
bits : 6 - 6 (1 bit)
access : read-only

EOC7 : End of Conversion Interrupt Mask 7
bits : 7 - 7 (1 bit)
access : read-only

EOC8 : End of Conversion Interrupt Mask 8
bits : 8 - 8 (1 bit)
access : read-only

EOC9 : End of Conversion Interrupt Mask 9
bits : 9 - 9 (1 bit)
access : read-only

EOC10 : End of Conversion Interrupt Mask 10
bits : 10 - 10 (1 bit)
access : read-only

EOC11 : End of Conversion Interrupt Mask 11
bits : 11 - 11 (1 bit)
access : read-only

EOC12 : End of Conversion Interrupt Mask 12
bits : 12 - 12 (1 bit)
access : read-only

EOC13 : End of Conversion Interrupt Mask 13
bits : 13 - 13 (1 bit)
access : read-only

EOC14 : End of Conversion Interrupt Mask 14
bits : 14 - 14 (1 bit)
access : read-only

EOC15 : End of Conversion Interrupt Mask 15
bits : 15 - 15 (1 bit)
access : read-only

DRDY : Data Ready Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only

GOVRE : General Overrun Error Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only

COMPE : Comparison Event Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only

ENDRX : End of Receive Buffer Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only

RXBUFF : Receive Buffer Full Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only


CDR[6]

Channel Data Register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[6] CDR[6] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


ISR

Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOC0 EOC1 EOC2 EOC3 EOC4 EOC5 EOC6 EOC7 EOC8 EOC9 EOC10 EOC11 EOC12 EOC13 EOC14 EOC15 DRDY GOVRE COMPE ENDRX RXBUFF

EOC0 : End of Conversion 0
bits : 0 - 0 (1 bit)
access : read-only

EOC1 : End of Conversion 1
bits : 1 - 1 (1 bit)
access : read-only

EOC2 : End of Conversion 2
bits : 2 - 2 (1 bit)
access : read-only

EOC3 : End of Conversion 3
bits : 3 - 3 (1 bit)
access : read-only

EOC4 : End of Conversion 4
bits : 4 - 4 (1 bit)
access : read-only

EOC5 : End of Conversion 5
bits : 5 - 5 (1 bit)
access : read-only

EOC6 : End of Conversion 6
bits : 6 - 6 (1 bit)
access : read-only

EOC7 : End of Conversion 7
bits : 7 - 7 (1 bit)
access : read-only

EOC8 : End of Conversion 8
bits : 8 - 8 (1 bit)
access : read-only

EOC9 : End of Conversion 9
bits : 9 - 9 (1 bit)
access : read-only

EOC10 : End of Conversion 10
bits : 10 - 10 (1 bit)
access : read-only

EOC11 : End of Conversion 11
bits : 11 - 11 (1 bit)
access : read-only

EOC12 : End of Conversion 12
bits : 12 - 12 (1 bit)
access : read-only

EOC13 : End of Conversion 13
bits : 13 - 13 (1 bit)
access : read-only

EOC14 : End of Conversion 14
bits : 14 - 14 (1 bit)
access : read-only

EOC15 : End of Conversion 15
bits : 15 - 15 (1 bit)
access : read-only

DRDY : Data Ready
bits : 24 - 24 (1 bit)
access : read-only

GOVRE : General Overrun Error
bits : 25 - 25 (1 bit)
access : read-only

COMPE : Comparison Error
bits : 26 - 26 (1 bit)
access : read-only

ENDRX : End of RX Buffer
bits : 27 - 27 (1 bit)
access : read-only

RXBUFF : RX Buffer Full
bits : 28 - 28 (1 bit)
access : read-only


CDR[7]

Channel Data Register
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[7] CDR[7] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR[8]

Channel Data Register
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[8] CDR[8] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


OVER

Overrun Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OVER OVER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVRE0 OVRE1 OVRE2 OVRE3 OVRE4 OVRE5 OVRE6 OVRE7 OVRE8 OVRE9 OVRE10 OVRE11 OVRE12 OVRE13 OVRE14 OVRE15

OVRE0 : Overrun Error 0
bits : 0 - 0 (1 bit)
access : read-only

OVRE1 : Overrun Error 1
bits : 1 - 1 (1 bit)
access : read-only

OVRE2 : Overrun Error 2
bits : 2 - 2 (1 bit)
access : read-only

OVRE3 : Overrun Error 3
bits : 3 - 3 (1 bit)
access : read-only

OVRE4 : Overrun Error 4
bits : 4 - 4 (1 bit)
access : read-only

OVRE5 : Overrun Error 5
bits : 5 - 5 (1 bit)
access : read-only

OVRE6 : Overrun Error 6
bits : 6 - 6 (1 bit)
access : read-only

OVRE7 : Overrun Error 7
bits : 7 - 7 (1 bit)
access : read-only

OVRE8 : Overrun Error 8
bits : 8 - 8 (1 bit)
access : read-only

OVRE9 : Overrun Error 9
bits : 9 - 9 (1 bit)
access : read-only

OVRE10 : Overrun Error 10
bits : 10 - 10 (1 bit)
access : read-only

OVRE11 : Overrun Error 11
bits : 11 - 11 (1 bit)
access : read-only

OVRE12 : Overrun Error 12
bits : 12 - 12 (1 bit)
access : read-only

OVRE13 : Overrun Error 13
bits : 13 - 13 (1 bit)
access : read-only

OVRE14 : Overrun Error 14
bits : 14 - 14 (1 bit)
access : read-only

OVRE15 : Overrun Error 15
bits : 15 - 15 (1 bit)
access : read-only


MR

Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGEN TRGSEL SLEEP FWUP FREERUN PRESCAL STARTUP SETTLING ANACH TRACKTIM TRANSFER USEQ

TRGEN : Trigger Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Hardware triggers are disabled. Starting a conversion is only possible by software.

1 : EN

Hardware trigger selected by TRGSEL field is enabled.

End of enumeration elements list.

TRGSEL : Trigger Selection
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

0x0 : ADC_TRIG0

External trigger

0x1 : ADC_TRIG1

TIO Output of the Timer Counter Channel 0

0x2 : ADC_TRIG2

TIO Output of the Timer Counter Channel 1

0x3 : ADC_TRIG3

TIO Output of the Timer Counter Channel 2

0x4 : ADC_TRIG4

PWM Event Line 0

0x5 : ADC_TRIG5

PWM Event Line 1

End of enumeration elements list.

SLEEP : Sleep Mode
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NORMAL

Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions

1 : SLEEP

Sleep Mode: The wake-up time can be modified by programming FWUP bit

End of enumeration elements list.

FWUP : Fast Wake Up
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : OFF

If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions

1 : ON

If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF

End of enumeration elements list.

FREERUN : Free Run Mode
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : OFF

Normal Mode

1 : ON

Free Run Mode: Never wait for any trigger.

End of enumeration elements list.

PRESCAL : Prescaler Rate Selection
bits : 8 - 15 (8 bit)
access : read-write

STARTUP : Start Up Time
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x0 : SUT0

0 periods of ADCClock

0x1 : SUT8

8 periods of ADCClock

0x2 : SUT16

16 periods of ADCClock

0x3 : SUT24

24 periods of ADCClock

0x4 : SUT64

64 periods of ADCClock

0x5 : SUT80

80 periods of ADCClock

0x6 : SUT96

96 periods of ADCClock

0x7 : SUT112

112 periods of ADCClock

0x8 : SUT512

512 periods of ADCClock

0x9 : SUT576

576 periods of ADCClock

0xA : SUT640

640 periods of ADCClock

0xB : SUT704

704 periods of ADCClock

0xC : SUT768

768 periods of ADCClock

0xD : SUT832

832 periods of ADCClock

0xE : SUT896

896 periods of ADCClock

0xF : SUT960

960 periods of ADCClock

End of enumeration elements list.

SETTLING : Analog Settling Time
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : AST3

3 periods of ADCClock

0x1 : AST5

5 periods of ADCClock

0x2 : AST9

9 periods of ADCClock

0x3 : AST17

17 periods of ADCClock

End of enumeration elements list.

ANACH : Analog Change
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NONE

No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels

1 : ALLOWED

Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers

End of enumeration elements list.

TRACKTIM : Tracking Time
bits : 24 - 27 (4 bit)
access : read-write

TRANSFER : Transfer Period
bits : 28 - 29 (2 bit)
access : read-write

USEQ : Use Sequence Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NUM_ORDER

Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index.

1 : REG_ORDER

User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel.

End of enumeration elements list.


EMR

Extended Mode Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EMR EMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPMODE CMPSEL CMPALL TAG

CMPMODE : Comparison Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : LOW

Generates an event when the converted data is lower than the low threshold of the window.

0x1 : HIGH

Generates an event when the converted data is higher than the high threshold of the window.

0x2 : IN

Generates an event when the converted data is in the comparison window.

0x3 : OUT

Generates an event when the converted data is out of the comparison window.

End of enumeration elements list.

CMPSEL : Comparison Selected Channel
bits : 4 - 7 (4 bit)
access : read-write

CMPALL : Compare All Channels
bits : 9 - 9 (1 bit)
access : read-write

TAG : TAG of the ADC_LDCR register
bits : 24 - 24 (1 bit)
access : read-write


CDR[9]

Channel Data Register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[9] CDR[9] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CWR

Compare Window Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CWR CWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOWTHRES HIGHTHRES

LOWTHRES : Low Threshold
bits : 0 - 11 (12 bit)
access : read-write

HIGHTHRES : High Threshold
bits : 16 - 27 (12 bit)
access : read-write


CGR

Channel Gain Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGR CGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GAIN0 GAIN1 GAIN2 GAIN3 GAIN4 GAIN5 GAIN6 GAIN7 GAIN8 GAIN9 GAIN10 GAIN11 GAIN12 GAIN13 GAIN14 GAIN15

GAIN0 : Gain for Channel 0
bits : 0 - 1 (2 bit)
access : read-write

GAIN1 : Gain for Channel 1
bits : 2 - 3 (2 bit)
access : read-write

GAIN2 : Gain for Channel 2
bits : 4 - 5 (2 bit)
access : read-write

GAIN3 : Gain for Channel 3
bits : 6 - 7 (2 bit)
access : read-write

GAIN4 : Gain for Channel 4
bits : 8 - 9 (2 bit)
access : read-write

GAIN5 : Gain for Channel 5
bits : 10 - 11 (2 bit)
access : read-write

GAIN6 : Gain for Channel 6
bits : 12 - 13 (2 bit)
access : read-write

GAIN7 : Gain for Channel 7
bits : 14 - 15 (2 bit)
access : read-write

GAIN8 : Gain for Channel 8
bits : 16 - 17 (2 bit)
access : read-write

GAIN9 : Gain for Channel 9
bits : 18 - 19 (2 bit)
access : read-write

GAIN10 : Gain for Channel 10
bits : 20 - 21 (2 bit)
access : read-write

GAIN11 : Gain for Channel 11
bits : 22 - 23 (2 bit)
access : read-write

GAIN12 : Gain for Channel 12
bits : 24 - 25 (2 bit)
access : read-write

GAIN13 : Gain for Channel 13
bits : 26 - 27 (2 bit)
access : read-write

GAIN14 : Gain for Channel 14
bits : 28 - 29 (2 bit)
access : read-write

GAIN15 : Gain for Channel 15
bits : 30 - 31 (2 bit)
access : read-write


CDR[10]

Channel Data Register
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[10] CDR[10] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


COR

Channel Offset Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COR COR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFF0 OFF1 OFF2 OFF3 OFF4 OFF5 OFF6 OFF7 OFF8 OFF9 OFF10 OFF11 OFF12 OFF13 OFF14 OFF15 DIFF0 DIFF1 DIFF2 DIFF3 DIFF4 DIFF5 DIFF6 DIFF7 DIFF8 DIFF9 DIFF10 DIFF11 DIFF12 DIFF13 DIFF14 DIFF15

OFF0 : Offset for channel 0
bits : 0 - 0 (1 bit)
access : read-write

OFF1 : Offset for channel 1
bits : 1 - 1 (1 bit)
access : read-write

OFF2 : Offset for channel 2
bits : 2 - 2 (1 bit)
access : read-write

OFF3 : Offset for channel 3
bits : 3 - 3 (1 bit)
access : read-write

OFF4 : Offset for channel 4
bits : 4 - 4 (1 bit)
access : read-write

OFF5 : Offset for channel 5
bits : 5 - 5 (1 bit)
access : read-write

OFF6 : Offset for channel 6
bits : 6 - 6 (1 bit)
access : read-write

OFF7 : Offset for channel 7
bits : 7 - 7 (1 bit)
access : read-write

OFF8 : Offset for channel 8
bits : 8 - 8 (1 bit)
access : read-write

OFF9 : Offset for channel 9
bits : 9 - 9 (1 bit)
access : read-write

OFF10 : Offset for channel 10
bits : 10 - 10 (1 bit)
access : read-write

OFF11 : Offset for channel 11
bits : 11 - 11 (1 bit)
access : read-write

OFF12 : Offset for channel 12
bits : 12 - 12 (1 bit)
access : read-write

OFF13 : Offset for channel 13
bits : 13 - 13 (1 bit)
access : read-write

OFF14 : Offset for channel 14
bits : 14 - 14 (1 bit)
access : read-write

OFF15 : Offset for channel 15
bits : 15 - 15 (1 bit)
access : read-write

DIFF0 : Differential inputs for channel 0
bits : 16 - 16 (1 bit)
access : read-write

DIFF1 : Differential inputs for channel 1
bits : 17 - 17 (1 bit)
access : read-write

DIFF2 : Differential inputs for channel 2
bits : 18 - 18 (1 bit)
access : read-write

DIFF3 : Differential inputs for channel 3
bits : 19 - 19 (1 bit)
access : read-write

DIFF4 : Differential inputs for channel 4
bits : 20 - 20 (1 bit)
access : read-write

DIFF5 : Differential inputs for channel 5
bits : 21 - 21 (1 bit)
access : read-write

DIFF6 : Differential inputs for channel 6
bits : 22 - 22 (1 bit)
access : read-write

DIFF7 : Differential inputs for channel 7
bits : 23 - 23 (1 bit)
access : read-write

DIFF8 : Differential inputs for channel 8
bits : 24 - 24 (1 bit)
access : read-write

DIFF9 : Differential inputs for channel 9
bits : 25 - 25 (1 bit)
access : read-write

DIFF10 : Differential inputs for channel 10
bits : 26 - 26 (1 bit)
access : read-write

DIFF11 : Differential inputs for channel 11
bits : 27 - 27 (1 bit)
access : read-write

DIFF12 : Differential inputs for channel 12
bits : 28 - 28 (1 bit)
access : read-write

DIFF13 : Differential inputs for channel 13
bits : 29 - 29 (1 bit)
access : read-write

DIFF14 : Differential inputs for channel 14
bits : 30 - 30 (1 bit)
access : read-write

DIFF15 : Differential inputs for channel 15
bits : 31 - 31 (1 bit)
access : read-write


CDR0

Channel Data Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR0 CDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR[11]

Channel Data Register
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[11] CDR[11] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR1

Channel Data Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR1 CDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR2

Channel Data Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR2 CDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR[12]

Channel Data Register
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[12] CDR[12] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR3

Channel Data Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR3 CDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR4

Channel Data Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR4 CDR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR[13]

Channel Data Register
address_offset : 0x61C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[13] CDR[13] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR5

Channel Data Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR5 CDR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR6

Channel Data Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR6 CDR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR[14]

Channel Data Register
address_offset : 0x6A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[14] CDR[14] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR7

Channel Data Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR7 CDR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR8

Channel Data Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR8 CDR8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR9

Channel Data Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR9 CDR9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR10

Channel Data Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR10 CDR10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR11

Channel Data Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR11 CDR11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


SEQR0

Channel Sequence Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SEQR0 SEQR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CDR12

Channel Data Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR12 CDR12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR13

Channel Data Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR13 CDR13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR14

Channel Data Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR14 CDR14 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


ACR

Analog Control Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACR ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSON IBCTL

TSON : Temperature Sensor On
bits : 4 - 4 (1 bit)
access : read-write

IBCTL : ADC Bias Current Control
bits : 8 - 9 (2 bit)
access : read-write


CDR[0]

Channel Data Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[0] CDR[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


SEQR1

Channel Sequence Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SEQR1 SEQR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WPMR

Write Protect Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protect KEY
bits : 8 - 31 (24 bit)
access : read-write

Enumeration:

0x414443 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0

End of enumeration elements list.


WPSR

Write Protect Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protect Violation Status
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protect Violation Source
bits : 8 - 23 (16 bit)
access : read-only


CDR[1]

Channel Data Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[1] CDR[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only



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