\n
address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PROCRST : Processor Reset
bits : 0 - 0 (1 bit)
access : write-only
PERRST : Peripheral Reset
bits : 2 - 2 (1 bit)
access : write-only
EXTRST : External Reset
bits : 3 - 3 (1 bit)
access : write-only
KEY : System Reset Key
bits : 24 - 31 (8 bit)
access : write-only
Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
URSTS : User Reset Status
bits : 0 - 0 (1 bit)
access : read-only
RSTTYP : Reset Type
bits : 8 - 10 (3 bit)
access : read-only
NRSTL : NRST Pin Level
bits : 16 - 16 (1 bit)
access : read-only
SRCMP : Software Reset Command in Progress
bits : 17 - 17 (1 bit)
access : read-only
Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
URSTEN : User Reset Enable
bits : 0 - 0 (1 bit)
access : read-write
URSTIEN : User Reset Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
ERSTL : External Reset Length
bits : 8 - 11 (4 bit)
access : read-write
KEY : Password
bits : 24 - 31 (8 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.