\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Frame Number Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRM_NUM : Frame Number as Defined in the Packet Field Formats
bits : 0 - 10 (11 bit)
access : read-only
FRM_ERR : Frame Error
bits : 16 - 16 (1 bit)
access : read-only
FRM_OK : Frame OK
bits : 17 - 17 (1 bit)
access : read-only
Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EP0INT : Enable Endpoint 0 Interrupt
bits : 0 - 0 (1 bit)
access : write-only
EP1INT : Enable Endpoint 1 Interrupt
bits : 1 - 1 (1 bit)
access : write-only
EP2INT : Enable Endpoint 2Interrupt
bits : 2 - 2 (1 bit)
access : write-only
EP3INT : Enable Endpoint 3 Interrupt
bits : 3 - 3 (1 bit)
access : write-only
EP4INT : Enable Endpoint 4 Interrupt
bits : 4 - 4 (1 bit)
access : write-only
EP5INT : Enable Endpoint 5 Interrupt
bits : 5 - 5 (1 bit)
access : write-only
EP6INT : Enable Endpoint 6 Interrupt
bits : 6 - 6 (1 bit)
access : write-only
EP7INT : Enable Endpoint 7 Interrupt
bits : 7 - 7 (1 bit)
access : write-only
RXSUSP : Enable UDP Suspend Interrupt
bits : 8 - 8 (1 bit)
access : write-only
RXRSM : Enable UDP Resume Interrupt
bits : 9 - 9 (1 bit)
access : write-only
EXTRSM :
bits : 10 - 10 (1 bit)
access : write-only
SOFINT : Enable Start Of Frame Interrupt
bits : 11 - 11 (1 bit)
access : write-only
WAKEUP : Enable UDP bus Wakeup Interrupt
bits : 13 - 13 (1 bit)
access : write-only
Endpoint Control and Status Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
STALLSENT : Stall Sent
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x2 : BULK_OUT
Bulk OUT
0x3 : INT_OUT
Interrupt OUT
0x5 : ISO_IN
Isochronous IN
0x6 : BULK_IN
Bulk IN
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Interrupt Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EP0INT : Disable Endpoint 0 Interrupt
bits : 0 - 0 (1 bit)
access : write-only
EP1INT : Disable Endpoint 1 Interrupt
bits : 1 - 1 (1 bit)
access : write-only
EP2INT : Disable Endpoint 2 Interrupt
bits : 2 - 2 (1 bit)
access : write-only
EP3INT : Disable Endpoint 3 Interrupt
bits : 3 - 3 (1 bit)
access : write-only
EP4INT : Disable Endpoint 4 Interrupt
bits : 4 - 4 (1 bit)
access : write-only
EP5INT : Disable Endpoint 5 Interrupt
bits : 5 - 5 (1 bit)
access : write-only
EP6INT : Disable Endpoint 6 Interrupt
bits : 6 - 6 (1 bit)
access : write-only
EP7INT : Disable Endpoint 7 Interrupt
bits : 7 - 7 (1 bit)
access : write-only
RXSUSP : Disable UDP Suspend Interrupt
bits : 8 - 8 (1 bit)
access : write-only
RXRSM : Disable UDP Resume Interrupt
bits : 9 - 9 (1 bit)
access : write-only
EXTRSM :
bits : 10 - 10 (1 bit)
access : write-only
SOFINT : Disable Start Of Frame Interrupt
bits : 11 - 11 (1 bit)
access : write-only
WAKEUP : Disable USB Bus Interrupt
bits : 13 - 13 (1 bit)
access : write-only
Endpoint Control and Status Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
STALLSENT : Stall Sent
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x2 : BULK_OUT
Bulk OUT
0x3 : INT_OUT
Interrupt OUT
0x5 : ISO_IN
Isochronous IN
0x6 : BULK_IN
Bulk IN
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Endpoint FIFO Data Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO_DATA : FIFO Data Value
bits : 0 - 7 (8 bit)
access : read-write
Interrupt Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EP0INT : Mask Endpoint 0 Interrupt
bits : 0 - 0 (1 bit)
access : read-only
EP1INT : Mask Endpoint 1 Interrupt
bits : 1 - 1 (1 bit)
access : read-only
EP2INT : Mask Endpoint 2 Interrupt
bits : 2 - 2 (1 bit)
access : read-only
EP3INT : Mask Endpoint 3 Interrupt
bits : 3 - 3 (1 bit)
access : read-only
EP4INT : Mask Endpoint 4 Interrupt
bits : 4 - 4 (1 bit)
access : read-only
EP5INT : Mask Endpoint 5 Interrupt
bits : 5 - 5 (1 bit)
access : read-only
EP6INT : Mask Endpoint 6 Interrupt
bits : 6 - 6 (1 bit)
access : read-only
EP7INT : Mask Endpoint 7 Interrupt
bits : 7 - 7 (1 bit)
access : read-only
RXSUSP : Mask UDP Suspend Interrupt
bits : 8 - 8 (1 bit)
access : read-only
RXRSM : Mask UDP Resume Interrupt.
bits : 9 - 9 (1 bit)
access : read-only
EXTRSM :
bits : 10 - 10 (1 bit)
access : read-only
SOFINT : Mask Start Of Frame Interrupt
bits : 11 - 11 (1 bit)
access : read-only
BIT12 : UDP_IMR Bit 12
bits : 12 - 12 (1 bit)
access : read-only
WAKEUP : USB Bus WAKEUP Interrupt
bits : 13 - 13 (1 bit)
access : read-only
Endpoint Control and Status Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
STALLSENT : Stall Sent
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x2 : BULK_OUT
Bulk OUT
0x3 : INT_OUT
Interrupt OUT
0x5 : ISO_IN
Isochronous IN
0x6 : BULK_IN
Bulk IN
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Endpoint FIFO Data Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO_DATA : FIFO Data Value
bits : 0 - 7 (8 bit)
access : read-write
Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EP0INT : Endpoint 0 Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only
EP1INT : Endpoint 1 Interrupt Status
bits : 1 - 1 (1 bit)
access : read-only
EP2INT : Endpoint 2 Interrupt Status
bits : 2 - 2 (1 bit)
access : read-only
EP3INT : Endpoint 3 Interrupt Status
bits : 3 - 3 (1 bit)
access : read-only
EP4INT : Endpoint 4 Interrupt Status
bits : 4 - 4 (1 bit)
access : read-only
EP5INT : Endpoint 5 Interrupt Status
bits : 5 - 5 (1 bit)
access : read-only
EP6INT : Endpoint 6 Interrupt Status
bits : 6 - 6 (1 bit)
access : read-only
EP7INT : Endpoint 7Interrupt Status
bits : 7 - 7 (1 bit)
access : read-only
RXSUSP : UDP Suspend Interrupt Status
bits : 8 - 8 (1 bit)
access : read-only
RXRSM : UDP Resume Interrupt Status
bits : 9 - 9 (1 bit)
access : read-only
EXTRSM :
bits : 10 - 10 (1 bit)
access : read-only
SOFINT : Start of Frame Interrupt Status
bits : 11 - 11 (1 bit)
access : read-only
ENDBUSRES : End of BUS Reset Interrupt Status
bits : 12 - 12 (1 bit)
access : read-only
WAKEUP : UDP Resume Interrupt Status
bits : 13 - 13 (1 bit)
access : read-only
Endpoint Control and Status Register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
STALLSENT : Stall Sent
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x2 : BULK_OUT
Bulk OUT
0x3 : INT_OUT
Interrupt OUT
0x5 : ISO_IN
Isochronous IN
0x6 : BULK_IN
Bulk IN
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Interrupt Clear Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXSUSP : Clear UDP Suspend Interrupt
bits : 8 - 8 (1 bit)
access : write-only
RXRSM : Clear UDP Resume Interrupt
bits : 9 - 9 (1 bit)
access : write-only
EXTRSM :
bits : 10 - 10 (1 bit)
access : write-only
SOFINT : Clear Start Of Frame Interrupt
bits : 11 - 11 (1 bit)
access : write-only
ENDBUSRES : Clear End of Bus Reset Interrupt
bits : 12 - 12 (1 bit)
access : write-only
WAKEUP : Clear Wakeup Interrupt
bits : 13 - 13 (1 bit)
access : write-only
Endpoint FIFO Data Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO_DATA : FIFO Data Value
bits : 0 - 7 (8 bit)
access : read-write
Endpoint Control and Status Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
STALLSENT : Stall Sent
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x2 : BULK_OUT
Bulk OUT
0x3 : INT_OUT
Interrupt OUT
0x5 : ISO_IN
Isochronous IN
0x6 : BULK_IN
Bulk IN
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Endpoint FIFO Data Register
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO_DATA : FIFO Data Value
bits : 0 - 7 (8 bit)
access : read-write
Reset Endpoint Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP0 : Reset Endpoint 0
bits : 0 - 0 (1 bit)
access : read-write
EP1 : Reset Endpoint 1
bits : 1 - 1 (1 bit)
access : read-write
EP2 : Reset Endpoint 2
bits : 2 - 2 (1 bit)
access : read-write
EP3 : Reset Endpoint 3
bits : 3 - 3 (1 bit)
access : read-write
EP4 : Reset Endpoint 4
bits : 4 - 4 (1 bit)
access : read-write
EP5 : Reset Endpoint 5
bits : 5 - 5 (1 bit)
access : read-write
EP6 : Reset Endpoint 6
bits : 6 - 6 (1 bit)
access : read-write
EP7 : Reset Endpoint 7
bits : 7 - 7 (1 bit)
access : read-write
Endpoint FIFO Data Register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO_DATA : FIFO Data Value
bits : 0 - 7 (8 bit)
access : read-write
Endpoint Control and Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
ISOERROR : A CRC error has been detected in an isochronous transfer
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x5 : ISO_IN
Isochronous IN
0x2 : BULK_OUT
Bulk OUT
0x6 : BULK_IN
Bulk IN
0x3 : INT_OUT
Interrupt OUT
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Endpoint Control and Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
STALLSENT : Stall Sent
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x2 : BULK_OUT
Bulk OUT
0x3 : INT_OUT
Interrupt OUT
0x5 : ISO_IN
Isochronous IN
0x6 : BULK_IN
Bulk IN
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Endpoint Control and Status Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
STALLSENT : Stall Sent
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x2 : BULK_OUT
Bulk OUT
0x3 : INT_OUT
Interrupt OUT
0x5 : ISO_IN
Isochronous IN
0x6 : BULK_IN
Bulk IN
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Endpoint FIFO Data Register
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO_DATA : FIFO Data Value
bits : 0 - 7 (8 bit)
access : read-write
Endpoint Control and Status Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
STALLSENT : Stall Sent
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x2 : BULK_OUT
Bulk OUT
0x3 : INT_OUT
Interrupt OUT
0x5 : ISO_IN
Isochronous IN
0x6 : BULK_IN
Bulk IN
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Endpoint Control and Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
STALLSENT : Stall Sent
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x2 : BULK_OUT
Bulk OUT
0x3 : INT_OUT
Interrupt OUT
0x5 : ISO_IN
Isochronous IN
0x6 : BULK_IN
Bulk IN
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Global State Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FADDEN : Function Address Enable
bits : 0 - 0 (1 bit)
access : read-write
CONFG : Configured
bits : 1 - 1 (1 bit)
access : read-write
ESR : Enable Send Resume
bits : 2 - 2 (1 bit)
access : read-write
RSMINPR :
bits : 3 - 3 (1 bit)
access : read-write
RMWUPE : Remote Wake Up Enable
bits : 4 - 4 (1 bit)
access : read-write
Endpoint Control and Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
STALLSENT : Stall Sent
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x2 : BULK_OUT
Bulk OUT
0x3 : INT_OUT
Interrupt OUT
0x5 : ISO_IN
Isochronous IN
0x6 : BULK_IN
Bulk IN
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Endpoint Control and Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
STALLSENT : Stall Sent
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x2 : BULK_OUT
Bulk OUT
0x3 : INT_OUT
Interrupt OUT
0x5 : ISO_IN
Isochronous IN
0x6 : BULK_IN
Bulk IN
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Endpoint Control and Status Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
STALLSENT : Stall Sent
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x2 : BULK_OUT
Bulk OUT
0x3 : INT_OUT
Interrupt OUT
0x5 : ISO_IN
Isochronous IN
0x6 : BULK_IN
Bulk IN
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Endpoint Control and Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
STALLSENT : Stall Sent
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x2 : BULK_OUT
Bulk OUT
0x3 : INT_OUT
Interrupt OUT
0x5 : ISO_IN
Isochronous IN
0x6 : BULK_IN
Bulk IN
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Endpoint FIFO Data Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FIFO_DATA : FIFO Data Value
bits : 0 - 7 (8 bit)
access : read-write
Endpoint FIFO Data Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FIFO_DATA : FIFO Data Value
bits : 0 - 7 (8 bit)
access : read-write
Endpoint FIFO Data Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FIFO_DATA : FIFO Data Value
bits : 0 - 7 (8 bit)
access : read-write
Endpoint FIFO Data Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FIFO_DATA : FIFO Data Value
bits : 0 - 7 (8 bit)
access : read-write
Endpoint Control and Status Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
STALLSENT : Stall Sent
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x2 : BULK_OUT
Bulk OUT
0x3 : INT_OUT
Interrupt OUT
0x5 : ISO_IN
Isochronous IN
0x6 : BULK_IN
Bulk IN
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Endpoint FIFO Data Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FIFO_DATA : FIFO Data Value
bits : 0 - 7 (8 bit)
access : read-write
Endpoint FIFO Data Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FIFO_DATA : FIFO Data Value
bits : 0 - 7 (8 bit)
access : read-write
Endpoint FIFO Data Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FIFO_DATA : FIFO Data Value
bits : 0 - 7 (8 bit)
access : read-write
Endpoint FIFO Data Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FIFO_DATA : FIFO Data Value
bits : 0 - 7 (8 bit)
access : read-write
Transceiver Control Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXVDIS : Transceiver Disable
bits : 8 - 8 (1 bit)
access : read-write
PUON : Pull-up On
bits : 9 - 9 (1 bit)
access : read-write
Function Address Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FADD : Function Address Value
bits : 0 - 6 (7 bit)
access : read-write
FEN : Function Enable
bits : 8 - 8 (1 bit)
access : read-write
Endpoint Control and Status Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
STALLSENT : Stall Sent
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x2 : BULK_OUT
Bulk OUT
0x3 : INT_OUT
Interrupt OUT
0x5 : ISO_IN
Isochronous IN
0x6 : BULK_IN
Bulk IN
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Endpoint FIFO Data Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO_DATA : FIFO Data Value
bits : 0 - 7 (8 bit)
access : read-write
Endpoint Control and Status Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCOMP : Generates an IN Packet with Data Previously Written in the DPR
bits : 0 - 0 (1 bit)
access : read-write
RX_DATA_BK0 : Receive Data Bank 0
bits : 1 - 1 (1 bit)
access : read-write
RXSETUP : Received Setup
bits : 2 - 2 (1 bit)
access : read-write
STALLSENT : Stall Sent
bits : 3 - 3 (1 bit)
access : read-write
TXPKTRDY : Transmit Packet Ready
bits : 4 - 4 (1 bit)
access : read-write
FORCESTALL : Force Stall (used by Control, Bulk and Isochronous Endpoints)
bits : 5 - 5 (1 bit)
access : read-write
RX_DATA_BK1 : Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
bits : 6 - 6 (1 bit)
access : read-write
DIR : Transfer Direction (only available for control endpoints)
bits : 7 - 7 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO_OUT
Isochronous OUT
0x2 : BULK_OUT
Bulk OUT
0x3 : INT_OUT
Interrupt OUT
0x5 : ISO_IN
Isochronous IN
0x6 : BULK_IN
Bulk IN
0x7 : INT_IN
Interrupt IN
End of enumeration elements list.
DTGLE : Data Toggle
bits : 11 - 11 (1 bit)
access : read-write
EPEDS : Endpoint Enable Disable
bits : 15 - 15 (1 bit)
access : read-write
RXBYTECNT : Number of Bytes Available in the FIFO
bits : 16 - 26 (11 bit)
access : read-write
Endpoint FIFO Data Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO_DATA : FIFO Data Value
bits : 0 - 7 (8 bit)
access : read-write
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