\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
CMU Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKOUTSEL0 : Clock Output Select 0
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
Disabled
0x00000001 : ULFRCO
ULFRCO (directly from oscillator)
0x00000002 : LFRCO
LFRCO (directly from oscillator)
0x00000003 : LFXO
LFXO (directly from oscillator)
0x00000006 : HFXO
HFXO (directly from oscillator)
0x00000007 : HFEXPCLK
HFEXPCLK
0x00000009 : ULFRCOQ
ULFRCO (qualified)
0x0000000A : LFRCOQ
LFRCO (qualified)
0x0000000B : LFXOQ
LFXO (qualified)
0x0000000C : HFRCOQ
HFRCO (qualified)
0x0000000D : AUXHFRCOQ
AUXHFRCO (qualified)
0x0000000E : HFXOQ
HFXO (qualified)
0x0000000F : HFSRCCLK
HFSRCCLK
End of enumeration elements list.
CLKOUTSEL1 : Clock Output Select 1
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
Disabled
0x00000001 : ULFRCO
ULFRCO (directly from oscillator)
0x00000002 : LFRCO
LFRCO (directly from oscillator)
0x00000003 : LFXO
LFXO (directly from oscillator)
0x00000006 : HFXO
HFXO (directly from oscillator)
0x00000007 : HFEXPCLK
HFEXPCLK
0x00000009 : ULFRCOQ
ULFRCO (qualified)
0x0000000A : LFRCOQ
LFRCO (qualified)
0x0000000B : LFXOQ
LFXO (qualified)
0x0000000C : HFRCOQ
HFRCO (qualified)
0x0000000D : AUXHFRCOQ
AUXHFRCO (qualified)
0x0000000E : HFXOQ
HFXO (qualified)
0x0000000F : HFSRCCLK
HFSRCCLK
End of enumeration elements list.
WSHFLE : Wait State for High-Frequency LE Interface
bits : 16 - 16 (1 bit)
access : read-write
HFPERCLKEN : HFPERCLK Enable
bits : 20 - 20 (1 bit)
access : read-write
HFRCO Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNING : HFRCO Tuning Value
bits : 0 - 6 (7 bit)
access : read-write
FINETUNING : HFRCO Fine Tuning Value
bits : 8 - 13 (6 bit)
access : read-write
FREQRANGE : HFRCO Frequency Range
bits : 16 - 20 (5 bit)
access : read-write
CMPBIAS : HFRCO Comparator Bias Current
bits : 21 - 23 (3 bit)
access : read-write
LDOHP : HFRCO LDO High Power Mode
bits : 24 - 24 (1 bit)
access : read-write
CLKDIV : Locally Divide HFRCO Clock Output
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0x00000000 : DIV1
Divide by 1.
0x00000001 : DIV2
Divide by 2.
0x00000002 : DIV4
Divide by 4.
End of enumeration elements list.
FINETUNINGEN : Enable Reference for Fine Tuning
bits : 27 - 27 (1 bit)
access : read-write
VREFTC : HFRCO Temperature Coefficient Trim on Comparator Reference
bits : 28 - 31 (4 bit)
access : read-write
High Frequency Clock Prescaler Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : HFCLK Prescaler
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0x00000000 : NODIVISION
None
End of enumeration elements list.
HFCLKLEPRESC : HFCLKLE Prescaler
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x00000000 : DIV2
HFCLKLE is HFBUSCLKLE divided by 2.
0x00000001 : DIV4
HFCLKLE is HFBUSCLKLE divided by 4.
End of enumeration elements list.
High Frequency Core Clock Prescaler Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : HFCORECLK Prescaler
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0x00000000 : NODIVISION
None
End of enumeration elements list.
High Frequency Peripheral Clock Prescaler Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : HFPERCLK Prescaler
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0x00000000 : NODIVISION
None
End of enumeration elements list.
High Frequency Export Clock Prescaler Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : HFEXPCLK Prescaler
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0x00000000 : NODIVISION
None
End of enumeration elements list.
Low Frequency a Prescaler Register 0 (Async Reg)
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LETIMER0 : Low Energy Timer 0 Prescaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x00000000 : DIV1
LFACLKLETIMER0 = LFACLK
0x00000001 : DIV2
LFACLKLETIMER0 = LFACLK/2
0x00000002 : DIV4
LFACLKLETIMER0 = LFACLK/4
0x00000003 : DIV8
LFACLKLETIMER0 = LFACLK/8
0x00000004 : DIV16
LFACLKLETIMER0 = LFACLK/16
0x00000005 : DIV32
LFACLKLETIMER0 = LFACLK/32
0x00000006 : DIV64
LFACLKLETIMER0 = LFACLK/64
0x00000007 : DIV128
LFACLKLETIMER0 = LFACLK/128
0x00000008 : DIV256
LFACLKLETIMER0 = LFACLK/256
0x00000009 : DIV512
LFACLKLETIMER0 = LFACLK/512
0x0000000A : DIV1024
LFACLKLETIMER0 = LFACLK/1024
0x0000000B : DIV2048
LFACLKLETIMER0 = LFACLK/2048
0x0000000C : DIV4096
LFACLKLETIMER0 = LFACLK/4096
0x0000000D : DIV8192
LFACLKLETIMER0 = LFACLK/8192
0x0000000E : DIV16384
LFACLKLETIMER0 = LFACLK/16384
0x0000000F : DIV32768
LFACLKLETIMER0 = LFACLK/32768
End of enumeration elements list.
Low Frequency B Prescaler Register 0 (Async Reg)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEUART0 : Low Energy UART 0 Prescaler
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x00000000 : DIV1
LFBCLKLEUART0 = LFBCLK
0x00000001 : DIV2
LFBCLKLEUART0 = LFBCLK/2
0x00000002 : DIV4
LFBCLKLEUART0 = LFBCLK/4
0x00000003 : DIV8
LFBCLKLEUART0 = LFBCLK/8
End of enumeration elements list.
Low Frequency E Prescaler Register 0 (Async Reg)
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCC : Real-Time Counter and Calendar Prescaler
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
0x00000000 : DIV1
LFECLKRTCC = LFECLK
End of enumeration elements list.
Synchronization Busy Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LFACLKEN0 : Low Frequency a Clock Enable 0 Busy
bits : 0 - 0 (1 bit)
access : read-only
LFAPRESC0 : Low Frequency a Prescaler 0 Busy
bits : 2 - 2 (1 bit)
access : read-only
LFBCLKEN0 : Low Frequency B Clock Enable 0 Busy
bits : 4 - 4 (1 bit)
access : read-only
LFBPRESC0 : Low Frequency B Prescaler 0 Busy
bits : 6 - 6 (1 bit)
access : read-only
LFECLKEN0 : Low Frequency E Clock Enable 0 Busy
bits : 16 - 16 (1 bit)
access : read-only
LFEPRESC0 : Low Frequency E Prescaler 0 Busy
bits : 18 - 18 (1 bit)
access : read-only
HFRCOBSY : HFRCO Busy
bits : 24 - 24 (1 bit)
access : read-only
AUXHFRCOBSY : AUXHFRCO Busy
bits : 25 - 25 (1 bit)
access : read-only
LFRCOBSY : LFRCO Busy
bits : 26 - 26 (1 bit)
access : read-only
LFRCOVREFBSY : LFRCO VREF Busy
bits : 27 - 27 (1 bit)
access : read-only
HFXOBSY : HFXO Busy
bits : 28 - 28 (1 bit)
access : read-only
LFXOBSY : LFXO Busy
bits : 29 - 29 (1 bit)
access : read-only
Freeze Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGFREEZE : Register Update Freeze
bits : 0 - 0 (1 bit)
access : read-write
PCNT Control Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCNT0CLKEN : PCNT0 Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
PCNT0CLKSEL : PCNT0 Clock Select
bits : 1 - 1 (1 bit)
access : read-write
ADC Control Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0CLKSEL : ADC0 Clock Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
ADC0 is not clocked
0x00000001 : AUXHFRCO
AUXHFRCO is clocking ADC0
0x00000002 : HFXO
HFXO is clocking ADC0
0x00000003 : HFSRCCLK
HFSRCCLK is clocking ADC0
End of enumeration elements list.
ADC0CLKINV : Invert Clock Selected By ADC0CLKSEL
bits : 8 - 8 (1 bit)
access : read-write
I/O Routing Pin Enable Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKOUT0PEN : CLKOUT0 Pin Enable
bits : 0 - 0 (1 bit)
access : read-write
CLKOUT1PEN : CLKOUT1 Pin Enable
bits : 1 - 1 (1 bit)
access : read-write
I/O Routing Location Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKOUT0LOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
0x00000007 : LOC7
Location 7
End of enumeration elements list.
CLKOUT1LOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
0x00000007 : LOC7
Location 7
End of enumeration elements list.
AUXHFRCO Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNING : AUXHFRCO Tuning Value
bits : 0 - 6 (7 bit)
access : read-write
FINETUNING : AUXHFRCO Fine Tuning Value
bits : 8 - 13 (6 bit)
access : read-write
FREQRANGE : AUXHFRCO Frequency Range
bits : 16 - 20 (5 bit)
access : read-write
CMPBIAS : AUXHFRCO Comparator Bias Current
bits : 21 - 23 (3 bit)
access : read-write
LDOHP : AUXHFRCO LDO High Power Mode
bits : 24 - 24 (1 bit)
access : read-write
CLKDIV : Locally Divide AUXHFRCO Clock Output
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0x00000000 : DIV1
Divide by 1.
0x00000001 : DIV2
Divide by 2.
0x00000002 : DIV4
Divide by 4.
End of enumeration elements list.
FINETUNINGEN : Enable Reference for Fine Tuning
bits : 27 - 27 (1 bit)
access : read-write
VREFTC : AUXHFRCO Temperature Coefficient Trim on Comparator Reference
bits : 28 - 31 (4 bit)
access : read-write
Configuration Lock Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKKEY : Configuration Lock Key
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0x00000000 : UNLOCKED
None
0x00000001 : LOCKED
None
End of enumeration elements list.
LFRCO Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNING : LFRCO Tuning Value
bits : 0 - 8 (9 bit)
access : read-write
ENVREF : Enable Duty Cycling of Vref
bits : 16 - 16 (1 bit)
access : read-write
ENCHOP : Enable Comparator Chopping
bits : 17 - 17 (1 bit)
access : read-write
ENDEM : Enable Dynamic Element Matching
bits : 18 - 18 (1 bit)
access : read-write
TIMEOUT : LFRCO Timeout
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x00000000 : 2CYCLES
Timeout period of 2 cycles
0x00000001 : 16CYCLES
Timeout period of 16 cycles
0x00000002 : 32CYCLES
Timeout period of 32 cycles
End of enumeration elements list.
GMCCURTUNE : Tuning of Gmc Current
bits : 28 - 31 (4 bit)
access : read-write
HFXO Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : HFXO Mode
bits : 0 - 0 (1 bit)
access : read-write
PEAKDETSHUNTOPTMODE : HFXO Automatic Peak Detection and Shunt Current Optimization Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x00000000 : AUTOCMD
Automatic control of HFXO peak detection and shunt optimization sequences. CMU_CMD HFXOPEAKDETSTART and HFXOSHUNTOPTSTART can also be used.
0x00000001 : CMD
CMU_CMD HFXOPEAKDETSTART and HFXOSHUNTOPTSTART can be used to trigger peak detection and shunt optimization sequences.
0x00000002 : MANUAL
CMU_HFXOSTEADYSTATECTRL IBTRIMXOCORE, REGISH, REGSELILOW, and PEAKDETEN are under full software control and are allowed to be changed once HFXO is ready.
End of enumeration elements list.
LOWPOWER : Low Power Mode Control
bits : 8 - 8 (1 bit)
access : read-write
XTI2GND : Clamp HFXTAL_N Pin to Ground When HFXO Oscillator is Off
bits : 9 - 9 (1 bit)
access : read-write
XTO2GND : Clamp HFXTAL_P Pin to Ground When HFXO Oscillator is Off
bits : 10 - 10 (1 bit)
access : read-write
LFTIMEOUT : HFXO Low Frequency Timeout
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x00000000 : 0CYCLES
Timeout period of 0 cycles (disabled)
0x00000001 : 2CYCLES
Timeout period of 2 cycles
0x00000002 : 4CYCLES
Timeout period of 4 cycles
0x00000003 : 16CYCLES
Timeout period of 16 cycles
0x00000004 : 32CYCLES
Timeout period of 32 cycles
0x00000005 : 64CYCLES
Timeout period of 64 cycles
0x00000006 : 1KCYCLES
Timeout period of 1024 cycles
0x00000007 : 4KCYCLES
Timeout period of 4096 cycles
End of enumeration elements list.
AUTOSTARTEM0EM1 : Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3
bits : 28 - 28 (1 bit)
access : read-write
AUTOSTARTSELEM0EM1 : Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3
bits : 29 - 29 (1 bit)
access : read-write
HFXO Control 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEAKDETTHR : Sets the Peak Detector amplitude detection threshold levels
bits : 0 - 2 (3 bit)
access : read-write
REGLVL : Reserved for internal use. Do not change.
bits : 4 - 6 (3 bit)
access : read-write
XTIBIASEN : Reserved for internal use. Do not change.
bits : 9 - 9 (1 bit)
access : read-write
HFXO Startup Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IBTRIMXOCORE : Sets the Startup Oscillator Core Bias Current
bits : 0 - 6 (7 bit)
access : read-write
CTUNE : Sets Oscillator Tuning Capacitance
bits : 11 - 19 (9 bit)
access : read-write
RESERVED0 : This Field is Reserved. It Should Be Set to 0x9
bits : 21 - 27 (7 bit)
access : read-write
RESERVED1 : Sets the Regulator Output Current Level (shunt Regulator)
bits : 28 - 31 (4 bit)
access : read-write
HFXO Steady State Control
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IBTRIMXOCORE : Sets the Steady State Oscillator Core Bias Current.
bits : 0 - 6 (7 bit)
access : read-write
REGISH : Sets the Steady State Regulator Output Current Level (shunt Regulator)
bits : 7 - 10 (4 bit)
access : read-write
CTUNE : Sets Oscillator Tuning Capacitance
bits : 11 - 19 (9 bit)
access : read-write
REGSELILOW : Controls Regulator Minimum Shunt Current Detection Relative to Nominal
bits : 24 - 25 (2 bit)
access : read-write
PEAKDETEN : Enables Oscillator Peak Detectors
bits : 26 - 26 (1 bit)
access : read-write
REGISHUPPER : Set Regulator Output Current Level (shunt Regulator). Ish = 120uA + REGISHUPPER X 120uA
bits : 28 - 31 (4 bit)
access : read-write
HFXO Timeout Control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTUPTIMEOUT : Wait Duration in HFXO Startup Enable Wait State
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x00000000 : 2CYCLES
Timeout period of 2 cycles
0x00000001 : 4CYCLES
Timeout period of 4 cycles
0x00000002 : 16CYCLES
Timeout period of 16 cycles
0x00000003 : 32CYCLES
Timeout period of 32 cycles
0x00000004 : 256CYCLES
Timeout period of 256 cycles
0x00000005 : 1KCYCLES
Timeout period of 1024 cycles
0x00000006 : 2KCYCLES
Timeout period of 2048 cycles
0x00000007 : 4KCYCLES
Timeout period of 4096 cycles
0x00000008 : 8KCYCLES
Timeout period of 8192 cycles
0x00000009 : 16KCYCLES
Timeout period of 16384 cycles
0x0000000A : 32KCYCLES
Timeout period of 32768 cycles
End of enumeration elements list.
STEADYTIMEOUT : Wait Duration in HFXO Startup Steady Wait State
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x00000000 : 2CYCLES
Timeout period of 2 cycles
0x00000001 : 4CYCLES
Timeout period of 4 cycles
0x00000002 : 16CYCLES
Timeout period of 16 cycles
0x00000003 : 32CYCLES
Timeout period of 32 cycles
0x00000004 : 256CYCLES
Timeout period of 256 cycles
0x00000005 : 1KCYCLES
Timeout period of 1024 cycles
0x00000006 : 2KCYCLES
Timeout period of 2048 cycles
0x00000007 : 4KCYCLES
Timeout period of 4096 cycles
0x00000008 : 8KCYCLES
Timeout period of 8192 cycles
0x00000009 : 16KCYCLES
Timeout period of 16384 cycles
0x0000000A : 32KCYCLES
Timeout period of 32768 cycles
End of enumeration elements list.
RESERVED2 : Wait Duration in HFXO Warm Startup Steady Wait State
bits : 8 - 11 (4 bit)
access : read-write
PEAKDETTIMEOUT : Wait Duration in HFXO Peak Detection Wait State
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0x00000000 : 2CYCLES
Timeout period of 2 cycles
0x00000001 : 4CYCLES
Timeout period of 4 cycles
0x00000002 : 16CYCLES
Timeout period of 16 cycles
0x00000003 : 32CYCLES
Timeout period of 32 cycles
0x00000004 : 256CYCLES
Timeout period of 256 cycles
0x00000005 : 1KCYCLES
Timeout period of 1024 cycles
0x00000006 : 2KCYCLES
Timeout period of 2048 cycles
0x00000007 : 4KCYCLES
Timeout period of 4096 cycles
0x00000008 : 8KCYCLES
Timeout period of 8192 cycles
0x00000009 : 16KCYCLES
Timeout period of 16384 cycles
0x0000000A : 32KCYCLES
Timeout period of 32768 cycles
End of enumeration elements list.
SHUNTOPTTIMEOUT : Wait Duration in HFXO Shunt Current Optimization Wait State
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x00000000 : 2CYCLES
Timeout period of 2 cycles
0x00000001 : 4CYCLES
Timeout period of 4 cycles
0x00000002 : 16CYCLES
Timeout period of 16 cycles
0x00000003 : 32CYCLES
Timeout period of 32 cycles
0x00000004 : 256CYCLES
Timeout period of 256 cycles
0x00000005 : 1KCYCLES
Timeout period of 1024 cycles
0x00000006 : 2KCYCLES
Timeout period of 2048 cycles
0x00000007 : 4KCYCLES
Timeout period of 4096 cycles
0x00000008 : 8KCYCLES
Timeout period of 8192 cycles
0x00000009 : 16KCYCLES
Timeout period of 16384 cycles
0x0000000A : 32KCYCLES
Timeout period of 32768 cycles
End of enumeration elements list.
LFXO Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNING : LFXO Internal Capacitor Array Tuning Value
bits : 0 - 6 (7 bit)
access : read-write
MODE : LFXO Mode
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x00000000 : XTAL
32768 Hz crystal oscillator
0x00000001 : BUFEXTCLK
An AC coupled buffer is coupled in series with LFXTAL_N pin, suitable for external sinus wave (32768 Hz).
0x00000002 : DIGEXTCLK
Digital external clock on LFXTAL_N pin. Oscillator is effectively bypassed.
End of enumeration elements list.
GAIN : LFXO Startup Gain
bits : 11 - 12 (2 bit)
access : read-write
HIGHAMPL : LFXO High XTAL Oscillation Amplitude Enable
bits : 14 - 14 (1 bit)
access : read-write
AGC : LFXO AGC Enable
bits : 15 - 15 (1 bit)
access : read-write
CUR : LFXO Current Trim
bits : 16 - 17 (2 bit)
access : read-write
BUFCUR : LFXO Buffer Bias Current
bits : 20 - 20 (1 bit)
access : read-write
TIMEOUT : LFXO Timeout
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x00000000 : 2CYCLES
Timeout period of 2 cycles
0x00000001 : 256CYCLES
Timeout period of 256 cycles
0x00000002 : 1KCYCLES
Timeout period of 1024 cycles
0x00000003 : 2KCYCLES
Timeout period of 2048 cycles
0x00000004 : 4KCYCLES
Timeout period of 4096 cycles
0x00000005 : 8KCYCLES
Timeout period of 8192 cycles
0x00000006 : 16KCYCLES
Timeout period of 16384 cycles
0x00000007 : 32KCYCLES
Timeout period of 32768 cycles
End of enumeration elements list.
ULFRCO Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNING : ULFRCO TUNING Value
bits : 0 - 5 (6 bit)
access : read-write
MODE : ULFRCO Mode
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x00000000 : 1KHZ
ULFRCO = 1 kHz
0x00000001 : 2KHZ
ULFRCO = 2 kHz
0x00000002 : 4KHZ
ULFRCO = 4 kHz
0x00000003 : 32KHZ
ULFRCO = 32 kHz
End of enumeration elements list.
RESTRIM : ULFRCO Resistor Trim Value (for Resistor in Bias Circuit NOT for USE as FREQUENCY CALIBRATION)
bits : 16 - 17 (2 bit)
access : read-write
Calibration Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPSEL : Calibration Up-counter Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x00000000 : HFXO
Select HFXO as up-counter
0x00000001 : LFXO
Select LFXO as up-counter
0x00000002 : HFRCO
Select HFRCO as up-counter
0x00000003 : LFRCO
Select LFRCO as up-counter
0x00000004 : AUXHFRCO
Select AUXHFRCO as up-counter
0x00000005 : PRS
Select PRS input selected by PRSUPSEL as up-counter
End of enumeration elements list.
DOWNSEL : Calibration Down-counter Select
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x00000000 : HFCLK
Select HFCLK for down-counter
0x00000001 : HFXO
Select HFXO for down-counter
0x00000002 : LFXO
Select LFXO for down-counter
0x00000003 : HFRCO
Select HFRCO for down-counter
0x00000004 : LFRCO
Select LFRCO for down-counter
0x00000005 : AUXHFRCO
Select AUXHFRCO for down-counter
0x00000006 : PRS
Select PRS input selected by PRSDOWNSEL as down-counter
End of enumeration elements list.
CONT : Continuous Calibration
bits : 8 - 8 (1 bit)
access : read-write
PRSUPSEL : PRS Select for PRS Input When Selected in UPSEL
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x00000000 : PRSCH0
PRS Channel 0 selected as input
0x00000001 : PRSCH1
PRS Channel 1 selected as input
0x00000002 : PRSCH2
PRS Channel 2 selected as input
0x00000003 : PRSCH3
PRS Channel 3 selected as input
0x00000004 : PRSCH4
PRS Channel 4 selected as input
0x00000005 : PRSCH5
PRS Channel 5 selected as input
0x00000006 : PRSCH6
PRS Channel 6 selected as input
0x00000007 : PRSCH7
PRS Channel 7 selected as input
0x00000008 : PRSCH8
PRS Channel 8 selected as input
0x00000009 : PRSCH9
PRS Channel 9 selected as input
0x0000000A : PRSCH10
PRS Channel 10 selected as input
0x0000000B : PRSCH11
PRS Channel 11 selected as input
End of enumeration elements list.
PRSDOWNSEL : PRS Select for PRS Input When Selected in DOWNSEL
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0x00000000 : PRSCH0
PRS Channel 0 selected as input
0x00000001 : PRSCH1
PRS Channel 1 selected as input
0x00000002 : PRSCH2
PRS Channel 2 selected as input
0x00000003 : PRSCH3
PRS Channel 3 selected as input
0x00000004 : PRSCH4
PRS Channel 4 selected as input
0x00000005 : PRSCH5
PRS Channel 5 selected as input
0x00000006 : PRSCH6
PRS Channel 6 selected as input
0x00000007 : PRSCH7
PRS Channel 7 selected as input
0x00000008 : PRSCH8
PRS Channel 8 selected as input
0x00000009 : PRSCH9
PRS Channel 9 selected as input
0x0000000A : PRSCH10
PRS Channel 10 selected as input
0x0000000B : PRSCH11
PRS Channel 11 selected as input
End of enumeration elements list.
Calibration Counter Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALCNT : Calibration Counter
bits : 0 - 19 (20 bit)
access : read-write
Oscillator Enable/Disable Command Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
HFRCOEN : HFRCO Enable
bits : 0 - 0 (1 bit)
access : write-only
HFRCODIS : HFRCO Disable
bits : 1 - 1 (1 bit)
access : write-only
HFXOEN : HFXO Enable
bits : 2 - 2 (1 bit)
access : write-only
HFXODIS : HFXO Disable
bits : 3 - 3 (1 bit)
access : write-only
AUXHFRCOEN : AUXHFRCO Enable
bits : 4 - 4 (1 bit)
access : write-only
AUXHFRCODIS : AUXHFRCO Disable
bits : 5 - 5 (1 bit)
access : write-only
LFRCOEN : LFRCO Enable
bits : 6 - 6 (1 bit)
access : write-only
LFRCODIS : LFRCO Disable
bits : 7 - 7 (1 bit)
access : write-only
LFXOEN : LFXO Enable
bits : 8 - 8 (1 bit)
access : write-only
LFXODIS : LFXO Disable
bits : 9 - 9 (1 bit)
access : write-only
Command Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CALSTART : Calibration Start
bits : 0 - 0 (1 bit)
access : write-only
CALSTOP : Calibration Stop
bits : 1 - 1 (1 bit)
access : write-only
HFXOPEAKDETSTART : HFXO Peak Detection Start
bits : 4 - 4 (1 bit)
access : write-only
HFXOSHUNTOPTSTART : HFXO Shunt Current Optimization Start
bits : 5 - 5 (1 bit)
access : write-only
Debug Trace Clock Select
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG : Debug Trace Clock
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x00000000 : AUXHFRCO
AUXHFRCO is the debug trace clock
0x00000001 : HFCLK
HFCLK is the debug trace clock
End of enumeration elements list.
High Frequency Clock Select Command Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
HF : HFCLK Select
bits : 0 - 2 (3 bit)
access : write-only
Enumeration:
0x00000001 : HFRCO
Select HFRCO as HFCLK
0x00000002 : HFXO
Select HFXO as HFCLK
0x00000003 : LFRCO
Select LFRCO as HFCLK
0x00000004 : LFXO
Select LFXO as HFCLK
End of enumeration elements list.
Low Frequency A Clock Select Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LFA : Clock Select for LFA
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
LFACLK is disabled
0x00000001 : LFRCO
LFRCO selected as LFACLK
0x00000002 : LFXO
LFXO selected as LFACLK
0x00000004 : ULFRCO
ULFRCO selected as LFACLK
End of enumeration elements list.
Low Frequency B Clock Select Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LFB : Clock Select for LFB
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
LFBCLK is disabled
0x00000001 : LFRCO
LFRCO selected as LFBCLK
0x00000002 : LFXO
LFXO selected as LFBCLK
0x00000003 : HFCLKLE
HFCLK divided by two/four is selected as LFBCLK
0x00000004 : ULFRCO
ULFRCO selected as LFBCLK
End of enumeration elements list.
Low Frequency E Clock Select Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LFE : Clock Select for LFE
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
LFECLK is disabled
0x00000001 : LFRCO
LFRCO selected as LFECLK
0x00000002 : LFXO
LFXO selected as LFECLK
0x00000004 : ULFRCO
ULFRCO selected as LFECLK
End of enumeration elements list.
Status Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HFRCOENS : HFRCO Enable Status
bits : 0 - 0 (1 bit)
access : read-only
HFRCORDY : HFRCO Ready
bits : 1 - 1 (1 bit)
access : read-only
HFXOENS : HFXO Enable Status
bits : 2 - 2 (1 bit)
access : read-only
HFXORDY : HFXO Ready
bits : 3 - 3 (1 bit)
access : read-only
AUXHFRCOENS : AUXHFRCO Enable Status
bits : 4 - 4 (1 bit)
access : read-only
AUXHFRCORDY : AUXHFRCO Ready
bits : 5 - 5 (1 bit)
access : read-only
LFRCOENS : LFRCO Enable Status
bits : 6 - 6 (1 bit)
access : read-only
LFRCORDY : LFRCO Ready
bits : 7 - 7 (1 bit)
access : read-only
LFXOENS : LFXO Enable Status
bits : 8 - 8 (1 bit)
access : read-only
LFXORDY : LFXO Ready
bits : 9 - 9 (1 bit)
access : read-only
CALRDY : Calibration Ready
bits : 16 - 16 (1 bit)
access : read-only
HFXOREQ : HFXO is Required By Hardware
bits : 21 - 21 (1 bit)
access : read-only
HFXOPEAKDETRDY : HFXO Peak Detection Ready
bits : 22 - 22 (1 bit)
access : read-only
HFXOSHUNTOPTRDY : HFXO Shunt Current Optimization Ready
bits : 23 - 23 (1 bit)
access : read-only
HFXOAMPHIGH : HFXO Oscillation Amplitude is Too High
bits : 24 - 24 (1 bit)
access : read-only
HFXOAMPLOW : HFXO Amplitude Tuning Value Too Low
bits : 25 - 25 (1 bit)
access : read-only
HFXOREGILOW : HFXO Regulator Shunt Current Too Low
bits : 26 - 26 (1 bit)
access : read-only
HFCLK Status Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SELECTED : HFCLK Selected
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0x00000001 : HFRCO
HFRCO is selected as HFCLK clock source
0x00000002 : HFXO
HFXO is selected as HFCLK clock source
0x00000003 : LFRCO
LFRCO is selected as HFCLK clock source
0x00000004 : LFXO
LFXO is selected as HFCLK clock source
End of enumeration elements list.
HFXO Trim Status
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IBTRIMXOCORE : Value of IBTRIMXOCORE Found By Automatic HFXO Peak Detection Algorithm
bits : 0 - 6 (7 bit)
access : read-only
REGISH : Value of REGISH Found By Automatic HFXO Shunt Current Optimization Algorithm
bits : 7 - 10 (4 bit)
access : read-only
Interrupt Flag Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HFRCORDY : HFRCO Ready Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only
HFXORDY : HFXO Ready Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only
LFRCORDY : LFRCO Ready Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only
LFXORDY : LFXO Ready Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only
AUXHFRCORDY : AUXHFRCO Ready Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-only
CALRDY : Calibration Ready Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-only
CALOF : Calibration Overflow Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-only
HFXODISERR : HFXO Disable Error Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-only
HFXOAUTOSW : HFXO Automatic Switch Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-only
HFXOPEAKDETERR : HFXO Automatic Peak Detection Error Interrupt Flag
bits : 10 - 10 (1 bit)
access : read-only
HFXOPEAKDETRDY : HFXO Automatic Peak Detection Ready Interrupt Flag
bits : 11 - 11 (1 bit)
access : read-only
HFXOSHUNTOPTRDY : HFXO Automatic Shunt Current Optimization Ready Interrupt Flag
bits : 12 - 12 (1 bit)
access : read-only
HFRCODIS : HFRCO Disable Interrupt Flag
bits : 13 - 13 (1 bit)
access : read-only
LFTIMEOUTERR : Low Frequency Timeout Error Interrupt Flag
bits : 14 - 14 (1 bit)
access : read-only
CMUERR : CMU Error Interrupt Flag
bits : 31 - 31 (1 bit)
access : read-only
Interrupt Flag Set Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
HFRCORDY : Set HFRCORDY Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only
HFXORDY : Set HFXORDY Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only
LFRCORDY : Set LFRCORDY Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only
LFXORDY : Set LFXORDY Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only
AUXHFRCORDY : Set AUXHFRCORDY Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only
CALRDY : Set CALRDY Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only
CALOF : Set CALOF Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only
HFXODISERR : Set HFXODISERR Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only
HFXOAUTOSW : Set HFXOAUTOSW Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only
HFXOPEAKDETERR : Set HFXOPEAKDETERR Interrupt Flag
bits : 10 - 10 (1 bit)
access : write-only
HFXOPEAKDETRDY : Set HFXOPEAKDETRDY Interrupt Flag
bits : 11 - 11 (1 bit)
access : write-only
HFXOSHUNTOPTRDY : Set HFXOSHUNTOPTRDY Interrupt Flag
bits : 12 - 12 (1 bit)
access : write-only
HFRCODIS : Set HFRCODIS Interrupt Flag
bits : 13 - 13 (1 bit)
access : write-only
LFTIMEOUTERR : Set LFTIMEOUTERR Interrupt Flag
bits : 14 - 14 (1 bit)
access : write-only
CMUERR : Set CMUERR Interrupt Flag
bits : 31 - 31 (1 bit)
access : write-only
Interrupt Flag Clear Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
HFRCORDY : Clear HFRCORDY Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only
HFXORDY : Clear HFXORDY Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only
LFRCORDY : Clear LFRCORDY Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only
LFXORDY : Clear LFXORDY Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only
AUXHFRCORDY : Clear AUXHFRCORDY Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only
CALRDY : Clear CALRDY Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only
CALOF : Clear CALOF Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only
HFXODISERR : Clear HFXODISERR Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only
HFXOAUTOSW : Clear HFXOAUTOSW Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only
HFXOPEAKDETERR : Clear HFXOPEAKDETERR Interrupt Flag
bits : 10 - 10 (1 bit)
access : write-only
HFXOPEAKDETRDY : Clear HFXOPEAKDETRDY Interrupt Flag
bits : 11 - 11 (1 bit)
access : write-only
HFXOSHUNTOPTRDY : Clear HFXOSHUNTOPTRDY Interrupt Flag
bits : 12 - 12 (1 bit)
access : write-only
HFRCODIS : Clear HFRCODIS Interrupt Flag
bits : 13 - 13 (1 bit)
access : write-only
LFTIMEOUTERR : Clear LFTIMEOUTERR Interrupt Flag
bits : 14 - 14 (1 bit)
access : write-only
CMUERR : Clear CMUERR Interrupt Flag
bits : 31 - 31 (1 bit)
access : write-only
Interrupt Enable Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HFRCORDY : HFRCORDY Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
HFXORDY : HFXORDY Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
LFRCORDY : LFRCORDY Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
LFXORDY : LFXORDY Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
AUXHFRCORDY : AUXHFRCORDY Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
CALRDY : CALRDY Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
CALOF : CALOF Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
HFXODISERR : HFXODISERR Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
HFXOAUTOSW : HFXOAUTOSW Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
HFXOPEAKDETERR : HFXOPEAKDETERR Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
HFXOPEAKDETRDY : HFXOPEAKDETRDY Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
HFXOSHUNTOPTRDY : HFXOSHUNTOPTRDY Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
HFRCODIS : HFRCODIS Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
LFTIMEOUTERR : LFTIMEOUTERR Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
CMUERR : CMUERR Interrupt Enable
bits : 31 - 31 (1 bit)
access : read-write
High Frequency Bus Clock Enable Register 0
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LE : Low Energy Peripheral Interface Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
CRYPTO : Advanced Encryption Standard Accelerator Clock Enable
bits : 1 - 1 (1 bit)
access : read-write
GPIO : General purpose Input/Output Clock Enable
bits : 2 - 2 (1 bit)
access : read-write
PRS : Peripheral Reflex System Clock Enable
bits : 3 - 3 (1 bit)
access : read-write
LDMA : Linked Direct Memory Access Controller Clock Enable
bits : 4 - 4 (1 bit)
access : read-write
GPCRC : General Purpose CRC Clock Enable
bits : 5 - 5 (1 bit)
access : read-write
High Frequency Peripheral Clock Enable Register 0
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER0 : Timer 0 Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
TIMER1 : Timer 1 Clock Enable
bits : 1 - 1 (1 bit)
access : read-write
USART0 : Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable
bits : 2 - 2 (1 bit)
access : read-write
USART1 : Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable
bits : 3 - 3 (1 bit)
access : read-write
ACMP0 : Analog Comparator 0 Clock Enable
bits : 4 - 4 (1 bit)
access : read-write
ACMP1 : Analog Comparator 1 Clock Enable
bits : 5 - 5 (1 bit)
access : read-write
CRYOTIMER : CRYOTIMER Clock Enable
bits : 6 - 6 (1 bit)
access : read-write
I2C0 : I2C 0 Clock Enable
bits : 7 - 7 (1 bit)
access : read-write
ADC0 : Analog to Digital Converter 0 Clock Enable
bits : 8 - 8 (1 bit)
access : read-write
IDAC0 : Current Digital to Analog Converter 0 Clock Enable
bits : 9 - 9 (1 bit)
access : read-write
Low Frequency a Clock Enable Register 0 (Async Reg)
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LETIMER0 : Low Energy Timer 0 Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Low Frequency B Clock Enable Register 0 (Async Reg)
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEUART0 : Low Energy UART 0 Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Low Frequency E Clock Enable Register 0 (Async Reg)
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCC : Real-Time Counter and Calendar Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
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