\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN1 : DAC channel1 enable
bits : 0 - 0 (1 bit)
BOFF1 : DAC channel1 output buffer disable
bits : 1 - 1 (1 bit)
TEN1 : DAC channel1 trigger enable
bits : 2 - 2 (1 bit)
TSEL1 : DAC channel1 trigger selection
bits : 3 - 5 (3 bit)
WAVE2 : WAVE2
bits : 6 - 6 (1 bit)
WAVE1 : DAC channel1 noise/triangle wave generation enable
bits : 7 - 7 (1 bit)
MAMP10 : MAMP10
bits : 8 - 8 (1 bit)
MAMP11 : MAMP11
bits : 9 - 9 (1 bit)
MAMP12 : MAMP12
bits : 10 - 10 (1 bit)
MAMP13 : DAC channel1 mask/amplitude selector
bits : 11 - 11 (1 bit)
DMAEN1 : DAC channel1 DMA enable
bits : 12 - 12 (1 bit)
DMAUDRIE1 : DAC channel1 DMA Underrun Interrupt enable
bits : 13 - 13 (1 bit)
DAC channel1 8-bit right aligned data holding register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 8-bit right-aligned data
bits : 0 - 7 (8 bit)
DAC channel1 data output register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DACC1DOR : DAC channel1 data output
bits : 0 - 11 (12 bit)
DAC status register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAUDR1 : DAC channel1 DMA underrun flag
bits : 13 - 13 (1 bit)
software trigger register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWTRIG1 : DAC channel1 software trigger
bits : 0 - 0 (1 bit)
channel1 12-bit right-aligned data holding register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit right-aligned data
bits : 0 - 11 (12 bit)
DAC channel1 12-bit left aligned data holding register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit left-aligned data
bits : 4 - 15 (12 bit)
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