\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)
access : write-only
RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)
access : write-only
RXEN : Receiver Enable
bits : 4 - 4 (1 bit)
access : write-only
RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)
access : write-only
TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)
access : write-only
TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)
access : write-only
RSTSTA : Reset Status Bits
bits : 8 - 8 (1 bit)
access : write-only
STTBRK : Start Break
bits : 9 - 9 (1 bit)
access : write-only
STPBRK : Stop Break
bits : 10 - 10 (1 bit)
access : write-only
STTTO : Start Time-out
bits : 11 - 11 (1 bit)
access : write-only
SENDA : Send Address
bits : 12 - 12 (1 bit)
access : write-only
RSTIT : Reset Iterations
bits : 13 - 13 (1 bit)
access : write-only
RSTNACK : Reset Non Acknowledge
bits : 14 - 14 (1 bit)
access : write-only
RETTO : Rearm Time-out
bits : 15 - 15 (1 bit)
access : write-only
DTREN : Data Terminal Ready Enable
bits : 16 - 16 (1 bit)
access : write-only
DTRDIS : Data Terminal Ready Disable
bits : 17 - 17 (1 bit)
access : write-only
RTSEN : Request to Send Enable
bits : 18 - 18 (1 bit)
access : write-only
RTSDIS : Request to Send Disable
bits : 19 - 19 (1 bit)
access : write-only
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0
RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)
access : write-only
RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)
access : write-only
RXEN : Receiver Enable
bits : 4 - 4 (1 bit)
access : write-only
RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)
access : write-only
TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)
access : write-only
TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)
access : write-only
RSTSTA : Reset Status Bits
bits : 8 - 8 (1 bit)
access : write-only
FCS : Force SPI Chip Select
bits : 18 - 18 (1 bit)
access : write-only
RCS : Release SPI Chip Select
bits : 19 - 19 (1 bit)
access : write-only
Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
RXBRK : Receiver Break Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
ENDRX : End of Receive Transfer Interrupt Mask (available in all USART modes of operation)
bits : 3 - 3 (1 bit)
access : read-only
ENDTX : End of Transmit Interrupt Mask (available in all USART modes of operation)
bits : 4 - 4 (1 bit)
access : read-only
OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
FRAME : Framing Error Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
PARE : Parity Error Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only
TIMEOUT : Time-out Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
ITER : Max Number of Repetitions Reached Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
TXBUFE : Buffer Empty Interrupt Mask (available in all USART modes of operation)
bits : 11 - 11 (1 bit)
access : read-only
RXBUFF : Buffer Full Interrupt Mask (available in all USART modes of operation)
bits : 12 - 12 (1 bit)
access : read-only
NACK : Non AcknowledgeInterrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
RIIC : Ring Indicator Input Change Mask
bits : 16 - 16 (1 bit)
access : read-only
DSRIC : Data Set Ready Input Change Mask
bits : 17 - 17 (1 bit)
access : read-only
DCDIC : Data Carrier Detect Input Change Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only
CTSIC : Clear to Send Input Change Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only
MANE : Manchester Error Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only
Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
ENDRX :
bits : 3 - 3 (1 bit)
access : read-only
ENDTX :
bits : 4 - 4 (1 bit)
access : read-only
OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
UNRE : SPI Underrun Error Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
TXBUFE :
bits : 11 - 11 (1 bit)
access : read-only
RXBUFF :
bits : 12 - 12 (1 bit)
access : read-only
Receive Pointer Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXPTR : Receive Pointer Register
bits : 0 - 31 (32 bit)
access : read-write
Receive Counter Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXCTR : Receive Counter Register
bits : 0 - 15 (16 bit)
access : read-write
Transmit Pointer Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPTR : Transmit Counter Register
bits : 0 - 31 (32 bit)
access : read-write
Transmit Counter Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCTR : Transmit Counter Register
bits : 0 - 15 (16 bit)
access : read-write
Receive Next Pointer Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXNPTR : Receive Next Pointer
bits : 0 - 31 (32 bit)
access : read-write
Receive Next Counter Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXNCTR : Receive Next Counter
bits : 0 - 15 (16 bit)
access : read-write
Transmit Next Pointer Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNPTR : Transmit Next Pointer
bits : 0 - 31 (32 bit)
access : read-write
Transmit Next Counter Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNCTR : Transmit Counter Next
bits : 0 - 15 (16 bit)
access : read-write
Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only
RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only
TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only
Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only
Channel Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receiver Ready
bits : 0 - 0 (1 bit)
access : read-only
TXRDY : Transmitter Ready
bits : 1 - 1 (1 bit)
access : read-only
RXBRK : Break Received/End of Break
bits : 2 - 2 (1 bit)
access : read-only
ENDRX : End of Receiver Transfer
bits : 3 - 3 (1 bit)
access : read-only
ENDTX : End of Transmitter Transfer
bits : 4 - 4 (1 bit)
access : read-only
OVRE : Overrun Error
bits : 5 - 5 (1 bit)
access : read-only
FRAME : Framing Error
bits : 6 - 6 (1 bit)
access : read-only
PARE : Parity Error
bits : 7 - 7 (1 bit)
access : read-only
TIMEOUT : Receiver Time-out
bits : 8 - 8 (1 bit)
access : read-only
TXEMPTY : Transmitter Empty
bits : 9 - 9 (1 bit)
access : read-only
ITER : Max Number of Repetitions Reached
bits : 10 - 10 (1 bit)
access : read-only
TXBUFE : Transmission Buffer Empty
bits : 11 - 11 (1 bit)
access : read-only
RXBUFF : Reception Buffer Full
bits : 12 - 12 (1 bit)
access : read-only
NACK : Non AcknowledgeInterrupt
bits : 13 - 13 (1 bit)
access : read-only
RIIC : Ring Indicator Input Change Flag
bits : 16 - 16 (1 bit)
access : read-only
DSRIC : Data Set Ready Input Change Flag
bits : 17 - 17 (1 bit)
access : read-only
DCDIC : Data Carrier Detect Input Change Flag
bits : 18 - 18 (1 bit)
access : read-only
CTSIC : Clear to Send Input Change Flag
bits : 19 - 19 (1 bit)
access : read-only
RI : Image of RI Input
bits : 20 - 20 (1 bit)
access : read-only
DSR : Image of DSR Input
bits : 21 - 21 (1 bit)
access : read-only
DCD : Image of DCD Input
bits : 22 - 22 (1 bit)
access : read-only
CTS : Image of CTS Input
bits : 23 - 23 (1 bit)
access : read-only
MANERR : Manchester Error
bits : 24 - 24 (1 bit)
access : read-only
Channel Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0
RXRDY : Receiver Ready
bits : 0 - 0 (1 bit)
access : read-only
TXRDY : Transmitter Ready
bits : 1 - 1 (1 bit)
access : read-only
ENDRX :
bits : 3 - 3 (1 bit)
access : read-only
ENDTX :
bits : 4 - 4 (1 bit)
access : read-only
OVRE : Overrun Error
bits : 5 - 5 (1 bit)
access : read-only
TXEMPTY : Transmitter Empty
bits : 9 - 9 (1 bit)
access : read-only
UNRE : Underrun Error
bits : 10 - 10 (1 bit)
access : read-only
TXBUFE :
bits : 11 - 11 (1 bit)
access : read-only
RXBUFF :
bits : 12 - 12 (1 bit)
access : read-only
Receiver Holding Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXCHR : Received Character
bits : 0 - 8 (9 bit)
access : read-only
RXSYNH : Received Sync
bits : 15 - 15 (1 bit)
access : read-only
Transmitter Holding Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXCHR : Character to be Transmitted
bits : 0 - 8 (9 bit)
access : write-only
TXSYNH : Sync Field to be Transmitted
bits : 15 - 15 (1 bit)
access : write-only
Baud Rate Generator Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CD : Clock Divider
bits : 0 - 15 (16 bit)
access : read-write
FP : Fractional Part
bits : 16 - 18 (3 bit)
access : read-write
Receiver Time-out Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TO : Time-out Value
bits : 0 - 15 (16 bit)
access : read-write
Transmitter Timeguard Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TG : Timeguard Value
bits : 0 - 7 (8 bit)
access : read-write
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USART_MODE : USART Mode of Operation
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : NORMAL
Normal mode
0x1 : RS485
RS485
0x2 : HW_HANDSHAKING
Hardware Handshaking
0x3 : MODEM
Modem
0x4 : IS07816_T_0
IS07816 Protocol: T = 0
0x6 : IS07816_T_1
IS07816 Protocol: T = 1
0x8 : IRDA
IrDA
0xE : SPI_MASTER
SPI Master
0xF : SPI_SLAVE
SPI Slave
End of enumeration elements list.
USCLKS : Clock Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : MCK
Master Clock MCK is selected
0x1 : DIV
Internal Clock Divided MCK/DIV (DIV=8) is selected
0x3 : SCK
Serial Clock SLK is selected
End of enumeration elements list.
CHRL : Character Length.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 5_BIT
Character length is 5 bits
0x1 : 6_BIT
Character length is 6 bits
0x2 : 7_BIT
Character length is 7 bits
0x3 : 8_BIT
Character length is 8 bits
End of enumeration elements list.
SYNC : Synchronous Mode Select
bits : 8 - 8 (1 bit)
access : read-write
PAR : Parity Type
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0x0 : EVEN
Even parity
0x1 : ODD
Odd parity
0x2 : SPACE
Parity forced to 0 (Space)
0x3 : MARK
Parity forced to 1 (Mark)
0x4 : NO
No parity
0x6 : MULTIDROP
Multidrop mode
End of enumeration elements list.
NBSTOP : Number of Stop Bits
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BIT
1 stop bit
0x1 : 1_5_BIT
1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
0x2 : 2_BIT
2 stop bits
End of enumeration elements list.
CHMODE : Channel Mode
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0x0 : NORMAL
Normal Mode
0x1 : AUTOMATIC
Automatic Echo. Receiver input is connected to the TXD pin.
0x2 : LOCAL_LOOPBACK
Local Loopback. Transmitter output is connected to the Receiver Input.
0x3 : REMOTE_LOOPBACK
Remote Loopback. RXD pin is internally connected to the TXD pin.
End of enumeration elements list.
MSBF : Bit Order
bits : 16 - 16 (1 bit)
access : read-write
MODE9 : 9-bit Character Length
bits : 17 - 17 (1 bit)
access : read-write
CLKO : Clock Output Select
bits : 18 - 18 (1 bit)
access : read-write
OVER : Oversampling Mode
bits : 19 - 19 (1 bit)
access : read-write
INACK : Inhibit Non Acknowledge
bits : 20 - 20 (1 bit)
access : read-write
DSNACK : Disable Successive NACK
bits : 21 - 21 (1 bit)
access : read-write
VAR_SYNC : Variable Synchronization of Command/Data Sync Start Frame Delimiter
bits : 22 - 22 (1 bit)
access : read-write
INVDATA : Inverted Data
bits : 23 - 23 (1 bit)
access : read-write
MAX_ITERATION : Maximum Number of Automatic Iteration
bits : 24 - 26 (3 bit)
access : read-write
FILTER : Infrared Receive Line Filter
bits : 28 - 28 (1 bit)
access : read-write
MAN : Manchester Encoder/Decoder Enable
bits : 29 - 29 (1 bit)
access : read-write
MODSYNC : Manchester Synchronization Mode
bits : 30 - 30 (1 bit)
access : read-write
ONEBIT : Start Frame Delimiter Selector
bits : 31 - 31 (1 bit)
access : read-write
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0
USART_MODE : USART Mode of Operation
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0xE : SPI_MASTER
SPI Master
0xF : SPI_SLAVE
SPI Slave
End of enumeration elements list.
USCLKS : Clock Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : MCK
Master Clock MCK is selected
0x1 : DIV
Internal Clock Divided MCK/DIV (DIV=8) is selected
0x3 : SCK
Serial Clock SLK is selected
End of enumeration elements list.
CHRL : Character Length.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x3 : 8_BIT
Character length is 8 bits
End of enumeration elements list.
CPHA : SPI Clock Phase
bits : 8 - 8 (1 bit)
access : read-write
CPOL : SPI Clock Polarity
bits : 16 - 16 (1 bit)
access : read-write
WRDBT : Wait Read Data Before Transfer
bits : 20 - 20 (1 bit)
access : read-write
FI DI Ratio Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FI_DI_RATIO : FI Over DI Ratio Value
bits : 0 - 15 (16 bit)
access : read-write
Number of Errors Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NB_ERRORS : Number of Errors
bits : 0 - 7 (8 bit)
access : read-only
IrDA Filter Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRDA_FILTER : IrDA Filter
bits : 0 - 7 (8 bit)
access : read-write
Manchester Encoder Decoder Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_PL : Transmitter Preamble Length
bits : 0 - 3 (4 bit)
access : read-write
TX_PP : Transmitter Preamble Pattern
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : ALL_ONE
The preamble is composed of '1's
0x1 : ALL_ZERO
The preamble is composed of '0's
0x2 : ZERO_ONE
The preamble is composed of '01's
0x3 : ONE_ZERO
The preamble is composed of '10's
End of enumeration elements list.
TX_MPOL : Transmitter Manchester Polarity
bits : 12 - 12 (1 bit)
access : read-write
RX_PL : Receiver Preamble Length
bits : 16 - 19 (4 bit)
access : read-write
RX_PP : Receiver Preamble Pattern detected
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : ALL_ONE
The preamble is composed of '1's
0x1 : ALL_ZERO
The preamble is composed of '0's
0x2 : ZERO_ONE
The preamble is composed of '01's
0x3 : ONE_ZERO
The preamble is composed of '10's
End of enumeration elements list.
RX_MPOL : Receiver Manchester Polarity
bits : 28 - 28 (1 bit)
access : read-write
ONE : Must Be Set to 1
bits : 29 - 29 (1 bit)
access : read-write
DRIFT : Drift Compensation
bits : 30 - 30 (1 bit)
access : read-write
Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXRDY : TXRDY Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
RXBRK : Receiver Break Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
ENDRX : End of Receive Transfer Interrupt Enable (available in all USART modes of operation)
bits : 3 - 3 (1 bit)
access : write-only
ENDTX : End of Transmit Interrupt Enable (available in all USART modes of operation)
bits : 4 - 4 (1 bit)
access : write-only
OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
FRAME : Framing Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
PARE : Parity Error Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
TIMEOUT : Time-out Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
TXEMPTY : TXEMPTY Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
ITER : Max number of Repetitions Reached Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXBUFE : Buffer Empty Interrupt Enable (available in all USART modes of operation)
bits : 11 - 11 (1 bit)
access : write-only
RXBUFF : Buffer Full Interrupt Enable (available in all USART modes of operation)
bits : 12 - 12 (1 bit)
access : write-only
NACK : Non AcknowledgeInterrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
RIIC : Ring Indicator Input Change Enable
bits : 16 - 16 (1 bit)
access : write-only
DSRIC : Data Set Ready Input Change Enable
bits : 17 - 17 (1 bit)
access : write-only
DCDIC : Data Carrier Detect Input Change Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
CTSIC : Clear to Send Input Change Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
MANE : Manchester Error Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only
Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXRDY : TXRDY Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
ENDRX :
bits : 3 - 3 (1 bit)
access : write-only
ENDTX :
bits : 4 - 4 (1 bit)
access : write-only
OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
TXEMPTY : TXEMPTY Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
UNRE : SPI Underrun Error Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXBUFE :
bits : 11 - 11 (1 bit)
access : write-only
RXBUFF :
bits : 12 - 12 (1 bit)
access : write-only
Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXRDY : TXRDY Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
RXBRK : Receiver Break Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
ENDRX : End of Receive Transfer Interrupt Disable (available in all USART modes of operation)
bits : 3 - 3 (1 bit)
access : write-only
ENDTX : End of Transmit Interrupt Disable (available in all USART modes of operation)
bits : 4 - 4 (1 bit)
access : write-only
OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
FRAME : Framing Error Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
PARE : Parity Error Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
TIMEOUT : Time-out Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
TXEMPTY : TXEMPTY Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
ITER : Max Number of Repetitions Reached Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXBUFE : Buffer Empty Interrupt Disable (available in all USART modes of operation)
bits : 11 - 11 (1 bit)
access : write-only
RXBUFF : Buffer Full Interrupt Disable (available in all USART modes of operation)
bits : 12 - 12 (1 bit)
access : write-only
NACK : Non AcknowledgeInterrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
RIIC : Ring Indicator Input Change Disable
bits : 16 - 16 (1 bit)
access : write-only
DSRIC : Data Set Ready Input Change Disable
bits : 17 - 17 (1 bit)
access : write-only
DCDIC : Data Carrier Detect Input Change Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
CTSIC : Clear to Send Input Change Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
MANE : Manchester Error Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only
Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXRDY : TXRDY Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
ENDRX :
bits : 3 - 3 (1 bit)
access : write-only
ENDTX :
bits : 4 - 4 (1 bit)
access : write-only
OVRE : Overrun Error Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
TXEMPTY : TXEMPTY Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
UNRE : SPI Underrun Error Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXBUFE :
bits : 11 - 11 (1 bit)
access : write-only
RXBUFF :
bits : 12 - 12 (1 bit)
access : write-only
Write Protect Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protect KEY.
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x555341 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
End of enumeration elements list.
Write Protect Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protect Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protect Violation Source
bits : 8 - 23 (16 bit)
access : read-only
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