\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP Version ID
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COREBIASSTARTUPI : Intermediate Startup Core Bias Current
bits : 0 - 5 (6 bit)
access : read-write
COREBIASSTARTUP : Startup Core Bias Current
bits : 6 - 11 (6 bit)
access : read-write
CTUNEXISTARTUP : Startup Tuning Capacitance on XI
bits : 12 - 15 (4 bit)
access : read-write
CTUNEXOSTARTUP : Startup Tuning Capacitance on XO
bits : 16 - 19 (4 bit)
access : read-write
TIMEOUTSTEADY : Steady State Timeout
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0 : T16US
The steady state timeout is set to 16 us minimum. The maximum can be +40%.
1 : T41US
The steady state timeout is set to 41 us minimum. The maximum can be +40%.
2 : T83US
The steady state timeout is set to 83 us minimum. The maximum can be +40%.
3 : T125US
The steady state timeout is set to 125 us minimum. The maximum can be +40%.
4 : T166US
The steady state timeout is set to 166 us minimum. The maximum can be +40%.
5 : T208US
The steady state timeout is set to 208 us minimum. The maximum can be +40%.
6 : T250US
The steady state timeout is set to 250 us minimum. The maximum can be +40%.
7 : T333US
The steady state timeout is set to 333 us minimum. The maximum can be +40%.
8 : T416US
The steady state timeout is set to 416 us minimum. The maximum can be +40%.
9 : T500US
The steady state timeout is set to 500 us minimum. The maximum can be +40%.
10 : T666US
The steady state timeout is set to 666 us minimum. The maximum can be +40%.
11 : T833US
The steady state timeout is set to 833 us minimum. The maximum can be +40%.
12 : T1666US
The steady state timeout is set to 1666 us minimum. The maximum can be +40%.
13 : T2500US
The steady state timeout is set to 2500 us minimum. The maximum can be +40%.
14 : T4166US
The steady state timeout is set to 4166 us minimum. The maximum can be +40%.
15 : T7500US
The steady state timeout is set to 7500 us minimum. The maximum can be +40%.
End of enumeration elements list.
TIMEOUTCBLSB : Core Bias LSB Change Timeout
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : T8US
The core bias LSB change timeout is set to 8 us minimum. The maximum can be +40%.
1 : T20US
The core bias LSB change timeout is set to 20 us minimum. The maximum can be +40%.
2 : T41US
The core bias LSB change timeout is set to 41 us minimum. The maximum can be +40%.
3 : T62US
The core bias LSB change timeout is set to 62 us minimum. The maximum can be +40%.
4 : T83US
The core bias LSB change timeout is set to 83 us minimum. The maximum can be +40%.
5 : T104US
The core bias LSB change timeout is set to 104 us minimum. The maximum can be +40%.
6 : T125US
The core bias LSB change timeout is set to 125 us minimum. The maximum can be +40%.
7 : T166US
The core bias LSB change timeout is set to 166 us minimum. The maximum can be +40%.
8 : T208US
The core bias LSB change timeout is set to 208 us minimum. The maximum can be +40%.
9 : T250US
The core bias LSB change timeout is set to 250 us minimum. The maximum can be +40%.
10 : T333US
The core bias LSB change timeout is set to 333 us minimum. The maximum can be +40%.
11 : T416US
The core bias LSB change timeout is set to 416 us minimum. The maximum can be +40%.
12 : T833US
The core bias LSB change timeout is set to 833 us minimum. The maximum can be +40%.
13 : T1250US
The core bias LSB change timeout is set to 1250 us minimum. The maximum can be +40%.
14 : T2083US
The core bias LSB change timeout is set to 2083 us minimum. The maximum can be +40%.
15 : T3750US
The core bias LSB change timeout is set to 3750 us minimum. The maximum can be +40%.
End of enumeration elements list.
No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COREBIASANA : Core Bias Current
bits : 0 - 7 (8 bit)
access : read-write
CTUNEXIANA : Tuning Capacitance on XI
bits : 8 - 15 (8 bit)
access : read-write
CTUNEXOANA : Tuning Capacitance on XO
bits : 16 - 23 (8 bit)
access : read-write
CTUNEFIXANA : Fixed Tuning Capacitance
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : NONE
Remove fixed capacitance on XI and XO nodes
1 : XI
Adds fixed capacitance on XI node
2 : XO
Adds fixed capacitance on XO node
3 : BOTH
Adds fixed capacitance on both XI and XO nodes
End of enumeration elements list.
COREDGENANA : Core Degeneration
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : NONE
Do not apply core degeneration resistence
1 : DGEN33
Apply 33 ohm core degeneration resistence
2 : DGEN50
Apply 50 ohm core degeneration resistence
3 : DGEN100
Apply 100 ohm core degeneration resistence
End of enumeration elements list.
SKIPCOREBIASOPT : Skip Core Bias Optimization
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Crystal Oscillator Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : XTAL
crystal oscillator
1 : EXTCLK
external sinusoidal clock can be supplied on XI pin.
End of enumeration elements list.
ENXIDCBIASANA : Enable XI Internal DC Bias
bits : 2 - 2 (1 bit)
access : read-write
SQBUFSCHTRGANA : Squaring Buffer Schmitt Trigger
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Squaring buffer schmitt trigger is disabled
1 : ENABLE
Squaring buffer schmitt trigger is enabled
End of enumeration elements list.
No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORCEEN : Force Enable
bits : 0 - 0 (1 bit)
access : read-write
DISONDEMAND : Disable On-demand Mode
bits : 1 - 1 (1 bit)
access : read-write
KEEPWARM : Keep Warm
bits : 2 - 2 (1 bit)
access : read-write
FORCEXI2GNDANA : Force XI Pin to Ground
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled (not pulled)
1 : ENABLE
Enabled (pulled)
End of enumeration elements list.
FORCEXO2GNDANA : Force XO Pin to Ground
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled (not pulled)
1 : ENABLE
Enabled (pulled)
End of enumeration elements list.
No Description
address_offset : 0x50 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COREBIASOPT : Core Bias Optimizaton
bits : 0 - 0 (1 bit)
access : write-only
MANUALOVERRIDE : Manual Override
bits : 1 - 1 (1 bit)
access : write-only
No Description
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDY : Ready Status
bits : 0 - 0 (1 bit)
access : read-only
COREBIASOPTRDY : Core Bias Optimization Ready
bits : 1 - 1 (1 bit)
access : read-only
ENS : Enabled Status
bits : 16 - 16 (1 bit)
access : read-only
HWREQ : Oscillator Requested by Hardware
bits : 17 - 17 (1 bit)
access : read-only
ISWARM : Oscillator Is Kept Warm
bits : 19 - 19 (1 bit)
access : read-only
FSMLOCK : FSM Lock Status
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : UNLOCKED
FSM lock is unlocked
1 : LOCKED
FSM lock is locked
End of enumeration elements list.
LOCK : Configuration Lock Status
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : UNLOCKED
Configuration lock is unlocked
1 : LOCKED
Configuration lock is locked
End of enumeration elements list.
No Description
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDY : Ready Interrupt
bits : 0 - 0 (1 bit)
access : read-write
COREBIASOPTRDY : Core Bias Optimization Ready Interrupt
bits : 1 - 1 (1 bit)
access : read-write
DNSERR : Did Not Start Error Interrupt
bits : 29 - 29 (1 bit)
access : read-write
COREBIASOPTERR : Core Bias Optimization Error Interrupt
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDY : Ready Interrupt
bits : 0 - 0 (1 bit)
access : read-write
COREBIASOPTRDY : Core Bias Optimization Ready Interrupt
bits : 1 - 1 (1 bit)
access : read-write
DNSERR : Did Not Start Error Interrupt
bits : 29 - 29 (1 bit)
access : read-write
COREBIASOPTERR : Core Bias Optimization Error Interrupt
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LOCKKEY : Configuration Lock Key
bits : 0 - 15 (16 bit)
access : write-only
Enumeration:
22542 : UNLOCK
Write this value to unlock
End of enumeration elements list.
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