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CAN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MR

SR

BR

TIM

TIMESTP

ECR

MMR0

MAM0

MID0

MFID0

MSR0

MDL0

MDH0

MCR0

MMR1

MAM1

MID1

MFID1

MSR1

MDL1

MDH1

MCR1

TCR

MMR2

MAM2

MID2

MFID2

MSR2

MDL2

MDH2

MCR2

MMR3

MAM3

MID3

MFID3

MSR3

MDL3

MDH3

MCR3

ACR

MMR4

MAM4

MID4

MFID4

MSR4

MDL4

MDH4

MCR4

MMR5

MAM5

MID5

MFID5

MSR5

MDL5

MDH5

MCR5

MMR6

MAM6

MID6

MFID6

MSR6

MDL6

MDH6

MCR6

MMR7

MAM7

MID7

MFID7

MSR7

MDL7

MDH7

MCR7

IER

IDR

IMR

WPMR

WPSR


MR

Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CANEN LPM ABM OVL TEOF TTM TIMFRZ DRPT RXSYNC

CANEN : CAN Controller Enable
bits : 0 - 0 (1 bit)
access : read-write

LPM : Disable/Enable Low Power Mode
bits : 1 - 1 (1 bit)
access : read-write

ABM : Disable/Enable Autobaud/Listen mode
bits : 2 - 2 (1 bit)
access : read-write

OVL : Disable/Enable Overload Frame
bits : 3 - 3 (1 bit)
access : read-write

TEOF : Timestamp messages at each end of Frame
bits : 4 - 4 (1 bit)
access : read-write

TTM : Disable/Enable Time Triggered Mode
bits : 5 - 5 (1 bit)
access : read-write

TIMFRZ : Enable Timer Freeze
bits : 6 - 6 (1 bit)
access : read-write

DRPT : Disable Repeat
bits : 7 - 7 (1 bit)
access : read-write

RXSYNC : Reception Synchronization Stage (not readable)
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x0 : DOUBLE_PP

Rx Signal with Double Synchro Stages (2 Positive Edges)

0x1 : DOUBLE_PN

Rx Signal with Double Synchro Stages (One Positive Edge and One Negative Edge)

0x2 : SINGLE_P

Rx Signal with Single Synchro Stage (Positive Edge)

0x3 : NONE

Rx Signal with No Synchro Stage

End of enumeration elements list.


SR

Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7 ERRA WARN ERRP BOFF SLEEP WAKEUP TOVF TSTP CERR SERR AERR FERR BERR RBSY TBSY OVLSY

MB0 : Mailbox 0 Event
bits : 0 - 0 (1 bit)
access : read-only

MB1 : Mailbox 1 Event
bits : 1 - 1 (1 bit)
access : read-only

MB2 : Mailbox 2 Event
bits : 2 - 2 (1 bit)
access : read-only

MB3 : Mailbox 3 Event
bits : 3 - 3 (1 bit)
access : read-only

MB4 : Mailbox 4 Event
bits : 4 - 4 (1 bit)
access : read-only

MB5 : Mailbox 5 Event
bits : 5 - 5 (1 bit)
access : read-only

MB6 : Mailbox 6 Event
bits : 6 - 6 (1 bit)
access : read-only

MB7 : Mailbox 7 Event
bits : 7 - 7 (1 bit)
access : read-only

ERRA : Error Active Mode
bits : 16 - 16 (1 bit)
access : read-only

WARN : Warning Limit
bits : 17 - 17 (1 bit)
access : read-only

ERRP : Error Passive Mode
bits : 18 - 18 (1 bit)
access : read-only

BOFF : Bus Off Mode
bits : 19 - 19 (1 bit)
access : read-only

SLEEP : CAN controller in Low power Mode
bits : 20 - 20 (1 bit)
access : read-only

WAKEUP : CAN controller is not in Low power Mode
bits : 21 - 21 (1 bit)
access : read-only

TOVF : Timer Overflow
bits : 22 - 22 (1 bit)
access : read-only

TSTP :
bits : 23 - 23 (1 bit)
access : read-only

CERR : Mailbox CRC Error
bits : 24 - 24 (1 bit)
access : read-only

SERR : Mailbox Stuffing Error
bits : 25 - 25 (1 bit)
access : read-only

AERR : Acknowledgment Error
bits : 26 - 26 (1 bit)
access : read-only

FERR : Form Error
bits : 27 - 27 (1 bit)
access : read-only

BERR : Bit Error
bits : 28 - 28 (1 bit)
access : read-only

RBSY : Receiver busy
bits : 29 - 29 (1 bit)
access : read-only

TBSY : Transmitter busy
bits : 30 - 30 (1 bit)
access : read-only

OVLSY : Overload busy
bits : 31 - 31 (1 bit)
access : read-only


BR

Baudrate Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BR BR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHASE2 PHASE1 PROPAG SJW BRP SMP

PHASE2 : Phase 2 segment
bits : 0 - 2 (3 bit)
access : read-write

PHASE1 : Phase 1 segment
bits : 4 - 6 (3 bit)
access : read-write

PROPAG : Programming time segment
bits : 8 - 10 (3 bit)
access : read-write

SJW : Re-synchronization jump width
bits : 12 - 13 (2 bit)
access : read-write

BRP : Baudrate Prescaler.
bits : 16 - 22 (7 bit)
access : read-write

SMP : Sampling Mode
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ONCE

The incoming bit stream is sampled once at sample point.

1 : THREE

The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point.

End of enumeration elements list.


TIM

Timer Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TIM TIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER

TIMER : Timer
bits : 0 - 15 (16 bit)
access : read-only


TIMESTP

Timestamp Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TIMESTP TIMESTP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMESTAMP

MTIMESTAMP : Timestamp
bits : 0 - 15 (16 bit)
access : read-only


ECR

Error Counter Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECR ECR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REC TEC

REC : Receive Error Counter
bits : 0 - 7 (8 bit)
access : read-only

TEC : Transmit Error Counter
bits : 16 - 23 (8 bit)
access : read-only


MMR0

Mailbox Mode Register (MB = 0)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMR0 MMR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMEMARK PRIOR MOT

MTIMEMARK : Mailbox Timemark
bits : 0 - 15 (16 bit)
access : read-write

PRIOR : Mailbox Priority
bits : 16 - 19 (4 bit)
access : read-write

MOT : Mailbox Object Type
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x0 : MB_DISABLED

Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.

0x1 : MB_RX

Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.

0x2 : MB_RX_OVERWRITE

Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.

0x3 : MB_TX

Transmit mailbox. Mailbox is configured for transmission.

0x4 : MB_CONSUMER

Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.

0x5 : MB_PRODUCER

Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

End of enumeration elements list.


MAM0

Mailbox Acceptance Mask Register (MB = 0)
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAM0 MAM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIDvB MIDvA MIDE

MIDvB : Complementary bits for identifier in extended frame mode
bits : 0 - 17 (18 bit)
access : read-write

MIDvA : Identifier for standard frame mode
bits : 18 - 28 (11 bit)
access : read-write

MIDE : Identifier Version
bits : 29 - 29 (1 bit)
access : read-write


MID0

Mailbox ID Register (MB = 0)
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MID0 MID0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIDvB MIDvA MIDE

MIDvB : Complementary bits for identifier in extended frame mode
bits : 0 - 17 (18 bit)
access : read-write

MIDvA : Identifier for standard frame mode
bits : 18 - 28 (11 bit)
access : read-write

MIDE : Identifier Version
bits : 29 - 29 (1 bit)
access : read-write


MFID0

Mailbox Family ID Register (MB = 0)
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MFID0 MFID0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFID

MFID : Family ID
bits : 0 - 28 (29 bit)
access : read-only


MSR0

Mailbox Status Register (MB = 0)
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSR0 MSR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMESTAMP MDLC MRTR MABT MRDY MMI

MTIMESTAMP : Timer value
bits : 0 - 15 (16 bit)
access : read-only

MDLC : Mailbox Data Length Code
bits : 16 - 19 (4 bit)
access : read-only

MRTR : Mailbox Remote Transmission Request
bits : 20 - 20 (1 bit)
access : read-only

MABT : Mailbox Message Abort
bits : 22 - 22 (1 bit)
access : read-only

MRDY : Mailbox Ready
bits : 23 - 23 (1 bit)
access : read-only

MMI : Mailbox Message Ignored
bits : 24 - 24 (1 bit)
access : read-only


MDL0

Mailbox Data Low Register (MB = 0)
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDL0 MDL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDL

MDL : Message Data Low Value
bits : 0 - 31 (32 bit)
access : read-write


MDH0

Mailbox Data High Register (MB = 0)
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDH0 MDH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDH

MDH : Message Data High Value
bits : 0 - 31 (32 bit)
access : read-write


MCR0

Mailbox Control Register (MB = 0)
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MCR0 MCR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDLC MRTR MACR MTCR

MDLC : Mailbox Data Length Code
bits : 16 - 19 (4 bit)
access : write-only

MRTR : Mailbox Remote Transmission Request
bits : 20 - 20 (1 bit)
access : write-only

MACR : Abort Request for Mailbox x
bits : 22 - 22 (1 bit)
access : write-only

MTCR : Mailbox Transfer Command
bits : 23 - 23 (1 bit)
access : write-only


MMR1

Mailbox Mode Register (MB = 1)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMR1 MMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMEMARK PRIOR MOT

MTIMEMARK : Mailbox Timemark
bits : 0 - 15 (16 bit)
access : read-write

PRIOR : Mailbox Priority
bits : 16 - 19 (4 bit)
access : read-write

MOT : Mailbox Object Type
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x0 : MB_DISABLED

Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.

0x1 : MB_RX

Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.

0x2 : MB_RX_OVERWRITE

Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.

0x3 : MB_TX

Transmit mailbox. Mailbox is configured for transmission.

0x4 : MB_CONSUMER

Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.

0x5 : MB_PRODUCER

Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

End of enumeration elements list.


MAM1

Mailbox Acceptance Mask Register (MB = 1)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAM1 MAM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIDvB MIDvA MIDE

MIDvB : Complementary bits for identifier in extended frame mode
bits : 0 - 17 (18 bit)
access : read-write

MIDvA : Identifier for standard frame mode
bits : 18 - 28 (11 bit)
access : read-write

MIDE : Identifier Version
bits : 29 - 29 (1 bit)
access : read-write


MID1

Mailbox ID Register (MB = 1)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MID1 MID1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIDvB MIDvA MIDE

MIDvB : Complementary bits for identifier in extended frame mode
bits : 0 - 17 (18 bit)
access : read-write

MIDvA : Identifier for standard frame mode
bits : 18 - 28 (11 bit)
access : read-write

MIDE : Identifier Version
bits : 29 - 29 (1 bit)
access : read-write


MFID1

Mailbox Family ID Register (MB = 1)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MFID1 MFID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFID

MFID : Family ID
bits : 0 - 28 (29 bit)
access : read-only


MSR1

Mailbox Status Register (MB = 1)
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSR1 MSR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMESTAMP MDLC MRTR MABT MRDY MMI

MTIMESTAMP : Timer value
bits : 0 - 15 (16 bit)
access : read-only

MDLC : Mailbox Data Length Code
bits : 16 - 19 (4 bit)
access : read-only

MRTR : Mailbox Remote Transmission Request
bits : 20 - 20 (1 bit)
access : read-only

MABT : Mailbox Message Abort
bits : 22 - 22 (1 bit)
access : read-only

MRDY : Mailbox Ready
bits : 23 - 23 (1 bit)
access : read-only

MMI : Mailbox Message Ignored
bits : 24 - 24 (1 bit)
access : read-only


MDL1

Mailbox Data Low Register (MB = 1)
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDL1 MDL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDL

MDL : Message Data Low Value
bits : 0 - 31 (32 bit)
access : read-write


MDH1

Mailbox Data High Register (MB = 1)
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDH1 MDH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDH

MDH : Message Data High Value
bits : 0 - 31 (32 bit)
access : read-write


MCR1

Mailbox Control Register (MB = 1)
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MCR1 MCR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDLC MRTR MACR MTCR

MDLC : Mailbox Data Length Code
bits : 16 - 19 (4 bit)
access : write-only

MRTR : Mailbox Remote Transmission Request
bits : 20 - 20 (1 bit)
access : write-only

MACR : Abort Request for Mailbox x
bits : 22 - 22 (1 bit)
access : write-only

MTCR : Mailbox Transfer Command
bits : 23 - 23 (1 bit)
access : write-only


TCR

Transfer Command Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TCR TCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7 TIMRST

MB0 : Transfer Request for Mailbox 0
bits : 0 - 0 (1 bit)
access : write-only

MB1 : Transfer Request for Mailbox 1
bits : 1 - 1 (1 bit)
access : write-only

MB2 : Transfer Request for Mailbox 2
bits : 2 - 2 (1 bit)
access : write-only

MB3 : Transfer Request for Mailbox 3
bits : 3 - 3 (1 bit)
access : write-only

MB4 : Transfer Request for Mailbox 4
bits : 4 - 4 (1 bit)
access : write-only

MB5 : Transfer Request for Mailbox 5
bits : 5 - 5 (1 bit)
access : write-only

MB6 : Transfer Request for Mailbox 6
bits : 6 - 6 (1 bit)
access : write-only

MB7 : Transfer Request for Mailbox 7
bits : 7 - 7 (1 bit)
access : write-only

TIMRST : Timer Reset
bits : 31 - 31 (1 bit)
access : write-only


MMR2

Mailbox Mode Register (MB = 2)
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMR2 MMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMEMARK PRIOR MOT

MTIMEMARK : Mailbox Timemark
bits : 0 - 15 (16 bit)
access : read-write

PRIOR : Mailbox Priority
bits : 16 - 19 (4 bit)
access : read-write

MOT : Mailbox Object Type
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x0 : MB_DISABLED

Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.

0x1 : MB_RX

Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.

0x2 : MB_RX_OVERWRITE

Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.

0x3 : MB_TX

Transmit mailbox. Mailbox is configured for transmission.

0x4 : MB_CONSUMER

Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.

0x5 : MB_PRODUCER

Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

End of enumeration elements list.


MAM2

Mailbox Acceptance Mask Register (MB = 2)
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAM2 MAM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIDvB MIDvA MIDE

MIDvB : Complementary bits for identifier in extended frame mode
bits : 0 - 17 (18 bit)
access : read-write

MIDvA : Identifier for standard frame mode
bits : 18 - 28 (11 bit)
access : read-write

MIDE : Identifier Version
bits : 29 - 29 (1 bit)
access : read-write


MID2

Mailbox ID Register (MB = 2)
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MID2 MID2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIDvB MIDvA MIDE

MIDvB : Complementary bits for identifier in extended frame mode
bits : 0 - 17 (18 bit)
access : read-write

MIDvA : Identifier for standard frame mode
bits : 18 - 28 (11 bit)
access : read-write

MIDE : Identifier Version
bits : 29 - 29 (1 bit)
access : read-write


MFID2

Mailbox Family ID Register (MB = 2)
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MFID2 MFID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFID

MFID : Family ID
bits : 0 - 28 (29 bit)
access : read-only


MSR2

Mailbox Status Register (MB = 2)
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSR2 MSR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMESTAMP MDLC MRTR MABT MRDY MMI

MTIMESTAMP : Timer value
bits : 0 - 15 (16 bit)
access : read-only

MDLC : Mailbox Data Length Code
bits : 16 - 19 (4 bit)
access : read-only

MRTR : Mailbox Remote Transmission Request
bits : 20 - 20 (1 bit)
access : read-only

MABT : Mailbox Message Abort
bits : 22 - 22 (1 bit)
access : read-only

MRDY : Mailbox Ready
bits : 23 - 23 (1 bit)
access : read-only

MMI : Mailbox Message Ignored
bits : 24 - 24 (1 bit)
access : read-only


MDL2

Mailbox Data Low Register (MB = 2)
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDL2 MDL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDL

MDL : Message Data Low Value
bits : 0 - 31 (32 bit)
access : read-write


MDH2

Mailbox Data High Register (MB = 2)
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDH2 MDH2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDH

MDH : Message Data High Value
bits : 0 - 31 (32 bit)
access : read-write


MCR2

Mailbox Control Register (MB = 2)
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MCR2 MCR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDLC MRTR MACR MTCR

MDLC : Mailbox Data Length Code
bits : 16 - 19 (4 bit)
access : write-only

MRTR : Mailbox Remote Transmission Request
bits : 20 - 20 (1 bit)
access : write-only

MACR : Abort Request for Mailbox x
bits : 22 - 22 (1 bit)
access : write-only

MTCR : Mailbox Transfer Command
bits : 23 - 23 (1 bit)
access : write-only


MMR3

Mailbox Mode Register (MB = 3)
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMR3 MMR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMEMARK PRIOR MOT

MTIMEMARK : Mailbox Timemark
bits : 0 - 15 (16 bit)
access : read-write

PRIOR : Mailbox Priority
bits : 16 - 19 (4 bit)
access : read-write

MOT : Mailbox Object Type
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x0 : MB_DISABLED

Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.

0x1 : MB_RX

Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.

0x2 : MB_RX_OVERWRITE

Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.

0x3 : MB_TX

Transmit mailbox. Mailbox is configured for transmission.

0x4 : MB_CONSUMER

Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.

0x5 : MB_PRODUCER

Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

End of enumeration elements list.


MAM3

Mailbox Acceptance Mask Register (MB = 3)
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAM3 MAM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIDvB MIDvA MIDE

MIDvB : Complementary bits for identifier in extended frame mode
bits : 0 - 17 (18 bit)
access : read-write

MIDvA : Identifier for standard frame mode
bits : 18 - 28 (11 bit)
access : read-write

MIDE : Identifier Version
bits : 29 - 29 (1 bit)
access : read-write


MID3

Mailbox ID Register (MB = 3)
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MID3 MID3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIDvB MIDvA MIDE

MIDvB : Complementary bits for identifier in extended frame mode
bits : 0 - 17 (18 bit)
access : read-write

MIDvA : Identifier for standard frame mode
bits : 18 - 28 (11 bit)
access : read-write

MIDE : Identifier Version
bits : 29 - 29 (1 bit)
access : read-write


MFID3

Mailbox Family ID Register (MB = 3)
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MFID3 MFID3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFID

MFID : Family ID
bits : 0 - 28 (29 bit)
access : read-only


MSR3

Mailbox Status Register (MB = 3)
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSR3 MSR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMESTAMP MDLC MRTR MABT MRDY MMI

MTIMESTAMP : Timer value
bits : 0 - 15 (16 bit)
access : read-only

MDLC : Mailbox Data Length Code
bits : 16 - 19 (4 bit)
access : read-only

MRTR : Mailbox Remote Transmission Request
bits : 20 - 20 (1 bit)
access : read-only

MABT : Mailbox Message Abort
bits : 22 - 22 (1 bit)
access : read-only

MRDY : Mailbox Ready
bits : 23 - 23 (1 bit)
access : read-only

MMI : Mailbox Message Ignored
bits : 24 - 24 (1 bit)
access : read-only


MDL3

Mailbox Data Low Register (MB = 3)
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDL3 MDL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDL

MDL : Message Data Low Value
bits : 0 - 31 (32 bit)
access : read-write


MDH3

Mailbox Data High Register (MB = 3)
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDH3 MDH3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDH

MDH : Message Data High Value
bits : 0 - 31 (32 bit)
access : read-write


MCR3

Mailbox Control Register (MB = 3)
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MCR3 MCR3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDLC MRTR MACR MTCR

MDLC : Mailbox Data Length Code
bits : 16 - 19 (4 bit)
access : write-only

MRTR : Mailbox Remote Transmission Request
bits : 20 - 20 (1 bit)
access : write-only

MACR : Abort Request for Mailbox x
bits : 22 - 22 (1 bit)
access : write-only

MTCR : Mailbox Transfer Command
bits : 23 - 23 (1 bit)
access : write-only


ACR

Abort Command Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ACR ACR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7

MB0 : Abort Request for Mailbox 0
bits : 0 - 0 (1 bit)
access : write-only

MB1 : Abort Request for Mailbox 1
bits : 1 - 1 (1 bit)
access : write-only

MB2 : Abort Request for Mailbox 2
bits : 2 - 2 (1 bit)
access : write-only

MB3 : Abort Request for Mailbox 3
bits : 3 - 3 (1 bit)
access : write-only

MB4 : Abort Request for Mailbox 4
bits : 4 - 4 (1 bit)
access : write-only

MB5 : Abort Request for Mailbox 5
bits : 5 - 5 (1 bit)
access : write-only

MB6 : Abort Request for Mailbox 6
bits : 6 - 6 (1 bit)
access : write-only

MB7 : Abort Request for Mailbox 7
bits : 7 - 7 (1 bit)
access : write-only


MMR4

Mailbox Mode Register (MB = 4)
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMR4 MMR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMEMARK PRIOR MOT

MTIMEMARK : Mailbox Timemark
bits : 0 - 15 (16 bit)
access : read-write

PRIOR : Mailbox Priority
bits : 16 - 19 (4 bit)
access : read-write

MOT : Mailbox Object Type
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x0 : MB_DISABLED

Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.

0x1 : MB_RX

Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.

0x2 : MB_RX_OVERWRITE

Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.

0x3 : MB_TX

Transmit mailbox. Mailbox is configured for transmission.

0x4 : MB_CONSUMER

Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.

0x5 : MB_PRODUCER

Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

End of enumeration elements list.


MAM4

Mailbox Acceptance Mask Register (MB = 4)
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAM4 MAM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIDvB MIDvA MIDE

MIDvB : Complementary bits for identifier in extended frame mode
bits : 0 - 17 (18 bit)
access : read-write

MIDvA : Identifier for standard frame mode
bits : 18 - 28 (11 bit)
access : read-write

MIDE : Identifier Version
bits : 29 - 29 (1 bit)
access : read-write


MID4

Mailbox ID Register (MB = 4)
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MID4 MID4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIDvB MIDvA MIDE

MIDvB : Complementary bits for identifier in extended frame mode
bits : 0 - 17 (18 bit)
access : read-write

MIDvA : Identifier for standard frame mode
bits : 18 - 28 (11 bit)
access : read-write

MIDE : Identifier Version
bits : 29 - 29 (1 bit)
access : read-write


MFID4

Mailbox Family ID Register (MB = 4)
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MFID4 MFID4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFID

MFID : Family ID
bits : 0 - 28 (29 bit)
access : read-only


MSR4

Mailbox Status Register (MB = 4)
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSR4 MSR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMESTAMP MDLC MRTR MABT MRDY MMI

MTIMESTAMP : Timer value
bits : 0 - 15 (16 bit)
access : read-only

MDLC : Mailbox Data Length Code
bits : 16 - 19 (4 bit)
access : read-only

MRTR : Mailbox Remote Transmission Request
bits : 20 - 20 (1 bit)
access : read-only

MABT : Mailbox Message Abort
bits : 22 - 22 (1 bit)
access : read-only

MRDY : Mailbox Ready
bits : 23 - 23 (1 bit)
access : read-only

MMI : Mailbox Message Ignored
bits : 24 - 24 (1 bit)
access : read-only


MDL4

Mailbox Data Low Register (MB = 4)
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDL4 MDL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDL

MDL : Message Data Low Value
bits : 0 - 31 (32 bit)
access : read-write


MDH4

Mailbox Data High Register (MB = 4)
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDH4 MDH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDH

MDH : Message Data High Value
bits : 0 - 31 (32 bit)
access : read-write


MCR4

Mailbox Control Register (MB = 4)
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MCR4 MCR4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDLC MRTR MACR MTCR

MDLC : Mailbox Data Length Code
bits : 16 - 19 (4 bit)
access : write-only

MRTR : Mailbox Remote Transmission Request
bits : 20 - 20 (1 bit)
access : write-only

MACR : Abort Request for Mailbox x
bits : 22 - 22 (1 bit)
access : write-only

MTCR : Mailbox Transfer Command
bits : 23 - 23 (1 bit)
access : write-only


MMR5

Mailbox Mode Register (MB = 5)
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMR5 MMR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMEMARK PRIOR MOT

MTIMEMARK : Mailbox Timemark
bits : 0 - 15 (16 bit)
access : read-write

PRIOR : Mailbox Priority
bits : 16 - 19 (4 bit)
access : read-write

MOT : Mailbox Object Type
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x0 : MB_DISABLED

Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.

0x1 : MB_RX

Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.

0x2 : MB_RX_OVERWRITE

Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.

0x3 : MB_TX

Transmit mailbox. Mailbox is configured for transmission.

0x4 : MB_CONSUMER

Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.

0x5 : MB_PRODUCER

Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

End of enumeration elements list.


MAM5

Mailbox Acceptance Mask Register (MB = 5)
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAM5 MAM5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIDvB MIDvA MIDE

MIDvB : Complementary bits for identifier in extended frame mode
bits : 0 - 17 (18 bit)
access : read-write

MIDvA : Identifier for standard frame mode
bits : 18 - 28 (11 bit)
access : read-write

MIDE : Identifier Version
bits : 29 - 29 (1 bit)
access : read-write


MID5

Mailbox ID Register (MB = 5)
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MID5 MID5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIDvB MIDvA MIDE

MIDvB : Complementary bits for identifier in extended frame mode
bits : 0 - 17 (18 bit)
access : read-write

MIDvA : Identifier for standard frame mode
bits : 18 - 28 (11 bit)
access : read-write

MIDE : Identifier Version
bits : 29 - 29 (1 bit)
access : read-write


MFID5

Mailbox Family ID Register (MB = 5)
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MFID5 MFID5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFID

MFID : Family ID
bits : 0 - 28 (29 bit)
access : read-only


MSR5

Mailbox Status Register (MB = 5)
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSR5 MSR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMESTAMP MDLC MRTR MABT MRDY MMI

MTIMESTAMP : Timer value
bits : 0 - 15 (16 bit)
access : read-only

MDLC : Mailbox Data Length Code
bits : 16 - 19 (4 bit)
access : read-only

MRTR : Mailbox Remote Transmission Request
bits : 20 - 20 (1 bit)
access : read-only

MABT : Mailbox Message Abort
bits : 22 - 22 (1 bit)
access : read-only

MRDY : Mailbox Ready
bits : 23 - 23 (1 bit)
access : read-only

MMI : Mailbox Message Ignored
bits : 24 - 24 (1 bit)
access : read-only


MDL5

Mailbox Data Low Register (MB = 5)
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDL5 MDL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDL

MDL : Message Data Low Value
bits : 0 - 31 (32 bit)
access : read-write


MDH5

Mailbox Data High Register (MB = 5)
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDH5 MDH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDH

MDH : Message Data High Value
bits : 0 - 31 (32 bit)
access : read-write


MCR5

Mailbox Control Register (MB = 5)
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MCR5 MCR5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDLC MRTR MACR MTCR

MDLC : Mailbox Data Length Code
bits : 16 - 19 (4 bit)
access : write-only

MRTR : Mailbox Remote Transmission Request
bits : 20 - 20 (1 bit)
access : write-only

MACR : Abort Request for Mailbox x
bits : 22 - 22 (1 bit)
access : write-only

MTCR : Mailbox Transfer Command
bits : 23 - 23 (1 bit)
access : write-only


MMR6

Mailbox Mode Register (MB = 6)
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMR6 MMR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMEMARK PRIOR MOT

MTIMEMARK : Mailbox Timemark
bits : 0 - 15 (16 bit)
access : read-write

PRIOR : Mailbox Priority
bits : 16 - 19 (4 bit)
access : read-write

MOT : Mailbox Object Type
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x0 : MB_DISABLED

Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.

0x1 : MB_RX

Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.

0x2 : MB_RX_OVERWRITE

Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.

0x3 : MB_TX

Transmit mailbox. Mailbox is configured for transmission.

0x4 : MB_CONSUMER

Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.

0x5 : MB_PRODUCER

Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

End of enumeration elements list.


MAM6

Mailbox Acceptance Mask Register (MB = 6)
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAM6 MAM6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIDvB MIDvA MIDE

MIDvB : Complementary bits for identifier in extended frame mode
bits : 0 - 17 (18 bit)
access : read-write

MIDvA : Identifier for standard frame mode
bits : 18 - 28 (11 bit)
access : read-write

MIDE : Identifier Version
bits : 29 - 29 (1 bit)
access : read-write


MID6

Mailbox ID Register (MB = 6)
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MID6 MID6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIDvB MIDvA MIDE

MIDvB : Complementary bits for identifier in extended frame mode
bits : 0 - 17 (18 bit)
access : read-write

MIDvA : Identifier for standard frame mode
bits : 18 - 28 (11 bit)
access : read-write

MIDE : Identifier Version
bits : 29 - 29 (1 bit)
access : read-write


MFID6

Mailbox Family ID Register (MB = 6)
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MFID6 MFID6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFID

MFID : Family ID
bits : 0 - 28 (29 bit)
access : read-only


MSR6

Mailbox Status Register (MB = 6)
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSR6 MSR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMESTAMP MDLC MRTR MABT MRDY MMI

MTIMESTAMP : Timer value
bits : 0 - 15 (16 bit)
access : read-only

MDLC : Mailbox Data Length Code
bits : 16 - 19 (4 bit)
access : read-only

MRTR : Mailbox Remote Transmission Request
bits : 20 - 20 (1 bit)
access : read-only

MABT : Mailbox Message Abort
bits : 22 - 22 (1 bit)
access : read-only

MRDY : Mailbox Ready
bits : 23 - 23 (1 bit)
access : read-only

MMI : Mailbox Message Ignored
bits : 24 - 24 (1 bit)
access : read-only


MDL6

Mailbox Data Low Register (MB = 6)
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDL6 MDL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDL

MDL : Message Data Low Value
bits : 0 - 31 (32 bit)
access : read-write


MDH6

Mailbox Data High Register (MB = 6)
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDH6 MDH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDH

MDH : Message Data High Value
bits : 0 - 31 (32 bit)
access : read-write


MCR6

Mailbox Control Register (MB = 6)
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MCR6 MCR6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDLC MRTR MACR MTCR

MDLC : Mailbox Data Length Code
bits : 16 - 19 (4 bit)
access : write-only

MRTR : Mailbox Remote Transmission Request
bits : 20 - 20 (1 bit)
access : write-only

MACR : Abort Request for Mailbox x
bits : 22 - 22 (1 bit)
access : write-only

MTCR : Mailbox Transfer Command
bits : 23 - 23 (1 bit)
access : write-only


MMR7

Mailbox Mode Register (MB = 7)
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMR7 MMR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMEMARK PRIOR MOT

MTIMEMARK : Mailbox Timemark
bits : 0 - 15 (16 bit)
access : read-write

PRIOR : Mailbox Priority
bits : 16 - 19 (4 bit)
access : read-write

MOT : Mailbox Object Type
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x0 : MB_DISABLED

Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.

0x1 : MB_RX

Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.

0x2 : MB_RX_OVERWRITE

Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.

0x3 : MB_TX

Transmit mailbox. Mailbox is configured for transmission.

0x4 : MB_CONSUMER

Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.

0x5 : MB_PRODUCER

Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

End of enumeration elements list.


MAM7

Mailbox Acceptance Mask Register (MB = 7)
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAM7 MAM7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIDvB MIDvA MIDE

MIDvB : Complementary bits for identifier in extended frame mode
bits : 0 - 17 (18 bit)
access : read-write

MIDvA : Identifier for standard frame mode
bits : 18 - 28 (11 bit)
access : read-write

MIDE : Identifier Version
bits : 29 - 29 (1 bit)
access : read-write


MID7

Mailbox ID Register (MB = 7)
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MID7 MID7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIDvB MIDvA MIDE

MIDvB : Complementary bits for identifier in extended frame mode
bits : 0 - 17 (18 bit)
access : read-write

MIDvA : Identifier for standard frame mode
bits : 18 - 28 (11 bit)
access : read-write

MIDE : Identifier Version
bits : 29 - 29 (1 bit)
access : read-write


MFID7

Mailbox Family ID Register (MB = 7)
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MFID7 MFID7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFID

MFID : Family ID
bits : 0 - 28 (29 bit)
access : read-only


MSR7

Mailbox Status Register (MB = 7)
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSR7 MSR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTIMESTAMP MDLC MRTR MABT MRDY MMI

MTIMESTAMP : Timer value
bits : 0 - 15 (16 bit)
access : read-only

MDLC : Mailbox Data Length Code
bits : 16 - 19 (4 bit)
access : read-only

MRTR : Mailbox Remote Transmission Request
bits : 20 - 20 (1 bit)
access : read-only

MABT : Mailbox Message Abort
bits : 22 - 22 (1 bit)
access : read-only

MRDY : Mailbox Ready
bits : 23 - 23 (1 bit)
access : read-only

MMI : Mailbox Message Ignored
bits : 24 - 24 (1 bit)
access : read-only


MDL7

Mailbox Data Low Register (MB = 7)
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDL7 MDL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDL

MDL : Message Data Low Value
bits : 0 - 31 (32 bit)
access : read-write


MDH7

Mailbox Data High Register (MB = 7)
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDH7 MDH7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDH

MDH : Message Data High Value
bits : 0 - 31 (32 bit)
access : read-write


MCR7

Mailbox Control Register (MB = 7)
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MCR7 MCR7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDLC MRTR MACR MTCR

MDLC : Mailbox Data Length Code
bits : 16 - 19 (4 bit)
access : write-only

MRTR : Mailbox Remote Transmission Request
bits : 20 - 20 (1 bit)
access : write-only

MACR : Abort Request for Mailbox x
bits : 22 - 22 (1 bit)
access : write-only

MTCR : Mailbox Transfer Command
bits : 23 - 23 (1 bit)
access : write-only


IER

Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7 ERRA WARN ERRP BOFF SLEEP WAKEUP TOVF TSTP CERR SERR AERR FERR BERR

MB0 : Mailbox 0 Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

MB1 : Mailbox 1 Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

MB2 : Mailbox 2 Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

MB3 : Mailbox 3 Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

MB4 : Mailbox 4 Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

MB5 : Mailbox 5 Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

MB6 : Mailbox 6 Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

MB7 : Mailbox 7 Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

ERRA : Error Active Mode Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only

WARN : Warning Limit Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only

ERRP : Error Passive Mode Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

BOFF : Bus Off Mode Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only

SLEEP : Sleep Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only

WAKEUP : Wakeup Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only

TOVF : Timer Overflow Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only

TSTP : TimeStamp Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only

CERR : CRC Error Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only

SERR : Stuffing Error Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only

AERR : Acknowledgment Error Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only

FERR : Form Error Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only

BERR : Bit Error Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only


IDR

Interrupt Disable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7 ERRA WARN ERRP BOFF SLEEP WAKEUP TOVF TSTP CERR SERR AERR FERR BERR

MB0 : Mailbox 0 Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

MB1 : Mailbox 1 Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

MB2 : Mailbox 2 Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

MB3 : Mailbox 3 Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

MB4 : Mailbox 4 Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

MB5 : Mailbox 5 Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

MB6 : Mailbox 6 Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

MB7 : Mailbox 7 Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

ERRA : Error Active Mode Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only

WARN : Warning Limit Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only

ERRP : Error Passive Mode Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

BOFF : Bus Off Mode Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only

SLEEP : Sleep Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only

WAKEUP : Wakeup Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only

TOVF : Timer Overflow Interrupt
bits : 22 - 22 (1 bit)
access : write-only

TSTP : TimeStamp Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only

CERR : CRC Error Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only

SERR : Stuffing Error Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only

AERR : Acknowledgment Error Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only

FERR : Form Error Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only

BERR : Bit Error Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only


IMR

Interrupt Mask Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7 ERRA WARN ERRP BOFF SLEEP WAKEUP TOVF TSTP CERR SERR AERR FERR BERR

MB0 : Mailbox 0 Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

MB1 : Mailbox 1 Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

MB2 : Mailbox 2 Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

MB3 : Mailbox 3 Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only

MB4 : Mailbox 4 Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only

MB5 : Mailbox 5 Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

MB6 : Mailbox 6 Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only

MB7 : Mailbox 7 Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only

ERRA : Error Active Mode Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only

WARN : Warning Limit Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only

ERRP : Error Passive Mode Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only

BOFF : Bus Off Mode Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only

SLEEP : Sleep Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only

WAKEUP : Wakeup Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only

TOVF : Timer Overflow Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only

TSTP : Timestamp Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only

CERR : CRC Error Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only

SERR : Stuffing Error Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only

AERR : Acknowledgment Error Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only

FERR : Form Error Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only

BERR : Bit Error Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only


WPMR

Write Protect Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : SPI Write Protection Key Password
bits : 8 - 31 (24 bit)
access : read-write


WPSR

Write Protect Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protection Violation Source
bits : 8 - 15 (8 bit)
access : read-only



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