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SYSC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xE8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

TIMALR

CALALR

SR

SCCR

IER

IDR

IMR

VER

MR

TIMR

CALR

WPMR


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPDTIM UPDCAL TIMEVSEL CALEVSEL

UPDTIM : Update Request Time Register
bits : 0 - 0 (1 bit)
access : read-write

UPDCAL : Update Request Calendar Register
bits : 1 - 1 (1 bit)
access : read-write

TIMEVSEL : Time Event Selection
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : MINUTE

Minute change

0x1 : HOUR

Hour change

0x2 : MIDNIGHT

Every day at midnight

0x3 : NOON

Every day at noon

End of enumeration elements list.

CALEVSEL : Calendar Event Selection
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : WEEK

Week change (every Monday at time 00:00:00)

0x1 : MONTH

Month change (every 01 of each month at time 00:00:00)

0x2 : YEAR

Year change (every January 1 at time 00:00:00)

End of enumeration elements list.


TIMALR

Time Alarm Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMALR TIMALR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEC SECEN MIN MINEN HOUR AMPM HOUREN

SEC : Second Alarm
bits : 0 - 6 (7 bit)
access : read-write

SECEN : Second Alarm Enable
bits : 7 - 7 (1 bit)
access : read-write

MIN : Minute Alarm
bits : 8 - 14 (7 bit)
access : read-write

MINEN : Minute Alarm Enable
bits : 15 - 15 (1 bit)
access : read-write

HOUR : Hour Alarm
bits : 16 - 21 (6 bit)
access : read-write

AMPM : AM/PM Indicator
bits : 22 - 22 (1 bit)
access : read-write

HOUREN : Hour Alarm Enable
bits : 23 - 23 (1 bit)
access : read-write


CALALR

Calendar Alarm Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALALR CALALR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MONTH MTHEN DATE DATEEN

MONTH : Month Alarm
bits : 16 - 20 (5 bit)
access : read-write

MTHEN : Month Alarm Enable
bits : 23 - 23 (1 bit)
access : read-write

DATE : Date Alarm
bits : 24 - 29 (6 bit)
access : read-write

DATEEN : Date Alarm Enable
bits : 31 - 31 (1 bit)
access : read-write


SR

Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACKUPD ALARM SEC TIMEV CALEV

ACKUPD : Acknowledge for Update
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : FREERUN

Time and calendar registers cannot be updated.

1 : UPDATE

Time and calendar registers can be updated.

End of enumeration elements list.

ALARM : Alarm Flag
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : NO_ALARMEVENT

No alarm matching condition occurred.

1 : ALARMEVENT

An alarm matching condition has occurred.

End of enumeration elements list.

SEC : Second Event
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

0 : NO_SECEVENT

No second event has occurred since the last clear.

1 : SECEVENT

At least one second event has occurred since the last clear.

End of enumeration elements list.

TIMEV : Time Event
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0 : NO_TIMEVENT

No time event has occurred since the last clear.

1 : TIMEVENT

At least one time event has occurred since the last clear.

End of enumeration elements list.

CALEV : Calendar Event
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

0 : NO_CALEVENT

No calendar event has occurred since the last clear.

1 : CALEVENT

At least one calendar event has occurred since the last clear.

End of enumeration elements list.


SCCR

Status Clear Command Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCCR SCCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACKCLR ALRCLR SECCLR TIMCLR CALCLR

ACKCLR : Acknowledge Clear
bits : 0 - 0 (1 bit)
access : write-only

ALRCLR : Alarm Clear
bits : 1 - 1 (1 bit)
access : write-only

SECCLR : Second Clear
bits : 2 - 2 (1 bit)
access : write-only

TIMCLR : Time Clear
bits : 3 - 3 (1 bit)
access : write-only

CALCLR : Calendar Clear
bits : 4 - 4 (1 bit)
access : write-only


IER

Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACKEN ALREN SECEN TIMEN CALEN

ACKEN : Acknowledge Update Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

ALREN : Alarm Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

SECEN : Second Event Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

TIMEN : Time Event Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

CALEN : Calendar Event Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only


IDR

Interrupt Disable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACKDIS ALRDIS SECDIS TIMDIS CALDIS

ACKDIS : Acknowledge Update Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

ALRDIS : Alarm Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

SECDIS : Second Event Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

TIMDIS : Time Event Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

CALDIS : Calendar Event Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only


IMR

Interrupt Mask Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACK ALR SEC TIM CAL

ACK : Acknowledge Update Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

ALR : Alarm Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

SEC : Second Event Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

TIM : Time Event Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only

CAL : Calendar Event Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only


VER

Valid Entry Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VER VER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVTIM NVCAL NVTIMALR NVCALALR

NVTIM : Non-valid Time
bits : 0 - 0 (1 bit)
access : read-only

NVCAL : Non-valid Calendar
bits : 1 - 1 (1 bit)
access : read-only

NVTIMALR : Non-valid Time Alarm
bits : 2 - 2 (1 bit)
access : read-only

NVCALALR : Non-valid Calendar Alarm
bits : 3 - 3 (1 bit)
access : read-only


MR

Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HRMOD

HRMOD : 12-/24-hour Mode
bits : 0 - 0 (1 bit)
access : read-write


TIMR

Time Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMR TIMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEC MIN HOUR AMPM

SEC : Current Second
bits : 0 - 6 (7 bit)
access : read-write

MIN : Current Minute
bits : 8 - 14 (7 bit)
access : read-write

HOUR : Current Hour
bits : 16 - 21 (6 bit)
access : read-write

AMPM : Ante Meridiem Post Meridiem Indicator
bits : 22 - 22 (1 bit)
access : read-write


CALR

Calendar Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALR CALR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CENT YEAR MONTH DAY DATE

CENT : Current Century
bits : 0 - 6 (7 bit)
access : read-write

YEAR : Current Year
bits : 8 - 15 (8 bit)
access : read-write

MONTH : Current Month
bits : 16 - 20 (5 bit)
access : read-write

DAY : Current Day in Current Week
bits : 21 - 23 (3 bit)
access : read-write

DATE : Current Day in Current Month
bits : 24 - 29 (6 bit)
access : read-write


WPMR

Write Protect Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protect KEY
bits : 8 - 31 (24 bit)
access : read-write

Enumeration:

0x525443 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

End of enumeration elements list.



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