Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
SMC NFC Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAGESIZE : Page Size of the NAND Flash Device
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : PS512
Main area 512 Bytes
0x1 : PS1024
Main area 1024 Bytes
0x2 : PS2048
Main area 2048 Bytes
0x3 : PS4096
Main area 4096 Bytes
End of enumeration elements list.
WSPARE : Write Spare Area
bits : 8 - 8 (1 bit)
access : read-write
RSPARE : Read Spare Area
bits : 9 - 9 (1 bit)
access : read-write
EDGECTRL : Rising/Falling Edge Detection Control
bits : 12 - 12 (1 bit)
access : read-write
RBEDGE : Ready/Busy Signal Edge Detection
bits : 13 - 13 (1 bit)
access : read-write
DTOCYC : Data Timeout Cycle Number
bits : 16 - 19 (4 bit)
access : read-write
DTOMUL : Data Timeout Multiplier
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0x0 : X1
DTOCYC
0x1 : X16
DTOCYC x 16
0x2 : X128
DTOCYC x 128
0x3 : X256
DTOCYC x 256
0x4 : X1024
DTOCYC x 1024
0x5 : X4096
DTOCYC x 4096
0x6 : X65536
DTOCYC x 65536
0x7 : X1048576
DTOCYC x 1048576
End of enumeration elements list.
SMC NFC Interrupt Disable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RB_RISE : Ready Busy Rising Edge Detection Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
RB_FALL : Ready Busy Falling Edge Detection Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
XFRDONE : Transfer Done Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
CMDDONE : Command Done Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only
DTOE : Data Timeout Error Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only
UNDEF : Undefined Area Access Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only
AWB : Accessing While Busy Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only
NFCASE : NFC Access Size Error Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only
RB_EDGE0 : Ready/Busy Line 0 Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only
SMC Pulse Register (CS_number = 7)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write
NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write
NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write
NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write
SMC Cycle Register (CS_number = 7)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write
NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write
SMC Timings Register (CS_number = 7)
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCLR : CLE to REN Low Delay
bits : 0 - 3 (4 bit)
access : read-write
TADL : ALE to Data Start
bits : 4 - 7 (4 bit)
access : read-write
TAR : ALE to REN Low Delay
bits : 8 - 11 (4 bit)
access : read-write
OCMS : Off Chip Memory Scrambling Enable
bits : 12 - 12 (1 bit)
access : read-write
TRR : Ready to REN Low Delay
bits : 16 - 19 (4 bit)
access : read-write
TWB : WEN High to REN to Busy
bits : 24 - 27 (4 bit)
access : read-write
RBNSEL : Ready/Busy Line Selection
bits : 28 - 30 (3 bit)
access : read-write
NFSEL : NAND Flash Selection
bits : 31 - 31 (1 bit)
access : read-write
SMC Mode Register (CS_number = 7)
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_MODE : Selection of the Control Signal for Read Operation
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NCS_CTRL
The Read operation is controlled by the NCS signal.
1 : NRD_CTRL
The Read operation is controlled by the NRD signal.
End of enumeration elements list.
WRITE_MODE : Selection of the Control Signal for Write Operation
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NCS_CTRL
The Write operation is controller by the NCS signal.
1 : NWE_CTRL
The Write operation is controlled by the NWE signal.
End of enumeration elements list.
EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : DISABLED
Disabled
0x2 : FROZEN
Frozen Mode
0x3 : READY
Ready Mode
End of enumeration elements list.
BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write
DBW : Data Bus Width
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : BIT_8
8-bit bus
1 : BIT_16
16-bit bus
End of enumeration elements list.
TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write
TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write
SMC OCMS Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMSE : Static Memory Controller Scrambling Enable
bits : 0 - 0 (1 bit)
access : read-write
SRSE : SRAM Scrambling Enable
bits : 1 - 1 (1 bit)
access : read-write
SMC OCMS KEY1 Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY1 : Off Chip Memory Scrambling (OCMS) Key Part 1
bits : 0 - 31 (32 bit)
access : write-only
SMC OCMS KEY2 Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY2 : Off Chip Memory Scrambling (OCMS) Key Part 2
bits : 0 - 31 (32 bit)
access : write-only
SMC NFC Interrupt Mask Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RB_RISE : Ready Busy Rising Edge Detection Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
RB_FALL : Ready Busy Falling Edge Detection Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
XFRDONE : Transfer Done Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
CMDDONE : Command Done Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only
DTOE : Data Timeout Error Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only
UNDEF : Undefined Area Access Interrupt Mask5
bits : 21 - 21 (1 bit)
access : read-only
AWB : Accessing While Busy Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only
NFCASE : NFC Access Size Error Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only
RB_EDGE0 : Ready/Busy Line 0 Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only
SMC NFC Address Cycle Zero Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR_CYCLE0 : NAND Flash Array Address cycle 0
bits : 0 - 7 (8 bit)
access : read-write
SMC Bank Address Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BANK : Bank Identifier
bits : 0 - 2 (3 bit)
access : read-write
Write Protection Control Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WP_EN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : write-only
WP_KEY : Write Protection KEY Password
bits : 8 - 31 (24 bit)
access : write-only
Enumeration:
0x534D43 : PASSWD
Writing any other value in this field aborts the write operation of the WP_EN bit. Always reads as 0.
End of enumeration elements list.
Write Protection Status Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WP_VS : Write Protection Violation Status
bits : 0 - 3 (4 bit)
access : read-only
WP_VSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only
SMC ECC Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RST : Reset ECC
bits : 0 - 0 (1 bit)
access : write-only
SWRST : Software Reset
bits : 1 - 1 (1 bit)
access : write-only
SMC ECC Mode Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC_PAGESIZE : ECC Page Size
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : PS512
Main area 512 Words
0x1 : PS1024
Main area 1024 Words
0x2 : PS2048
Main area 2048 Words
0x3 : PS4096
Main area 4096 Words
End of enumeration elements list.
TYPCORREC : Type of Correction
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CPAGE
1 bit correction for a page of 512/1024/2048/4096 Bytes (for 8 or 16-bit NAND Flash)
0x1 : C256B
1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only)
0x2 : C512B
1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only)
End of enumeration elements list.
SMC ECC Status 1 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RECERR0 : Recoverable Error
bits : 0 - 0 (1 bit)
access : read-only
ECCERR0 : ECC Error
bits : 1 - 1 (1 bit)
access : read-only
MULERR0 : Multiple Error
bits : 2 - 2 (1 bit)
access : read-only
RECERR1 : Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes
bits : 4 - 4 (1 bit)
access : read-only
ECCERR1 : ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes
bits : 5 - 5 (1 bit)
access : read-only
MULERR1 : Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes
bits : 6 - 6 (1 bit)
access : read-only
RECERR2 : Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes
bits : 8 - 8 (1 bit)
access : read-only
ECCERR2 : ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes
bits : 9 - 9 (1 bit)
access : read-only
MULERR2 : Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes
bits : 10 - 10 (1 bit)
access : read-only
RECERR3 : Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes
bits : 12 - 12 (1 bit)
access : read-only
ECCERR3 : ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes
bits : 13 - 13 (1 bit)
access : read-only
MULERR3 : Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes
bits : 14 - 14 (1 bit)
access : read-only
RECERR4 : Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes
bits : 16 - 16 (1 bit)
access : read-only
ECCERR4 : ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes
bits : 17 - 17 (1 bit)
access : read-only
MULERR4 : Multiple Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes
bits : 18 - 18 (1 bit)
access : read-only
RECERR5 : Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes
bits : 20 - 20 (1 bit)
access : read-only
ECCERR5 : ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes
bits : 21 - 21 (1 bit)
access : read-only
MULERR5 : Multiple Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes
bits : 22 - 22 (1 bit)
access : read-only
RECERR6 : Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes
bits : 24 - 24 (1 bit)
access : read-only
ECCERR6 : ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes
bits : 25 - 25 (1 bit)
access : read-only
MULERR6 : Multiple Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes
bits : 26 - 26 (1 bit)
access : read-only
RECERR7 : Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes
bits : 28 - 28 (1 bit)
access : read-only
ECCERR7 : ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes
bits : 29 - 29 (1 bit)
access : read-only
MULERR7 : Multiple Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes
bits : 30 - 30 (1 bit)
access : read-only
SMC ECC Parity 0 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITADDR : Bit Address
bits : 0 - 3 (4 bit)
access : read-only
WORDADDR : Word Address
bits : 4 - 15 (12 bit)
access : read-only
SMC ECC Parity 0 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : W9BIT
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 11 (9 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 23 (12 bit)
access : read-only
SMC ECC Parity 0 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : W8BIT
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 10 (8 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 22 (11 bit)
access : read-only
SMC ECC parity 1 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NPARITY : Parity N
bits : 0 - 15 (16 bit)
access : read-only
SMC ECC parity 1 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : W9BIT
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 11 (9 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 23 (12 bit)
access : read-only
SMC ECC parity 1 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : W8BIT
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 10 (8 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 22 (11 bit)
access : read-only
SMC ECC status 2 Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RECERR8 : Recoverable Error in the page between the 2048th and the 2303rd bytes
bits : 0 - 0 (1 bit)
access : read-only
ECCERR8 : ECC Error in the page between the 2048th and the 2303rd bytes
bits : 1 - 1 (1 bit)
access : read-only
MULERR8 : Multiple Error in the page between the 2048th and the 2303rd bytes
bits : 2 - 2 (1 bit)
access : read-only
RECERR9 : Recoverable Error in the page between the 2304th and the 2559th bytes
bits : 4 - 4 (1 bit)
access : read-only
ECCERR9 : ECC Error in the page between the 2304th and the 2559th bytes
bits : 5 - 5 (1 bit)
access : read-only
MULERR9 : Multiple Error in the page between the 2304th and the 2559th bytes
bits : 6 - 6 (1 bit)
access : read-only
RECERR10 : Recoverable Error in the page between the 2560th and the 2815th bytes
bits : 8 - 8 (1 bit)
access : read-only
ECCERR10 : ECC Error in the page between the 2560th and the 2815th bytes
bits : 9 - 9 (1 bit)
access : read-only
MULERR10 : Multiple Error in the page between the 2560th and the 2815th bytes
bits : 10 - 10 (1 bit)
access : read-only
RECERR11 : Recoverable Error in the page between the 2816th and the 3071st bytes
bits : 12 - 12 (1 bit)
access : read-only
ECCERR11 : ECC Error in the page between the 2816th and the 3071st bytes
bits : 13 - 13 (1 bit)
access : read-only
MULERR11 : Multiple Error in the page between the 2816th and the 3071st bytes
bits : 14 - 14 (1 bit)
access : read-only
RECERR12 : Recoverable Error in the page between the 3072nd and the 3327th bytes
bits : 16 - 16 (1 bit)
access : read-only
ECCERR12 : ECC Error in the page between the 3072nd and the 3327th bytes
bits : 17 - 17 (1 bit)
access : read-only
MULERR12 : Multiple Error in the page between the 3072nd and the 3327th bytes
bits : 18 - 18 (1 bit)
access : read-only
RECERR13 : Recoverable Error in the page between the 3328th and the 3583rd bytes
bits : 20 - 20 (1 bit)
access : read-only
ECCERR13 : ECC Error in the page between the 3328th and the 3583rd bytes
bits : 21 - 21 (1 bit)
access : read-only
MULERR13 : Multiple Error in the page between the 3328th and the 3583rd bytes
bits : 22 - 22 (1 bit)
access : read-only
RECERR14 : Recoverable Error in the page between the 3584th and the 3839th bytes
bits : 24 - 24 (1 bit)
access : read-only
ECCERR14 : ECC Error in the page between the 3584th and the 3839th bytes
bits : 25 - 25 (1 bit)
access : read-only
MULERR14 : Multiple Error in the page between the 3584th and the 3839th bytes
bits : 26 - 26 (1 bit)
access : read-only
RECERR15 : Recoverable Error in the page between the 3840th and the 4095th bytes
bits : 28 - 28 (1 bit)
access : read-only
ECCERR15 : ECC Error in the page between the 3840th and the 4095th bytes
bits : 29 - 29 (1 bit)
access : read-only
MULERR15 : Multiple Error in the page between the 3840th and the 4095th bytes
bits : 30 - 30 (1 bit)
access : read-only
SMC ECC parity 2 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 11 (9 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 23 (12 bit)
access : read-only
SMC ECC parity 2 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : W8BIT
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 10 (8 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 22 (11 bit)
access : read-only
SMC ECC parity 3 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 11 (9 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 23 (12 bit)
access : read-only
SMC ECC parity 3 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : W8BIT
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 10 (8 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 22 (11 bit)
access : read-only
SMC NFC Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
NFCEN : NAND Flash Controller Enable
bits : 0 - 0 (1 bit)
access : write-only
NFCDIS : NAND Flash Controller Disable
bits : 1 - 1 (1 bit)
access : write-only
SMC ECC parity 4 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 11 (9 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 23 (12 bit)
access : read-only
SMC ECC parity 4 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : W8BIT
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 10 (8 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 22 (11 bit)
access : read-only
SMC ECC parity 5 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 11 (9 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 23 (12 bit)
access : read-only
SMC ECC parity 5 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : W8BIT
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 10 (8 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 22 (11 bit)
access : read-only
SMC ECC parity 6 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 11 (9 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 23 (12 bit)
access : read-only
SMC ECC parity 6 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : W8BIT
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 10 (8 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 22 (11 bit)
access : read-only
SMC ECC parity 7 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 11 (9 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 23 (12 bit)
access : read-only
SMC ECC parity 7 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : W8BIT
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 10 (8 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 22 (11 bit)
access : read-only
SMC ECC parity 8 Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 10 (8 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 22 (11 bit)
access : read-only
SMC ECC parity 9 Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 10 (8 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 22 (11 bit)
access : read-only
SMC ECC parity 10 Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 10 (8 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 22 (11 bit)
access : read-only
SMC ECC parity 11 Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 10 (8 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 22 (11 bit)
access : read-only
SMC ECC parity 12 Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 10 (8 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 22 (11 bit)
access : read-only
SMC ECC parity 13 Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 10 (8 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 22 (11 bit)
access : read-only
SMC ECC parity 14 Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 10 (8 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 22 (11 bit)
access : read-only
SMC ECC parity 15 Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITADDR : Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 0 - 2 (3 bit)
access : read-only
WORDADDR : Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes
bits : 3 - 10 (8 bit)
access : read-only
NPARITY : Parity N
bits : 12 - 22 (11 bit)
access : read-only
SMC Setup Register (CS_number = 0)
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write
NCS_WR_SETUP : NCS Setup Length in Write Access
bits : 8 - 13 (6 bit)
access : read-write
NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write
NCS_RD_SETUP : NCS Setup Length in Read Access
bits : 24 - 29 (6 bit)
access : read-write
SMC Pulse Register (CS_number = 0)
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write
NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write
NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write
NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write
SMC Cycle Register (CS_number = 0)
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write
NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write
SMC Timings Register (CS_number = 0)
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCLR : CLE to REN Low Delay
bits : 0 - 3 (4 bit)
access : read-write
TADL : ALE to Data Start
bits : 4 - 7 (4 bit)
access : read-write
TAR : ALE to REN Low Delay
bits : 8 - 11 (4 bit)
access : read-write
OCMS : Off Chip Memory Scrambling Enable
bits : 12 - 12 (1 bit)
access : read-write
TRR : Ready to REN Low Delay
bits : 16 - 19 (4 bit)
access : read-write
TWB : WEN High to REN to Busy
bits : 24 - 27 (4 bit)
access : read-write
RBNSEL : Ready/Busy Line Selection
bits : 28 - 30 (3 bit)
access : read-write
NFSEL : NAND Flash Selection
bits : 31 - 31 (1 bit)
access : read-write
SMC NFC Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SMCSTS : NAND Flash Controller status (this field cannot be reset)
bits : 0 - 0 (1 bit)
access : read-only
RB_RISE : Selected Ready Busy Rising Edge Detected
bits : 4 - 4 (1 bit)
access : read-only
RB_FALL : Selected Ready Busy Falling Edge Detected
bits : 5 - 5 (1 bit)
access : read-only
NFCBUSY : NFC Busy (this field cannot be reset)
bits : 8 - 8 (1 bit)
access : read-only
NFCWR : NFC Write/Read Operation (this field cannot be reset)
bits : 11 - 11 (1 bit)
access : read-only
NFCSID : NFC Chip Select ID (this field cannot be reset)
bits : 12 - 14 (3 bit)
access : read-only
XFRDONE : NFC Data Transfer Terminated
bits : 16 - 16 (1 bit)
access : read-only
CMDDONE : Command Done
bits : 17 - 17 (1 bit)
access : read-only
DTOE : Data Timeout Error
bits : 20 - 20 (1 bit)
access : read-only
UNDEF : Undefined Area Error
bits : 21 - 21 (1 bit)
access : read-only
AWB : Accessing While Busy
bits : 22 - 22 (1 bit)
access : read-only
NFCASE : NFC Access Size Error
bits : 23 - 23 (1 bit)
access : read-only
RB_EDGE0 : Ready/Busy Line 0 Edge Detected
bits : 24 - 24 (1 bit)
access : read-only
SMC Mode Register (CS_number = 0)
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_MODE : Selection of the Control Signal for Read Operation
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NCS_CTRL
The Read operation is controlled by the NCS signal.
1 : NRD_CTRL
The Read operation is controlled by the NRD signal.
End of enumeration elements list.
WRITE_MODE : Selection of the Control Signal for Write Operation
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NCS_CTRL
The Write operation is controller by the NCS signal.
1 : NWE_CTRL
The Write operation is controlled by the NWE signal.
End of enumeration elements list.
EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : DISABLED
Disabled
0x2 : FROZEN
Frozen Mode
0x3 : READY
Ready Mode
End of enumeration elements list.
BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write
DBW : Data Bus Width
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : BIT_8
8-bit bus
1 : BIT_16
16-bit bus
End of enumeration elements list.
TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write
TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write
SMC Setup Register (CS_number = 1)
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write
NCS_WR_SETUP : NCS Setup Length in Write Access
bits : 8 - 13 (6 bit)
access : read-write
NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write
NCS_RD_SETUP : NCS Setup Length in Read Access
bits : 24 - 29 (6 bit)
access : read-write
SMC Pulse Register (CS_number = 1)
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write
NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write
NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write
NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write
SMC Cycle Register (CS_number = 1)
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write
NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write
SMC Timings Register (CS_number = 1)
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCLR : CLE to REN Low Delay
bits : 0 - 3 (4 bit)
access : read-write
TADL : ALE to Data Start
bits : 4 - 7 (4 bit)
access : read-write
TAR : ALE to REN Low Delay
bits : 8 - 11 (4 bit)
access : read-write
OCMS : Off Chip Memory Scrambling Enable
bits : 12 - 12 (1 bit)
access : read-write
TRR : Ready to REN Low Delay
bits : 16 - 19 (4 bit)
access : read-write
TWB : WEN High to REN to Busy
bits : 24 - 27 (4 bit)
access : read-write
RBNSEL : Ready/Busy Line Selection
bits : 28 - 30 (3 bit)
access : read-write
NFSEL : NAND Flash Selection
bits : 31 - 31 (1 bit)
access : read-write
SMC Mode Register (CS_number = 1)
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_MODE : Selection of the Control Signal for Read Operation
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NCS_CTRL
The Read operation is controlled by the NCS signal.
1 : NRD_CTRL
The Read operation is controlled by the NRD signal.
End of enumeration elements list.
WRITE_MODE : Selection of the Control Signal for Write Operation
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NCS_CTRL
The Write operation is controller by the NCS signal.
1 : NWE_CTRL
The Write operation is controlled by the NWE signal.
End of enumeration elements list.
EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : DISABLED
Disabled
0x2 : FROZEN
Frozen Mode
0x3 : READY
Ready Mode
End of enumeration elements list.
BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write
DBW : Data Bus Width
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : BIT_8
8-bit bus
1 : BIT_16
16-bit bus
End of enumeration elements list.
TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write
TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write
SMC Setup Register (CS_number = 2)
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write
NCS_WR_SETUP : NCS Setup Length in Write Access
bits : 8 - 13 (6 bit)
access : read-write
NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write
NCS_RD_SETUP : NCS Setup Length in Read Access
bits : 24 - 29 (6 bit)
access : read-write
SMC Pulse Register (CS_number = 2)
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write
NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write
NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write
NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write
SMC Cycle Register (CS_number = 2)
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write
NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write
SMC Timings Register (CS_number = 2)
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCLR : CLE to REN Low Delay
bits : 0 - 3 (4 bit)
access : read-write
TADL : ALE to Data Start
bits : 4 - 7 (4 bit)
access : read-write
TAR : ALE to REN Low Delay
bits : 8 - 11 (4 bit)
access : read-write
OCMS : Off Chip Memory Scrambling Enable
bits : 12 - 12 (1 bit)
access : read-write
TRR : Ready to REN Low Delay
bits : 16 - 19 (4 bit)
access : read-write
TWB : WEN High to REN to Busy
bits : 24 - 27 (4 bit)
access : read-write
RBNSEL : Ready/Busy Line Selection
bits : 28 - 30 (3 bit)
access : read-write
NFSEL : NAND Flash Selection
bits : 31 - 31 (1 bit)
access : read-write
SMC Mode Register (CS_number = 2)
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_MODE : Selection of the Control Signal for Read Operation
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NCS_CTRL
The Read operation is controlled by the NCS signal.
1 : NRD_CTRL
The Read operation is controlled by the NRD signal.
End of enumeration elements list.
WRITE_MODE : Selection of the Control Signal for Write Operation
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NCS_CTRL
The Write operation is controller by the NCS signal.
1 : NWE_CTRL
The Write operation is controlled by the NWE signal.
End of enumeration elements list.
EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : DISABLED
Disabled
0x2 : FROZEN
Frozen Mode
0x3 : READY
Ready Mode
End of enumeration elements list.
BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write
DBW : Data Bus Width
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : BIT_8
8-bit bus
1 : BIT_16
16-bit bus
End of enumeration elements list.
TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write
TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write
SMC Setup Register (CS_number = 3)
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write
NCS_WR_SETUP : NCS Setup Length in Write Access
bits : 8 - 13 (6 bit)
access : read-write
NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write
NCS_RD_SETUP : NCS Setup Length in Read Access
bits : 24 - 29 (6 bit)
access : read-write
SMC Pulse Register (CS_number = 3)
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write
NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write
NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write
NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write
SMC Cycle Register (CS_number = 3)
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write
NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write
SMC Timings Register (CS_number = 3)
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCLR : CLE to REN Low Delay
bits : 0 - 3 (4 bit)
access : read-write
TADL : ALE to Data Start
bits : 4 - 7 (4 bit)
access : read-write
TAR : ALE to REN Low Delay
bits : 8 - 11 (4 bit)
access : read-write
OCMS : Off Chip Memory Scrambling Enable
bits : 12 - 12 (1 bit)
access : read-write
TRR : Ready to REN Low Delay
bits : 16 - 19 (4 bit)
access : read-write
TWB : WEN High to REN to Busy
bits : 24 - 27 (4 bit)
access : read-write
RBNSEL : Ready/Busy Line Selection
bits : 28 - 30 (3 bit)
access : read-write
NFSEL : NAND Flash Selection
bits : 31 - 31 (1 bit)
access : read-write
SMC Mode Register (CS_number = 3)
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_MODE : Selection of the Control Signal for Read Operation
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NCS_CTRL
The Read operation is controlled by the NCS signal.
1 : NRD_CTRL
The Read operation is controlled by the NRD signal.
End of enumeration elements list.
WRITE_MODE : Selection of the Control Signal for Write Operation
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NCS_CTRL
The Write operation is controller by the NCS signal.
1 : NWE_CTRL
The Write operation is controlled by the NWE signal.
End of enumeration elements list.
EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : DISABLED
Disabled
0x2 : FROZEN
Frozen Mode
0x3 : READY
Ready Mode
End of enumeration elements list.
BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write
DBW : Data Bus Width
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : BIT_8
8-bit bus
1 : BIT_16
16-bit bus
End of enumeration elements list.
TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write
TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write
SMC NFC Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RB_RISE : Ready Busy Rising Edge Detection Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
RB_FALL : Ready Busy Falling Edge Detection Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
XFRDONE : Transfer Done Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
CMDDONE : Command Done Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only
DTOE : Data Timeout Error Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only
UNDEF : Undefined Area Access Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only
AWB : Accessing While Busy Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only
NFCASE : NFC Access Size Error Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only
RB_EDGE0 : Ready/Busy Line 0 Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only
SMC Setup Register (CS_number = 4)
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write
NCS_WR_SETUP : NCS Setup Length in Write Access
bits : 8 - 13 (6 bit)
access : read-write
NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write
NCS_RD_SETUP : NCS Setup Length in Read Access
bits : 24 - 29 (6 bit)
access : read-write
SMC Pulse Register (CS_number = 4)
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write
NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write
NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write
NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write
SMC Cycle Register (CS_number = 4)
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write
NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write
SMC Timings Register (CS_number = 4)
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCLR : CLE to REN Low Delay
bits : 0 - 3 (4 bit)
access : read-write
TADL : ALE to Data Start
bits : 4 - 7 (4 bit)
access : read-write
TAR : ALE to REN Low Delay
bits : 8 - 11 (4 bit)
access : read-write
OCMS : Off Chip Memory Scrambling Enable
bits : 12 - 12 (1 bit)
access : read-write
TRR : Ready to REN Low Delay
bits : 16 - 19 (4 bit)
access : read-write
TWB : WEN High to REN to Busy
bits : 24 - 27 (4 bit)
access : read-write
RBNSEL : Ready/Busy Line Selection
bits : 28 - 30 (3 bit)
access : read-write
NFSEL : NAND Flash Selection
bits : 31 - 31 (1 bit)
access : read-write
SMC Mode Register (CS_number = 4)
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_MODE : Selection of the Control Signal for Read Operation
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NCS_CTRL
The Read operation is controlled by the NCS signal.
1 : NRD_CTRL
The Read operation is controlled by the NRD signal.
End of enumeration elements list.
WRITE_MODE : Selection of the Control Signal for Write Operation
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NCS_CTRL
The Write operation is controller by the NCS signal.
1 : NWE_CTRL
The Write operation is controlled by the NWE signal.
End of enumeration elements list.
EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : DISABLED
Disabled
0x2 : FROZEN
Frozen Mode
0x3 : READY
Ready Mode
End of enumeration elements list.
BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write
DBW : Data Bus Width
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : BIT_8
8-bit bus
1 : BIT_16
16-bit bus
End of enumeration elements list.
TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write
TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write
SMC Setup Register (CS_number = 5)
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write
NCS_WR_SETUP : NCS Setup Length in Write Access
bits : 8 - 13 (6 bit)
access : read-write
NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write
NCS_RD_SETUP : NCS Setup Length in Read Access
bits : 24 - 29 (6 bit)
access : read-write
SMC Pulse Register (CS_number = 5)
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write
NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write
NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write
NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write
SMC Cycle Register (CS_number = 5)
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write
NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write
SMC Timings Register (CS_number = 5)
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCLR : CLE to REN Low Delay
bits : 0 - 3 (4 bit)
access : read-write
TADL : ALE to Data Start
bits : 4 - 7 (4 bit)
access : read-write
TAR : ALE to REN Low Delay
bits : 8 - 11 (4 bit)
access : read-write
OCMS : Off Chip Memory Scrambling Enable
bits : 12 - 12 (1 bit)
access : read-write
TRR : Ready to REN Low Delay
bits : 16 - 19 (4 bit)
access : read-write
TWB : WEN High to REN to Busy
bits : 24 - 27 (4 bit)
access : read-write
RBNSEL : Ready/Busy Line Selection
bits : 28 - 30 (3 bit)
access : read-write
NFSEL : NAND Flash Selection
bits : 31 - 31 (1 bit)
access : read-write
SMC Mode Register (CS_number = 5)
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_MODE : Selection of the Control Signal for Read Operation
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NCS_CTRL
The Read operation is controlled by the NCS signal.
1 : NRD_CTRL
The Read operation is controlled by the NRD signal.
End of enumeration elements list.
WRITE_MODE : Selection of the Control Signal for Write Operation
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NCS_CTRL
The Write operation is controller by the NCS signal.
1 : NWE_CTRL
The Write operation is controlled by the NWE signal.
End of enumeration elements list.
EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : DISABLED
Disabled
0x2 : FROZEN
Frozen Mode
0x3 : READY
Ready Mode
End of enumeration elements list.
BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write
DBW : Data Bus Width
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : BIT_8
8-bit bus
1 : BIT_16
16-bit bus
End of enumeration elements list.
TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write
TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write
SMC Setup Register (CS_number = 6)
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write
NCS_WR_SETUP : NCS Setup Length in Write Access
bits : 8 - 13 (6 bit)
access : read-write
NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write
NCS_RD_SETUP : NCS Setup Length in Read Access
bits : 24 - 29 (6 bit)
access : read-write
SMC Pulse Register (CS_number = 6)
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write
NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write
NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write
NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write
SMC Cycle Register (CS_number = 6)
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write
NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write
SMC Timings Register (CS_number = 6)
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCLR : CLE to REN Low Delay
bits : 0 - 3 (4 bit)
access : read-write
TADL : ALE to Data Start
bits : 4 - 7 (4 bit)
access : read-write
TAR : ALE to REN Low Delay
bits : 8 - 11 (4 bit)
access : read-write
OCMS : Off Chip Memory Scrambling Enable
bits : 12 - 12 (1 bit)
access : read-write
TRR : Ready to REN Low Delay
bits : 16 - 19 (4 bit)
access : read-write
TWB : WEN High to REN to Busy
bits : 24 - 27 (4 bit)
access : read-write
RBNSEL : Ready/Busy Line Selection
bits : 28 - 30 (3 bit)
access : read-write
NFSEL : NAND Flash Selection
bits : 31 - 31 (1 bit)
access : read-write
SMC Mode Register (CS_number = 6)
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_MODE : Selection of the Control Signal for Read Operation
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NCS_CTRL
The Read operation is controlled by the NCS signal.
1 : NRD_CTRL
The Read operation is controlled by the NRD signal.
End of enumeration elements list.
WRITE_MODE : Selection of the Control Signal for Write Operation
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NCS_CTRL
The Write operation is controller by the NCS signal.
1 : NWE_CTRL
The Write operation is controlled by the NWE signal.
End of enumeration elements list.
EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : DISABLED
Disabled
0x2 : FROZEN
Frozen Mode
0x3 : READY
Ready Mode
End of enumeration elements list.
BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write
DBW : Data Bus Width
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : BIT_8
8-bit bus
1 : BIT_16
16-bit bus
End of enumeration elements list.
TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write
TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write
SMC Setup Register (CS_number = 7)
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write
NCS_WR_SETUP : NCS Setup Length in Write Access
bits : 8 - 13 (6 bit)
access : read-write
NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write
NCS_RD_SETUP : NCS Setup Length in Read Access
bits : 24 - 29 (6 bit)
access : read-write
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