\n
address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
SMC Setup Register (CS_number = 0)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write
NCS_WR_SETUP : NCS Setup Length in WRITE Access
bits : 8 - 13 (6 bit)
access : read-write
NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write
NCS_RD_SETUP : NCS Setup Length in READ Access
bits : 24 - 29 (6 bit)
access : read-write
SMC Setup Register (CS_number = 1)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write
NCS_WR_SETUP : NCS Setup Length in WRITE Access
bits : 8 - 13 (6 bit)
access : read-write
NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write
NCS_RD_SETUP : NCS Setup Length in READ Access
bits : 24 - 29 (6 bit)
access : read-write
SMC Pulse Register (CS_number = 1)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write
NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write
NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write
NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write
SMC Cycle Register (CS_number = 1)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write
NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write
SMC Mode Register (CS_number = 1)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_MODE : Read Mode
bits : 0 - 0 (1 bit)
access : read-write
WRITE_MODE : Write Mode
bits : 1 - 1 (1 bit)
access : read-write
EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : DISABLED
Disabled
0x2 : FROZEN
Frozen Mode
0x3 : READY
Ready Mode
End of enumeration elements list.
TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write
TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write
PMEN : Page Mode Enabled
bits : 24 - 24 (1 bit)
access : read-write
PS : Page Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : 4_BYTE
4-byte page
0x1 : 8_BYTE
8-byte page
0x2 : 16_BYTE
16-byte page
0x3 : 32_BYTE
32-byte page
End of enumeration elements list.
SMC Setup Register (CS_number = 2)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write
NCS_WR_SETUP : NCS Setup Length in WRITE Access
bits : 8 - 13 (6 bit)
access : read-write
NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write
NCS_RD_SETUP : NCS Setup Length in READ Access
bits : 24 - 29 (6 bit)
access : read-write
SMC Pulse Register (CS_number = 2)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write
NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write
NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write
NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write
SMC Cycle Register (CS_number = 2)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write
NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write
SMC Mode Register (CS_number = 2)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_MODE : Read Mode
bits : 0 - 0 (1 bit)
access : read-write
WRITE_MODE : Write Mode
bits : 1 - 1 (1 bit)
access : read-write
EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : DISABLED
Disabled
0x2 : FROZEN
Frozen Mode
0x3 : READY
Ready Mode
End of enumeration elements list.
TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write
TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write
PMEN : Page Mode Enabled
bits : 24 - 24 (1 bit)
access : read-write
PS : Page Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : 4_BYTE
4-byte page
0x1 : 8_BYTE
8-byte page
0x2 : 16_BYTE
16-byte page
0x3 : 32_BYTE
32-byte page
End of enumeration elements list.
SMC Setup Register (CS_number = 3)
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write
NCS_WR_SETUP : NCS Setup Length in WRITE Access
bits : 8 - 13 (6 bit)
access : read-write
NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write
NCS_RD_SETUP : NCS Setup Length in READ Access
bits : 24 - 29 (6 bit)
access : read-write
SMC Pulse Register (CS_number = 3)
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write
NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write
NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write
NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write
SMC Cycle Register (CS_number = 3)
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write
NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write
SMC Mode Register (CS_number = 3)
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_MODE : Read Mode
bits : 0 - 0 (1 bit)
access : read-write
WRITE_MODE : Write Mode
bits : 1 - 1 (1 bit)
access : read-write
EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : DISABLED
Disabled
0x2 : FROZEN
Frozen Mode
0x3 : READY
Ready Mode
End of enumeration elements list.
TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write
TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write
PMEN : Page Mode Enabled
bits : 24 - 24 (1 bit)
access : read-write
PS : Page Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : 4_BYTE
4-byte page
0x1 : 8_BYTE
8-byte page
0x2 : 16_BYTE
16-byte page
0x3 : 32_BYTE
32-byte page
End of enumeration elements list.
SMC Pulse Register (CS_number = 0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write
NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write
NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write
NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write
SMC Cycle Register (CS_number = 0)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write
NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write
SMC OCMS MODE Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMSE : Static Memory Controller Scrambling Enable
bits : 0 - 0 (1 bit)
access : read-write
CS0SE : Chip Select (x = 0 to 3) Scrambling Enable
bits : 16 - 16 (1 bit)
access : read-write
CS1SE : Chip Select (x = 0 to 3) Scrambling Enable
bits : 17 - 17 (1 bit)
access : read-write
CS2SE : Chip Select (x = 0 to 3) Scrambling Enable
bits : 18 - 18 (1 bit)
access : read-write
CS3SE : Chip Select (x = 0 to 3) Scrambling Enable
bits : 19 - 19 (1 bit)
access : read-write
SMC OCMS KEY1 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY1 : Off Chip Memory Scrambling (OCMS) Key Part 1
bits : 0 - 31 (32 bit)
access : write-only
SMC OCMS KEY2 Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY2 : Off Chip Memory Scrambling (OCMS) Key Part 2
bits : 0 - 31 (32 bit)
access : write-only
SMC Mode Register (CS_number = 0)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_MODE : Read Mode
bits : 0 - 0 (1 bit)
access : read-write
WRITE_MODE : Write Mode
bits : 1 - 1 (1 bit)
access : read-write
EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : DISABLED
Disabled
0x2 : FROZEN
Frozen Mode
0x3 : READY
Ready Mode
End of enumeration elements list.
TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write
TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write
PMEN : Page Mode Enabled
bits : 24 - 24 (1 bit)
access : read-write
PS : Page Size
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : 4_BYTE
4-byte page
0x1 : 8_BYTE
8-byte page
0x2 : 16_BYTE
16-byte page
0x3 : 32_BYTE
32-byte page
End of enumeration elements list.
SMC Write Protect Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protect KEY
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
5459267 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
End of enumeration elements list.
SMC Write Protect Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protect Violation Source
bits : 8 - 23 (16 bit)
access : read-only
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