\n
address_offset : 0x0 Bytes (0x0)
size : 0x140 byte (0x0)
mem_usage : registers
protection : not protected
System Clock Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDP : USB Device Port Clock Enable
bits : 7 - 7 (1 bit)
access : write-only
PCK0 : Programmable Clock 0 Output Enable
bits : 8 - 8 (1 bit)
access : write-only
PCK1 : Programmable Clock 1 Output Enable
bits : 9 - 9 (1 bit)
access : write-only
PCK2 : Programmable Clock 2 Output Enable
bits : 10 - 10 (1 bit)
access : write-only
Peripheral Clock Enable Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PID8 : Peripheral Clock 8 Enable
bits : 8 - 8 (1 bit)
access : write-only
PID9 : Peripheral Clock 9 Enable
bits : 9 - 9 (1 bit)
access : write-only
PID10 : Peripheral Clock 10 Enable
bits : 10 - 10 (1 bit)
access : write-only
PID11 : Peripheral Clock 11 Enable
bits : 11 - 11 (1 bit)
access : write-only
PID12 : Peripheral Clock 12 Enable
bits : 12 - 12 (1 bit)
access : write-only
PID13 : Peripheral Clock 13 Enable
bits : 13 - 13 (1 bit)
access : write-only
PID14 : Peripheral Clock 14 Enable
bits : 14 - 14 (1 bit)
access : write-only
PID15 : Peripheral Clock 15 Enable
bits : 15 - 15 (1 bit)
access : write-only
PID16 : Peripheral Clock 16 Enable
bits : 16 - 16 (1 bit)
access : write-only
PID17 : Peripheral Clock 17 Enable
bits : 17 - 17 (1 bit)
access : write-only
PID18 : Peripheral Clock 18 Enable
bits : 18 - 18 (1 bit)
access : write-only
PID19 : Peripheral Clock 19 Enable
bits : 19 - 19 (1 bit)
access : write-only
PID20 : Peripheral Clock 20 Enable
bits : 20 - 20 (1 bit)
access : write-only
PID21 : Peripheral Clock 21 Enable
bits : 21 - 21 (1 bit)
access : write-only
PID22 : Peripheral Clock 22 Enable
bits : 22 - 22 (1 bit)
access : write-only
PID23 : Peripheral Clock 23 Enable
bits : 23 - 23 (1 bit)
access : write-only
PID24 : Peripheral Clock 24 Enable
bits : 24 - 24 (1 bit)
access : write-only
PID25 : Peripheral Clock 25 Enable
bits : 25 - 25 (1 bit)
access : write-only
PID26 : Peripheral Clock 26 Enable
bits : 26 - 26 (1 bit)
access : write-only
PID27 : Peripheral Clock 27 Enable
bits : 27 - 27 (1 bit)
access : write-only
PID28 : Peripheral Clock 28 Enable
bits : 28 - 28 (1 bit)
access : write-only
PID29 : Peripheral Clock 29 Enable
bits : 29 - 29 (1 bit)
access : write-only
PID30 : Peripheral Clock 30 Enable
bits : 30 - 30 (1 bit)
access : write-only
PID31 : Peripheral Clock 31 Enable
bits : 31 - 31 (1 bit)
access : write-only
Peripheral Clock Enable Register 1
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PID32 : Peripheral Clock 32 Enable
bits : 0 - 0 (1 bit)
access : write-only
PID33 : Peripheral Clock 33 Enable
bits : 1 - 1 (1 bit)
access : write-only
PID34 : Peripheral Clock 34 Enable
bits : 2 - 2 (1 bit)
access : write-only
Peripheral Clock Disable Register 1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PID32 : Peripheral Clock 32 Disable
bits : 0 - 0 (1 bit)
access : write-only
PID33 : Peripheral Clock 33 Disable
bits : 1 - 1 (1 bit)
access : write-only
PID34 : Peripheral Clock 34 Disable
bits : 2 - 2 (1 bit)
access : write-only
Peripheral Clock Status Register 1
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PID32 : Peripheral Clock 32 Status
bits : 0 - 0 (1 bit)
access : read-only
PID33 : Peripheral Clock 33 Status
bits : 1 - 1 (1 bit)
access : read-only
PID34 : Peripheral Clock 34 Status
bits : 2 - 2 (1 bit)
access : read-only
Programmable Clock 0 Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSS : Master Clock Source Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : SLOW_CLK
Slow Clock is selected
0x1 : MAIN_CLK
Main Clock is selected
0x2 : PLLA_CLK
PLLA Clock is selected
0x3 : PLLB_CLK
PLLB Clock is selected
0x4 : MCK
Master Clock is selected
End of enumeration elements list.
PRES : Programmable Clock Prescaler
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : CLK_1
Selected clock
0x1 : CLK_2
Selected clock divided by 2
0x2 : CLK_4
Selected clock divided by 4
0x3 : CLK_8
Selected clock divided by 8
0x4 : CLK_16
Selected clock divided by 16
0x5 : CLK_32
Selected clock divided by 32
0x6 : CLK_64
Selected clock divided by 64
End of enumeration elements list.
Oscillator Calibration Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL4 : RC Oscillator Calibration bits for 4 MHz
bits : 0 - 6 (7 bit)
access : read-write
SEL4 : Selection of RC Oscillator Calibration bits for 4 MHz
bits : 7 - 7 (1 bit)
access : read-write
CAL8 : RC Oscillator Calibration bits for 8 MHz
bits : 8 - 14 (7 bit)
access : read-write
SEL8 : Selection of RC Oscillator Calibration bits for 8 MHz
bits : 15 - 15 (1 bit)
access : read-write
CAL12 : RC Oscillator Calibration bits for 12 MHz
bits : 16 - 22 (7 bit)
access : read-write
SEL12 : Selection of RC Oscillator Calibration bits for 12 MHz
bits : 23 - 23 (1 bit)
access : read-write
Peripheral Clock Disable Register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PID8 : Peripheral Clock 8 Disable
bits : 8 - 8 (1 bit)
access : write-only
PID9 : Peripheral Clock 9 Disable
bits : 9 - 9 (1 bit)
access : write-only
PID10 : Peripheral Clock 10 Disable
bits : 10 - 10 (1 bit)
access : write-only
PID11 : Peripheral Clock 11 Disable
bits : 11 - 11 (1 bit)
access : write-only
PID12 : Peripheral Clock 12 Disable
bits : 12 - 12 (1 bit)
access : write-only
PID13 : Peripheral Clock 13 Disable
bits : 13 - 13 (1 bit)
access : write-only
PID14 : Peripheral Clock 14 Disable
bits : 14 - 14 (1 bit)
access : write-only
PID15 : Peripheral Clock 15 Disable
bits : 15 - 15 (1 bit)
access : write-only
PID16 : Peripheral Clock 16 Disable
bits : 16 - 16 (1 bit)
access : write-only
PID17 : Peripheral Clock 17 Disable
bits : 17 - 17 (1 bit)
access : write-only
PID18 : Peripheral Clock 18 Disable
bits : 18 - 18 (1 bit)
access : write-only
PID19 : Peripheral Clock 19 Disable
bits : 19 - 19 (1 bit)
access : write-only
PID20 : Peripheral Clock 20 Disable
bits : 20 - 20 (1 bit)
access : write-only
PID21 : Peripheral Clock 21 Disable
bits : 21 - 21 (1 bit)
access : write-only
PID22 : Peripheral Clock 22 Disable
bits : 22 - 22 (1 bit)
access : write-only
PID23 : Peripheral Clock 23 Disable
bits : 23 - 23 (1 bit)
access : write-only
PID24 : Peripheral Clock 24 Disable
bits : 24 - 24 (1 bit)
access : write-only
PID25 : Peripheral Clock 25 Disable
bits : 25 - 25 (1 bit)
access : write-only
PID26 : Peripheral Clock 26 Disable
bits : 26 - 26 (1 bit)
access : write-only
PID27 : Peripheral Clock 27 Disable
bits : 27 - 27 (1 bit)
access : write-only
PID28 : Peripheral Clock 28 Disable
bits : 28 - 28 (1 bit)
access : write-only
PID29 : Peripheral Clock 29 Disable
bits : 29 - 29 (1 bit)
access : write-only
PID30 : Peripheral Clock 30 Disable
bits : 30 - 30 (1 bit)
access : write-only
PID31 : Peripheral Clock 31 Disable
bits : 31 - 31 (1 bit)
access : write-only
Peripheral Clock Status Register 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PID8 : Peripheral Clock 8 Status
bits : 8 - 8 (1 bit)
access : read-only
PID9 : Peripheral Clock 9 Status
bits : 9 - 9 (1 bit)
access : read-only
PID10 : Peripheral Clock 10 Status
bits : 10 - 10 (1 bit)
access : read-only
PID11 : Peripheral Clock 11 Status
bits : 11 - 11 (1 bit)
access : read-only
PID12 : Peripheral Clock 12 Status
bits : 12 - 12 (1 bit)
access : read-only
PID13 : Peripheral Clock 13 Status
bits : 13 - 13 (1 bit)
access : read-only
PID14 : Peripheral Clock 14 Status
bits : 14 - 14 (1 bit)
access : read-only
PID15 : Peripheral Clock 15 Status
bits : 15 - 15 (1 bit)
access : read-only
PID16 : Peripheral Clock 16 Status
bits : 16 - 16 (1 bit)
access : read-only
PID17 : Peripheral Clock 17 Status
bits : 17 - 17 (1 bit)
access : read-only
PID18 : Peripheral Clock 18 Status
bits : 18 - 18 (1 bit)
access : read-only
PID19 : Peripheral Clock 19 Status
bits : 19 - 19 (1 bit)
access : read-only
PID20 : Peripheral Clock 20 Status
bits : 20 - 20 (1 bit)
access : read-only
PID21 : Peripheral Clock 21 Status
bits : 21 - 21 (1 bit)
access : read-only
PID22 : Peripheral Clock 22 Status
bits : 22 - 22 (1 bit)
access : read-only
PID23 : Peripheral Clock 23 Status
bits : 23 - 23 (1 bit)
access : read-only
PID24 : Peripheral Clock 24 Status
bits : 24 - 24 (1 bit)
access : read-only
PID25 : Peripheral Clock 25 Status
bits : 25 - 25 (1 bit)
access : read-only
PID26 : Peripheral Clock 26 Status
bits : 26 - 26 (1 bit)
access : read-only
PID27 : Peripheral Clock 27 Status
bits : 27 - 27 (1 bit)
access : read-only
PID28 : Peripheral Clock 28 Status
bits : 28 - 28 (1 bit)
access : read-only
PID29 : Peripheral Clock 29 Status
bits : 29 - 29 (1 bit)
access : read-only
PID30 : Peripheral Clock 30 Status
bits : 30 - 30 (1 bit)
access : read-only
PID31 : Peripheral Clock 31 Status
bits : 31 - 31 (1 bit)
access : read-only
Main Oscillator Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOSCXTEN : Main Crystal Oscillator Enable
bits : 0 - 0 (1 bit)
access : read-write
MOSCXTBY : Main Crystal Oscillator Bypass
bits : 1 - 1 (1 bit)
access : read-write
WAITMODE : Wait Mode Command
bits : 2 - 2 (1 bit)
access : read-write
MOSCRCEN : Main On-Chip RC Oscillator Enable
bits : 3 - 3 (1 bit)
access : read-write
MOSCRCF : Main On-Chip RC Oscillator Frequency Selection
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 4_MHz
The Fast RC Oscillator Frequency is at 4 MHz (default)
0x1 : 8_MHz
The Fast RC Oscillator Frequency is at 8 MHz
0x2 : 12_MHz
The Fast RC Oscillator Frequency is at 12 MHz
End of enumeration elements list.
MOSCXTST : Main Crystal Oscillator Start-up Time
bits : 8 - 15 (8 bit)
access : read-write
KEY : Write Access Password
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0x37 : PASSWD
Writing any other value in this field aborts the write operation.Always reads as 0.
End of enumeration elements list.
MOSCSEL : Main Oscillator Selection
bits : 24 - 24 (1 bit)
access : read-write
CFDEN : Clock Failure Detector Enable
bits : 25 - 25 (1 bit)
access : read-write
Main Clock Frequency Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAINF : Main Clock Frequency
bits : 0 - 15 (16 bit)
access : read-write
MAINFRDY : Main Clock Ready
bits : 16 - 16 (1 bit)
access : read-write
RCMEAS : RC Oscillator Frequency Measure (write-only)
bits : 20 - 20 (1 bit)
access : read-write
PLLA Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVA : PLLA Front_End Divider
bits : 0 - 7 (8 bit)
access : read-write
PLLACOUNT : PLLA Counter
bits : 8 - 13 (6 bit)
access : read-write
MULA : PLLA Multiplier
bits : 16 - 26 (11 bit)
access : read-write
ONE : Must Be Set to 1
bits : 29 - 29 (1 bit)
access : read-write
PLLB Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVB : PLLB Front-End Divider
bits : 0 - 7 (8 bit)
access : read-write
PLLBCOUNT : PLLB Counter
bits : 8 - 13 (6 bit)
access : read-write
MULB : PLLB Multiplier
bits : 16 - 26 (11 bit)
access : read-write
Master Clock Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSS : Master Clock Source Selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : SLOW_CLK
Slow Clock is selected
0x1 : MAIN_CLK
Main Clock is selected
0x2 : PLLA_CLK
PLLA Clock is selected
0x3 : PLLB_CLK
PLLBClock is selected
End of enumeration elements list.
PRES : Processor Clock Prescaler
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : CLK_1
Selected clock
0x1 : CLK_2
Selected clock divided by 2
0x2 : CLK_4
Selected clock divided by 4
0x3 : CLK_8
Selected clock divided by 8
0x4 : CLK_16
Selected clock divided by 16
0x5 : CLK_32
Selected clock divided by 32
0x6 : CLK_64
Selected clock divided by 64
0x7 : CLK_3
Selected clock divided by 3
End of enumeration elements list.
PLLADIV2 : PLLA Divisor by 2
bits : 12 - 12 (1 bit)
access : read-write
PLLBDIV2 : PLLB Divisor by 2
bits : 13 - 13 (1 bit)
access : read-write
USB Clock Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBS : USB Input Clock Selection
bits : 0 - 0 (1 bit)
access : read-write
USBDIV : Divider for USB Clock
bits : 8 - 11 (4 bit)
access : read-write
System Clock Disable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDP : USB Device Port Clock Disable
bits : 7 - 7 (1 bit)
access : write-only
PCK0 : Programmable Clock 0 Output Disable
bits : 8 - 8 (1 bit)
access : write-only
PCK1 : Programmable Clock 1 Output Disable
bits : 9 - 9 (1 bit)
access : write-only
PCK2 : Programmable Clock 2 Output Disable
bits : 10 - 10 (1 bit)
access : write-only
Programmable Clock 0 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CSS : Master Clock Source Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : SLOW_CLK
Slow Clock is selected
0x1 : MAIN_CLK
Main Clock is selected
0x2 : PLLA_CLK
PLLA Clock is selected
0x3 : PLLB_CLK
PLLB Clock is selected
0x4 : MCK
Master Clock is selected
End of enumeration elements list.
PRES : Programmable Clock Prescaler
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : CLK_1
Selected clock
0x1 : CLK_2
Selected clock divided by 2
0x2 : CLK_4
Selected clock divided by 4
0x3 : CLK_8
Selected clock divided by 8
0x4 : CLK_16
Selected clock divided by 16
0x5 : CLK_32
Selected clock divided by 32
0x6 : CLK_64
Selected clock divided by 64
End of enumeration elements list.
Programmable Clock 0 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CSS : Master Clock Source Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : SLOW_CLK
Slow Clock is selected
0x1 : MAIN_CLK
Main Clock is selected
0x2 : PLLA_CLK
PLLA Clock is selected
0x3 : PLLB_CLK
PLLB Clock is selected
0x4 : MCK
Master Clock is selected
End of enumeration elements list.
PRES : Programmable Clock Prescaler
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : CLK_1
Selected clock
0x1 : CLK_2
Selected clock divided by 2
0x2 : CLK_4
Selected clock divided by 4
0x3 : CLK_8
Selected clock divided by 8
0x4 : CLK_16
Selected clock divided by 16
0x5 : CLK_32
Selected clock divided by 32
0x6 : CLK_64
Selected clock divided by 64
End of enumeration elements list.
Programmable Clock 0 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CSS : Master Clock Source Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : SLOW_CLK
Slow Clock is selected
0x1 : MAIN_CLK
Main Clock is selected
0x2 : PLLA_CLK
PLLA Clock is selected
0x3 : PLLB_CLK
PLLB Clock is selected
0x4 : MCK
Master Clock is selected
End of enumeration elements list.
PRES : Programmable Clock Prescaler
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : CLK_1
Selected clock
0x1 : CLK_2
Selected clock divided by 2
0x2 : CLK_4
Selected clock divided by 4
0x3 : CLK_8
Selected clock divided by 8
0x4 : CLK_16
Selected clock divided by 16
0x5 : CLK_32
Selected clock divided by 32
0x6 : CLK_64
Selected clock divided by 64
End of enumeration elements list.
Interrupt Enable Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MOSCXTS : Main Crystal Oscillator Status Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
LOCKA : PLLA Lock Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
LOCKB : PLLB Lock Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
MCKRDY : Master Clock Ready Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
PCKRDY0 : Programmable Clock Ready 0 Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
PCKRDY1 : Programmable Clock Ready 1 Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
PCKRDY2 : Programmable Clock Ready 2 Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
MOSCSELS : Main Oscillator Selection Status Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
MOSCRCS : Main On-Chip RC Status Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only
CFDEV : Clock Failure Detector Event Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
Interrupt Disable Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MOSCXTS : Main Crystal Oscillator Status Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
LOCKA : PLLA Lock Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
LOCKB : PLLB Lock Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
MCKRDY : Master Clock Ready Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
PCKRDY0 : Programmable Clock Ready 0 Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
PCKRDY1 : Programmable Clock Ready 1 Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
PCKRDY2 : Programmable Clock Ready 2 Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
MOSCSELS : Main Oscillator Selection Status Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
MOSCRCS : Main On-Chip RC Status Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only
CFDEV : Clock Failure Detector Event Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
Status Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MOSCXTS : Main XTAL Oscillator Status
bits : 0 - 0 (1 bit)
access : read-only
LOCKA : PLLA Lock Status
bits : 1 - 1 (1 bit)
access : read-only
LOCKB : PLLB Lock Status
bits : 2 - 2 (1 bit)
access : read-only
MCKRDY : Master Clock Status
bits : 3 - 3 (1 bit)
access : read-only
OSCSELS : Slow Clock Oscillator Selection
bits : 7 - 7 (1 bit)
access : read-only
PCKRDY0 : Programmable Clock Ready Status
bits : 8 - 8 (1 bit)
access : read-only
PCKRDY1 : Programmable Clock Ready Status
bits : 9 - 9 (1 bit)
access : read-only
PCKRDY2 : Programmable Clock Ready Status
bits : 10 - 10 (1 bit)
access : read-only
MOSCSELS : Main Oscillator Selection Status
bits : 16 - 16 (1 bit)
access : read-only
MOSCRCS : Main On-Chip RC Oscillator Status
bits : 17 - 17 (1 bit)
access : read-only
CFDEV : Clock Failure Detector Event
bits : 18 - 18 (1 bit)
access : read-only
CFDS : Clock Failure Detector Status
bits : 19 - 19 (1 bit)
access : read-only
FOS : Clock Failure Detector Fault Output Status
bits : 20 - 20 (1 bit)
access : read-only
Interrupt Mask Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MOSCXTS : Main Crystal Oscillator Status Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
LOCKA : PLLA Lock Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
LOCKB : PLLB Lock Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
MCKRDY : Master Clock Ready Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
PCKRDY0 : Programmable Clock Ready 0 Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
PCKRDY1 : Programmable Clock Ready 1 Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
PCKRDY2 : Programmable Clock Ready 2 Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
MOSCSELS : Main Oscillator Selection Status Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
MOSCRCS : Main On-Chip RC Status Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only
CFDEV : Clock Failure Detector Event Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only
Fast Start-up Mode Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSTT0 : Fast Start-up Input Enable 0
bits : 0 - 0 (1 bit)
access : read-write
FSTT1 : Fast Start-up Input Enable 1
bits : 1 - 1 (1 bit)
access : read-write
FSTT2 : Fast Start-up Input Enable 2
bits : 2 - 2 (1 bit)
access : read-write
FSTT3 : Fast Start-up Input Enable 3
bits : 3 - 3 (1 bit)
access : read-write
FSTT4 : Fast Start-up Input Enable 4
bits : 4 - 4 (1 bit)
access : read-write
FSTT5 : Fast Start-up Input Enable 5
bits : 5 - 5 (1 bit)
access : read-write
FSTT6 : Fast Start-up Input Enable 6
bits : 6 - 6 (1 bit)
access : read-write
FSTT7 : Fast Start-up Input Enable 7
bits : 7 - 7 (1 bit)
access : read-write
FSTT8 : Fast Start-up Input Enable 8
bits : 8 - 8 (1 bit)
access : read-write
FSTT9 : Fast Start-up Input Enable 9
bits : 9 - 9 (1 bit)
access : read-write
FSTT10 : Fast Start-up Input Enable 10
bits : 10 - 10 (1 bit)
access : read-write
FSTT11 : Fast Start-up Input Enable 11
bits : 11 - 11 (1 bit)
access : read-write
FSTT12 : Fast Start-up Input Enable 12
bits : 12 - 12 (1 bit)
access : read-write
FSTT13 : Fast Start-up Input Enable 13
bits : 13 - 13 (1 bit)
access : read-write
FSTT14 : Fast Start-up Input Enable 14
bits : 14 - 14 (1 bit)
access : read-write
FSTT15 : Fast Start-up Input Enable 15
bits : 15 - 15 (1 bit)
access : read-write
RTTAL : RTT Alarm Enable
bits : 16 - 16 (1 bit)
access : read-write
RTCAL : RTC Alarm Enable
bits : 17 - 17 (1 bit)
access : read-write
USBAL : USB Alarm Enable
bits : 18 - 18 (1 bit)
access : read-write
LPM : Low-power Mode
bits : 20 - 20 (1 bit)
access : read-write
FLPM : Flash Low-power Mode
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0x0 : FLASH_STANDBY
Flash is in Standby Mode when system enters Wait Mode
0x1 : FLASH_DEEP_POWERDOWN
Flash is in deep-power-down mode when system enters Wait Mode
0x2 : FLASH_IDLE
idle mode
End of enumeration elements list.
Fast Start-up Polarity Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSTP0 : Fast Start-up Input Polarityx
bits : 0 - 0 (1 bit)
access : read-write
FSTP1 : Fast Start-up Input Polarityx
bits : 1 - 1 (1 bit)
access : read-write
FSTP2 : Fast Start-up Input Polarityx
bits : 2 - 2 (1 bit)
access : read-write
FSTP3 : Fast Start-up Input Polarityx
bits : 3 - 3 (1 bit)
access : read-write
FSTP4 : Fast Start-up Input Polarityx
bits : 4 - 4 (1 bit)
access : read-write
FSTP5 : Fast Start-up Input Polarityx
bits : 5 - 5 (1 bit)
access : read-write
FSTP6 : Fast Start-up Input Polarityx
bits : 6 - 6 (1 bit)
access : read-write
FSTP7 : Fast Start-up Input Polarityx
bits : 7 - 7 (1 bit)
access : read-write
FSTP8 : Fast Start-up Input Polarityx
bits : 8 - 8 (1 bit)
access : read-write
FSTP9 : Fast Start-up Input Polarityx
bits : 9 - 9 (1 bit)
access : read-write
FSTP10 : Fast Start-up Input Polarityx
bits : 10 - 10 (1 bit)
access : read-write
FSTP11 : Fast Start-up Input Polarityx
bits : 11 - 11 (1 bit)
access : read-write
FSTP12 : Fast Start-up Input Polarityx
bits : 12 - 12 (1 bit)
access : read-write
FSTP13 : Fast Start-up Input Polarityx
bits : 13 - 13 (1 bit)
access : read-write
FSTP14 : Fast Start-up Input Polarityx
bits : 14 - 14 (1 bit)
access : read-write
FSTP15 : Fast Start-up Input Polarityx
bits : 15 - 15 (1 bit)
access : read-write
Fault Output Clear Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FOCLR : Fault Output Clear
bits : 0 - 0 (1 bit)
access : write-only
System Clock Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UDP : USB Device Port Clock Status
bits : 7 - 7 (1 bit)
access : read-only
PCK0 : Programmable Clock 0 Output Status
bits : 8 - 8 (1 bit)
access : read-only
PCK1 : Programmable Clock 1 Output Status
bits : 9 - 9 (1 bit)
access : read-only
PCK2 : Programmable Clock 2 Output Status
bits : 10 - 10 (1 bit)
access : read-only
Programmable Clock 0 Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSS : Master Clock Source Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : SLOW_CLK
Slow Clock is selected
0x1 : MAIN_CLK
Main Clock is selected
0x2 : PLLA_CLK
PLLA Clock is selected
0x3 : PLLB_CLK
PLLB Clock is selected
0x4 : MCK
Master Clock is selected
End of enumeration elements list.
PRES : Programmable Clock Prescaler
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : CLK_1
Selected clock
0x1 : CLK_2
Selected clock divided by 2
0x2 : CLK_4
Selected clock divided by 4
0x3 : CLK_8
Selected clock divided by 8
0x4 : CLK_16
Selected clock divided by 16
0x5 : CLK_32
Selected clock divided by 32
0x6 : CLK_64
Selected clock divided by 64
End of enumeration elements list.
Programmable Clock 0 Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSS : Master Clock Source Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : SLOW_CLK
Slow Clock is selected
0x1 : MAIN_CLK
Main Clock is selected
0x2 : PLLA_CLK
PLLA Clock is selected
0x3 : PLLB_CLK
PLLB Clock is selected
0x4 : MCK
Master Clock is selected
End of enumeration elements list.
PRES : Programmable Clock Prescaler
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : CLK_1
Selected clock
0x1 : CLK_2
Selected clock divided by 2
0x2 : CLK_4
Selected clock divided by 4
0x3 : CLK_8
Selected clock divided by 8
0x4 : CLK_16
Selected clock divided by 16
0x5 : CLK_32
Selected clock divided by 32
0x6 : CLK_64
Selected clock divided by 64
End of enumeration elements list.
Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x504D43 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
End of enumeration elements list.
Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.