\n
address_offset : 0x0 Bytes (0x0)
size : 0x40000 byte (0x0)
mem_usage : registers
protection : not protected
Main Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POWERDWN : ETM Control in low power mode
bits : 0 - 0 (1 bit)
access : read-write
PORTSIZE : ETM Port Size
bits : 4 - 6 (3 bit)
access : read-write
STALL : Stall Processor
bits : 7 - 7 (1 bit)
access : read-write
BRANCHOUTPUT : Branch Output
bits : 8 - 8 (1 bit)
access : read-write
DBGREQCTRL : Debug Request Control
bits : 9 - 9 (1 bit)
access : read-write
ETMPROG : ETM Programming
bits : 10 - 10 (1 bit)
access : read-write
ETMPORTSEL : ETM Port Selection
bits : 11 - 11 (1 bit)
access : read-write
PORTMODE2 : Port Mode[2]
bits : 13 - 13 (1 bit)
access : read-write
PORTMODE : Port Mode Control
bits : 16 - 17 (2 bit)
access : read-write
EPORTSIZE : Port Size[3]
bits : 21 - 22 (2 bit)
access : read-write
TSTAMPEN : Time Stamp Enable
bits : 28 - 28 (1 bit)
access : read-write
ETM Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETHOF : ETM Overflow
bits : 0 - 0 (1 bit)
access : read-only
ETMPROGBIT : ETM Programming Bit Status
bits : 1 - 1 (1 bit)
access : read-only
TRACESTAT : Trace Start/Stop Status
bits : 2 - 2 (1 bit)
access : read-write
TRIGBIT : Trigger Bit
bits : 3 - 3 (1 bit)
access : read-write
ETM System Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MAXPORTSIZE : Maximum Port Size
bits : 0 - 2 (3 bit)
access : read-only
FIFOFULL : FIFO FULL Supported
bits : 8 - 8 (1 bit)
access : read-only
MAXPORTSIZE3 : Max Port Size[3]
bits : 9 - 9 (1 bit)
access : read-only
PORTSIZE : Port Size Supported
bits : 10 - 10 (1 bit)
access : read-only
PORTMODE : Port Mode Supported
bits : 11 - 11 (1 bit)
access : read-only
PROCNUM : Number of Supported Processros
bits : 12 - 14 (3 bit)
access : read-only
NOFETCHCOMP : No Fetch Comparison
bits : 17 - 17 (1 bit)
access : read-only
Counter Reload Value
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Free running counter reload value
bits : 0 - 15 (16 bit)
access : read-write
Synchronisation Frequency Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQ : Synchronisation Frequency Value
bits : 0 - 11 (12 bit)
access : read-write
ID Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMPVER : Implementation Revision
bits : 0 - 3 (4 bit)
access : read-only
ETMMINVER : Minor ETM Architecture Version
bits : 4 - 7 (4 bit)
access : read-only
ETMMAJVER : Major ETM Architecture Version
bits : 8 - 11 (4 bit)
access : read-only
PROCFAM : Implementer Code
bits : 12 - 15 (4 bit)
access : read-only
LPCF : Load PC First
bits : 16 - 16 (1 bit)
access : read-only
THUMBT : 32-bit Thumb Instruction Tracing
bits : 18 - 18 (1 bit)
access : read-only
SECEXT : Security Extension Support
bits : 19 - 19 (1 bit)
access : read-only
BPE : Branch Packet Encoding
bits : 20 - 20 (1 bit)
access : read-only
IMPCODE : Implementer Code
bits : 24 - 31 (8 bit)
access : read-only
Configuration Code Extension Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXTINPSEL : Extended External Input Selectors
bits : 0 - 1 (2 bit)
access : read-only
EXTINPBUS : Extended External Input Bus
bits : 3 - 10 (8 bit)
access : read-only
READREGS : Readable Registers
bits : 11 - 11 (1 bit)
access : read-only
DADDRCMP : Data Address comparisons
bits : 12 - 12 (1 bit)
access : read-only
INSTRES : Instrumentation Resources
bits : 13 - 15 (3 bit)
access : read-only
EICEWPNT : EmbeddedICE watchpoint inputs
bits : 16 - 19 (4 bit)
access : read-only
TEICEWPNT : Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs
bits : 20 - 20 (1 bit)
access : read-only
EICEIMP : EmbeddedICE Behavior control Implemented
bits : 21 - 21 (1 bit)
access : read-only
TIMP : Timestamping Implemented
bits : 22 - 22 (1 bit)
access : read-only
RFCNT : Reduced Function Counter
bits : 27 - 27 (1 bit)
access : read-only
TENC : Timestamp Encoding
bits : 28 - 28 (1 bit)
access : read-only
TSIZE : Timestamp Size
bits : 29 - 29 (1 bit)
access : read-only
TraceEnable Start/Stop EmbeddedICE Control Register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTRSEL : Stop Resource Selection
bits : 0 - 3 (4 bit)
access : read-write
STOPRSEL : Stop Resource Selection
bits : 16 - 19 (4 bit)
access : read-write
Timestamp Event Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESAEVT : ETM Resource A Event
bits : 0 - 6 (7 bit)
access : read-write
RESBEVT : ETM Resource B Event
bits : 7 - 13 (7 bit)
access : read-write
ETMFCNEVT : ETM Function Event
bits : 14 - 16 (3 bit)
access : read-write
ETM TraceEnable Event Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESA : ETM Resource A Trace Enable
bits : 0 - 6 (7 bit)
access : read-write
RESB : ETM Resource B Trace Enable
bits : 7 - 13 (7 bit)
access : read-write
ETMFCNEN : ETM Function Trace Enable
bits : 14 - 16 (3 bit)
access : read-write
CoreSight Trace ID Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRACEID : Trace ID
bits : 0 - 6 (7 bit)
access : read-write
ETM ID Register 2
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFE : RFE Transfer Order
bits : 0 - 0 (1 bit)
access : read-only
SWP : SWP Transfer Order
bits : 1 - 1 (1 bit)
access : read-only
ETM Trace control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADRCMP : Address Comparator
bits : 0 - 7 (8 bit)
access : read-write
MEMMAP : Memmap
bits : 8 - 23 (16 bit)
access : read-write
INCEXCTL : Trace Include/Exclude Flag
bits : 24 - 24 (1 bit)
access : read-write
TCE : Trace Control Enable
bits : 25 - 25 (1 bit)
access : read-write
ETM Fifo Full Level Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYTENUM : Bytes left in FIFO
bits : 0 - 7 (8 bit)
access : read-write
Device Power-down Status Register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ETMUP : ETM Powered Up
bits : 0 - 0 (1 bit)
access : read-only
Configuration Code Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADRCMPPAIR : Number of Address Comparator Pairs
bits : 0 - 3 (4 bit)
access : read-only
DATACMPNUM : Number of Data Value Comparators
bits : 4 - 7 (4 bit)
access : read-only
MMDECCNT : Number of Memeory Map Decoders
bits : 8 - 12 (5 bit)
access : read-only
COUNTNUM : Number of Counters
bits : 13 - 15 (3 bit)
access : read-only
SEQPRES : Sequencer Present
bits : 16 - 16 (1 bit)
access : read-only
EXTINPNUM : Number of External Inputs
bits : 17 - 19 (3 bit)
access : read-only
Enumeration:
0x00000000 : ZERO
Zero inputs presents
0x00000001 : ONE
One inputs presents
0x00000002 : TWO
Two inputs presents
End of enumeration elements list.
EXTOUTNUM : Number of External Output
bits : 20 - 22 (3 bit)
access : read-only
FIFOFULLPRES : FIFIO FULL present
bits : 23 - 23 (1 bit)
access : read-only
IDCOMPNUM : Number of context ID Comparators
bits : 24 - 25 (2 bit)
access : read-only
TRACESS : Trace Start/Stop Block Present
bits : 26 - 26 (1 bit)
access : read-only
MMACCESS : Coprocessor and Memeory Access
bits : 27 - 27 (1 bit)
access : read-only
ETMID : ETM ID Register Present
bits : 31 - 31 (1 bit)
access : read-only
ETM Trigger Event Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESA : ETM Resource A
bits : 0 - 6 (7 bit)
access : read-write
RESB : ETM Resource B
bits : 7 - 13 (7 bit)
access : read-write
ETMFCN : ETM Function
bits : 14 - 16 (3 bit)
access : read-write
Integration Test Miscellaneous Inputs Register
address_offset : 0xEE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTIN : EXTIN Value
bits : 0 - 1 (2 bit)
access : read-write
COREHALT : Core Halt
bits : 4 - 4 (1 bit)
access : read-write
Integration Test Trigger Out Register
address_offset : 0xEE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGGEROUT : Trigger output value
bits : 0 - 0 (1 bit)
access : read-write
ETM Integration Test ATB Control 2 Register
address_offset : 0xEF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ATREADY : ATREADY Input Value
bits : 0 - 0 (1 bit)
access : read-only
ETM Integration Test ATB Control 0 Register
address_offset : 0xEF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATVALID : ATVALID Output Value
bits : 0 - 0 (1 bit)
access : read-write
ETM Integration Control Register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITEN : Integration Mode Enable
bits : 0 - 0 (1 bit)
access : read-write
ETM Claim Tag Set Register
address_offset : 0xFA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETTAG : Tag Bits
bits : 0 - 7 (8 bit)
access : read-write
ETM Claim Tag Clear Register
address_offset : 0xFA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRTAG : Tag Bits
bits : 0 - 0 (1 bit)
access : read-write
ETM Lock Access Register
address_offset : 0xFB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : Key Value
bits : 0 - 0 (1 bit)
access : read-write
Lock Status Register
address_offset : 0xFB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LOCKIMP : ETM Locking Implemented
bits : 0 - 0 (1 bit)
access : read-only
LOCKED : ETM locked
bits : 1 - 1 (1 bit)
access : read-only
ETM Authentication Status Register
address_offset : 0xFB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NONSECINVDBG : Non-secure invasive Debug Status
bits : 0 - 1 (2 bit)
access : read-only
NONSECNONINVDBG : Non-secure non-invasive Debug Status
bits : 2 - 3 (2 bit)
access : read-only
Enumeration:
0x00000002 : DISABLE
Non-secure non-invasive debug disable
0x00000003 : ENABLE
Non-secure non-invasive debug enable
End of enumeration elements list.
SECINVDBG : Secure invasive Debug Status
bits : 4 - 5 (2 bit)
access : read-only
SECNONINVDBG : Secure non-invasive Debug Status
bits : 6 - 7 (2 bit)
access : read-only
CoreSight Device Type Register
address_offset : 0xFCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TRACESRC : Trace Source
bits : 0 - 3 (4 bit)
access : read-only
PROCTRACE : Processor Trace
bits : 4 - 7 (4 bit)
access : read-only
Peripheral ID4 Register
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CONTCODE : JEP106 Continuation Code
bits : 0 - 3 (4 bit)
access : read-only
COUNT : 4KB Count
bits : 4 - 7 (4 bit)
access : read-only
Peripheral ID5 Register
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral ID6 Register
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral ID7 Register
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral ID0 Register
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PARTNUM : Part Number
bits : 0 - 7 (8 bit)
access : read-only
Peripheral ID1 Register
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PARTNUM : Part Number
bits : 0 - 3 (4 bit)
access : read-only
IDCODE : JEP106 Identity Code
bits : 4 - 7 (4 bit)
access : read-only
Peripheral ID2 Register
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IDCODE : JEP106 Identity Code
bits : 0 - 2 (3 bit)
access : read-only
ALWAYS1 : Always 1
bits : 3 - 3 (1 bit)
access : read-only
REV : Revision
bits : 4 - 7 (4 bit)
access : read-only
Peripheral ID3 Register
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CUSTMOD : Customer Modified
bits : 0 - 3 (4 bit)
access : read-only
REVAND : RevAnd
bits : 4 - 7 (4 bit)
access : read-only
Component ID0 Register
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMB : CoreSight Preamble
bits : 0 - 7 (8 bit)
access : read-only
Component ID1 Register
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMB : CoreSight Preamble
bits : 0 - 7 (8 bit)
access : read-only
Component ID2 Register
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMB : CoreSight Preamble
bits : 0 - 7 (8 bit)
access : read-only
Component ID3 Register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMB : CoreSight Preamble
bits : 0 - 7 (8 bit)
access : read-only
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