\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
CRCCU Descriptor Base Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSCR : Descriptor Base Address
bits : 9 - 31 (23 bit)
access : read-write
CRCCU DMA Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMASR : DMA Status Register
bits : 0 - 0 (1 bit)
access : read-only
CRCCU DMA Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DMAIER : Interrupt Enable register
bits : 0 - 0 (1 bit)
access : write-only
CRCCU DMA Interrupt Disable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DMAIDR : Interrupt Disable register
bits : 0 - 0 (1 bit)
access : write-only
CRCCU DMA Interrupt Mask Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMAIMR : Interrupt Mask Register
bits : 0 - 0 (1 bit)
access : read-only
CRCCU DMA Interrupt Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMAISR : Interrupt Status register
bits : 0 - 0 (1 bit)
access : read-only
CRCCU Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RESET : CRC Computation Reset
bits : 0 - 0 (1 bit)
access : write-only
CRCCU Mode Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : CRC Enable
bits : 0 - 0 (1 bit)
access : read-write
COMPARE : CRC Compare
bits : 1 - 1 (1 bit)
access : read-write
PTYPE : Primitive Polynomial
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : CCITT8023
Polynom 0x04C11DB7
0x1 : CASTAGNOLI
Polynom 0x1EDC6F41
0x2 : CCITT16
Polynom 0x1021
End of enumeration elements list.
DIVIDER : Request Divider
bits : 4 - 7 (4 bit)
access : read-write
CRCCU Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRC : Cyclic Redundancy Check Value
bits : 0 - 31 (32 bit)
access : read-only
CRCCU Interrupt Enable Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ERRIER : CRC Error Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
CRCCU Interrupt Disable Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ERRIDR : CRC Error Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
CRCCU Interrupt Mask Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRIMR : CRC Error Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
CRCCU Interrupt Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRISR : CRC Error Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only
CRCCU DMA Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DMAEN : DMA Enable Register
bits : 0 - 0 (1 bit)
access : write-only
CRCCU DMA Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DMADIS : DMA Disable Register
bits : 0 - 0 (1 bit)
access : write-only
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