\n
address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
Master Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : INFINITE
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
0x1 : SINGLE
The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst.
0x2 : FOUR_BEAT
The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end.
0x3 : EIGHT_BEAT
The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end.
0x4 : SIXTEEN_BEAT
The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end.
End of enumeration elements list.
Master Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : INFINITE
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
0x1 : SINGLE
The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst.
0x2 : FOUR_BEAT
The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end.
0x3 : EIGHT_BEAT
The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end.
0x4 : SIXTEEN_BEAT
The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end.
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NO_DEFAULT
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again.
0x2 : FIXED
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ROUND_ROBIN
Round-robin arbitration
1 : FIXED_PRIORITY
Fixed priority arbitration
End of enumeration elements list.
System I/O Configuration register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSIO4 : PB4 or TDI Assignment
bits : 4 - 4 (1 bit)
access : read-write
SYSIO5 : PB5 or TDO/TRACESWO Assignment
bits : 5 - 5 (1 bit)
access : read-write
SYSIO6 : PB6 or TMS/SWDIO Assignment
bits : 6 - 6 (1 bit)
access : read-write
SYSIO7 : PB7 or TCK/SWCLK Assignment
bits : 7 - 7 (1 bit)
access : read-write
SYSIO10 : PB10 or DDM Assignment
bits : 10 - 10 (1 bit)
access : read-write
SYSIO11 : PB11 or DDP Assignment
bits : 11 - 11 (1 bit)
access : read-write
SYSIO12 : PB12 or ERASE Assignment
bits : 12 - 12 (1 bit)
access : read-write
SMC Chip Select NAND Flash Assignment Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMC_NFCS0 : SMC NAND Flash Chip Select 0 Assignment
bits : 0 - 0 (1 bit)
access : read-write
SMC_NFCS1 : SMC NAND Flash Chip Select 1 Assignment
bits : 1 - 1 (1 bit)
access : read-write
SMC_NFCS2 : SMC NAND Flash Chip Select 2 Assignment
bits : 2 - 2 (1 bit)
access : read-write
SMC_NFCS3 : SMC NAND Flash Chip Select 3 Assignment
bits : 3 - 3 (1 bit)
access : read-write
Slave Configuration Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NO_DEFAULT
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again.
0x2 : FIXED
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ROUND_ROBIN
Round-robin arbitration
1 : FIXED_PRIORITY
Fixed priority arbitration
End of enumeration elements list.
Master Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : INFINITE
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
0x1 : SINGLE
The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst.
0x2 : FOUR_BEAT
The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end.
0x3 : EIGHT_BEAT
The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end.
0x4 : SIXTEEN_BEAT
The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end.
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NO_DEFAULT
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again.
0x2 : FIXED
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ROUND_ROBIN
Round-robin arbitration
1 : FIXED_PRIORITY
Fixed priority arbitration
End of enumeration elements list.
Write Protection Mode Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protect Key
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x4D4154 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
End of enumeration elements list.
Write Protection Status Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only
Master Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : INFINITE
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
0x1 : SINGLE
The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst.
0x2 : FOUR_BEAT
The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end.
0x3 : EIGHT_BEAT
The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end.
0x4 : SIXTEEN_BEAT
The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end.
End of enumeration elements list.
Master Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : INFINITE
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
0x1 : SINGLE
The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst.
0x2 : FOUR_BEAT
The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end.
0x3 : EIGHT_BEAT
The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end.
0x4 : SIXTEEN_BEAT
The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end.
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NO_DEFAULT
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again.
0x2 : FIXED
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ROUND_ROBIN
Round-robin arbitration
1 : FIXED_PRIORITY
Fixed priority arbitration
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NO_DEFAULT
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again.
0x2 : FIXED
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ROUND_ROBIN
Round-robin arbitration
1 : FIXED_PRIORITY
Fixed priority arbitration
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NO_DEFAULT
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again.
0x2 : FIXED
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ROUND_ROBIN
Round-robin arbitration
1 : FIXED_PRIORITY
Fixed priority arbitration
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NO_DEFAULT
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again.
0x2 : FIXED
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ROUND_ROBIN
Round-robin arbitration
1 : FIXED_PRIORITY
Fixed priority arbitration
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NO_DEFAULT
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again.
0x2 : FIXED
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ROUND_ROBIN
Round-robin arbitration
1 : FIXED_PRIORITY
Fixed priority arbitration
End of enumeration elements list.
Master Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : INFINITE
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
0x1 : SINGLE
The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst.
0x2 : FOUR_BEAT
The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end.
0x3 : EIGHT_BEAT
The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end.
0x4 : SIXTEEN_BEAT
The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end.
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NO_DEFAULT
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again.
0x2 : FIXED
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ROUND_ROBIN
Round-robin arbitration
1 : FIXED_PRIORITY
Fixed priority arbitration
End of enumeration elements list.
Priority Register A for Slave 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
Priority Register A for Slave 1
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
Priority Register A for Slave 2
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
Priority Register A for Slave 3
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
Priority Register A for Slave 4
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
Master Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : INFINITE
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
0x1 : SINGLE
The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst.
0x2 : FOUR_BEAT
The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end.
0x3 : EIGHT_BEAT
The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end.
0x4 : SIXTEEN_BEAT
The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end.
End of enumeration elements list.
Master Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : INFINITE
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
0x1 : SINGLE
The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst.
0x2 : FOUR_BEAT
The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end.
0x3 : EIGHT_BEAT
The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end.
0x4 : SIXTEEN_BEAT
The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end.
End of enumeration elements list.
Slave Configuration Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NO_DEFAULT
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again.
0x2 : FIXED
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 20 (3 bit)
access : read-write
ARBT : Arbitration Type
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ROUND_ROBIN
Round-robin arbitration
1 : FIXED_PRIORITY
Fixed priority arbitration
End of enumeration elements list.
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