\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only
Channel Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Enable
bits : 0 - 0 (1 bit)
access : write-only
CH1 : Channel 1 Enable
bits : 1 - 1 (1 bit)
access : write-only
Transmit Pointer Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPTR : Transmit Counter Register
bits : 0 - 31 (32 bit)
access : read-write
Transmit Counter Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCTR : Transmit Counter Register
bits : 0 - 15 (16 bit)
access : read-write
Transmit Next Pointer Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNPTR : Transmit Next Pointer
bits : 0 - 31 (32 bit)
access : read-write
Transmit Next Counter Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNCTR : Transmit Counter Next
bits : 0 - 15 (16 bit)
access : read-write
Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only
RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only
TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only
Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only
Channel Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Disable
bits : 0 - 0 (1 bit)
access : write-only
CH1 : Channel 1 Disable
bits : 1 - 1 (1 bit)
access : write-only
Channel Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Status
bits : 0 - 0 (1 bit)
access : read-only
CH1 : Channel 1 Status
bits : 1 - 1 (1 bit)
access : read-only
Conversion Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to Convert
bits : 0 - 31 (32 bit)
access : write-only
Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY : Transmit Ready Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
EOC : End of Conversion Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
ENDTX : End of Transmit Buffer Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
TXBUFE : Transmit Buffer Empty Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
Interrupt Disable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY : Transmit Ready Interrupt Disable.
bits : 0 - 0 (1 bit)
access : write-only
EOC : End of Conversion Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
ENDTX : End of Transmit Buffer Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
TXBUFE : Transmit Buffer Empty Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
Interrupt Mask Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY : Transmit Ready Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
EOC : End of Conversion Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
ENDTX : End of Transmit Buffer Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
TXBUFE : Transmit Buffer Empty Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY : Transmit Ready Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only
EOC : End of Conversion Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only
ENDTX : End of DMA Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only
TXBUFE : Transmit Buffer Empty
bits : 3 - 3 (1 bit)
access : read-only
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGEN : Trigger Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
External trigger mode disabled. DACC in free-running mode.
1 : EN
External trigger mode enabled.
End of enumeration elements list.
TRGSEL : Trigger Selection
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
0x0 : TRGSEL0
External trigger
0x1 : TRGSEL1
TIO Output of the Timer Counter Channel 0
0x2 : TRGSEL2
TIO Output of the Timer Counter Channel 1
0x3 : TRGSEL3
TIO Output of the Timer Counter Channel 2
0x4 : TRGSEL4
PWM Event Line 0
0x5 : TRGSEL5
PWM Event Line 1
End of enumeration elements list.
WORD : Word Transfer
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : HALF
Half-word transfer
1 : WORD
Word transfer
End of enumeration elements list.
SLEEP : Sleep Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Normal mode: the DAC core and reference voltage circuitry are kept ON between conversions.
1 : ENABLED
Sleep mode: the DAC core and/or reference voltage circuitry are OFF between conversions.
End of enumeration elements list.
FASTWKUP : Fast Wake-up Mode
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : STAMODE
Normal sleep mode: the sleep mode is defined by the SLEEP bit. Voltage reference is OFF between conversions.
1 : FASTWAKEUP
Fast wake-up after sleep mode: voltage reference is kept ON between conversions; DAC core is OFF
End of enumeration elements list.
ONE : Must Be Set to 1
bits : 8 - 8 (1 bit)
access : read-write
REFRESH : Automatic Refresh Period
bits : 8 - 15 (8 bit)
access : read-write
USER_SEL : User Channel Selection
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : CHANNEL0
Channel 0
1 : CHANNEL1
Channel 1
End of enumeration elements list.
TAG : Tag Selection Mode
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DIS
Tag selection mode disabled. Using USER_SEL to select the channel for the conversion.
1 : EN
Tag selection mode enabled
End of enumeration elements list.
MAXS : Max Speed Mode
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Normal mode
1 : MAXIMUM
Maximum speed mode enabled
End of enumeration elements list.
STARTUP : Startup Time Selection
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x0 : 0
0 periods of DACClock
0x1 : 8
8 periods of DACClock
0x2 : 16
16 periods of DACClock
0x3 : 24
24 periods of DACClock
0x4 : 64
64 periods of DACClock
0x5 : 80
80 periods of DACClock
0x6 : 96
96 periods of DACClock
0x7 : 112
112 periods of DACClock
0x8 : 512
512 periods of DACClock
0x9 : 576
576 periods of DACClock
0xA : 640
640 periods of DACClock
0xB : 704
704 periods of DACClock
0xC : 768
768 periods of DACClock
0xD : 832
832 periods of DACClock
0xE : 896
896 periods of DACClock
0xF : 960
960 periods of DACClock
0x10 : 1024
1024 periods of DACClock
0x11 : 1088
1088 periods of DACClock
0x12 : 1152
1152 periods of DACClock
0x13 : 1216
1216 periods of DACClock
0x14 : 1280
1280 periods of DACClock
0x15 : 1344
1344 periods of DACClock
0x16 : 1408
1408 periods of DACClock
0x17 : 1472
1472 periods of DACClock
0x18 : 1536
1536 periods of DACClock
0x19 : 1600
1600 periods of DACClock
0x1A : 1664
1664 periods of DACClock
0x1B : 1728
1728 periods of DACClock
0x1C : 1792
1792 periods of DACClock
0x1D : 1856
1856 periods of DACClock
0x1E : 1920
1920 periods of DACClock
0x1F : 1984
1984 periods of DACClock
0x20 : 2048
2048 periods of DACClock
0x21 : 2112
2112 periods of DACClock
0x22 : 2176
2176 periods of DACClock
0x23 : 2240
2240 periods of DACClock
0x24 : 2304
2304 periods of DACClock
0x25 : 2368
2368 periods of DACClock
0x26 : 2432
2432 periods of DACClock
0x27 : 2496
2496 periods of DACClock
0x28 : 2560
2560 periods of DACClock
0x29 : 2624
2624 periods of DACClock
0x2A : 2688
2688 periods of DACClock
0x2B : 2752
2752 periods of DACClock
0x2C : 2816
2816 periods of DACClock
0x2D : 2880
2880 periods of DACClock
0x2E : 2944
2944 periods of DACClock
0x2F : 3008
3008 periods of DACClock
0x30 : 3072
3072 periods of DACClock
0x31 : 3136
3136 periods of DACClock
0x32 : 3200
3200 periods of DACClock
0x33 : 3264
3264 periods of DACClock
0x34 : 3328
3328 periods of DACClock
0x35 : 3392
3392 periods of DACClock
0x36 : 3456
3456 periods of DACClock
0x37 : 3520
3520 periods of DACClock
0x38 : 3584
3584 periods of DACClock
0x39 : 3648
3648 periods of DACClock
0x3A : 3712
3712 periods of DACClock
0x3B : 3776
3776 periods of DACClock
0x3C : 3840
3840 periods of DACClock
0x3D : 3904
3904 periods of DACClock
0x3E : 3968
3968 periods of DACClock
0x3F : 4032
4032 periods of DACClock
End of enumeration elements list.
Analog Current Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IBCTLCH0 : Analog Output Current Control
bits : 0 - 1 (2 bit)
access : read-write
IBCTLCH1 : Analog Output Current Control
bits : 2 - 3 (2 bit)
access : read-write
IBCTLDACCORE : Bias Current Control for DAC Core
bits : 8 - 9 (2 bit)
access : read-write
Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protection KEY
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x444143 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
End of enumeration elements list.
Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protection Violation Source
bits : 8 - 15 (8 bit)
access : read-only
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